materials challenges for 3d tsv integration -...

NANOANALYSISNANOANALYSIS

Materials Challenges for 3D TSV Integration

Ehrenfried Zschech1, Jürgen Wolf2, Peter Schneider3

1 Fraunhofer IZFP-D Dresden

2 Fraunhofer IZM-ASSID Dresden

3 Fraunhofer IIS-EAS Dresden

Dresden Fraunhofer Cluster Nanoanalysis

Dresden, Germany

www.nanoanalysis.fraunhofer.de

Dresden, 11 October 2012

http://www.nanoanalysis.fraunhofer.de/


Performance Power loss reduction Multifunctionality Form factor Cost reduction

Integration density

Signal propagation time

Partitioning

Power density Multi Device Integration Sensor, Transceiver, MPU, GPU, Memory

Mobile Communication

ID cards

Heterogeneous integration: Driving forces


Design, manufacturing and analysis – Challenged by new materials!

Design

Manufacturing Analytics

Performance s imulation

Process optimization

Materials characterization

Design centering

Failure analys is

Reliability studies

Architectural Design


3D Through Silicon Via (TSV) integration scheme

Tier 1 Thickness ~ 50 µm

Active Face Down

BackSide Metal Pitch ~ 5-25 µm

Package Substrate Thickness ~ 180 µm

Underfill Gap ~ 80 µm

Flip Chip Bump Size ~ <100 um

Pitch ~ 100-200 um

TSV Size ~ 5-10 µm

Pitch ~ 10-50 µm

BGA Bump Pitch ~ 0.65 mm

Height ~ 300 um

Graphics adapted from R. Radojcic, Qualcomm

µ-Bump Pitch ~ 25-50 µm

Underfill Gap ~ 20 µm

Tier 2 Thickness ~ 260 µm

Active Face Down

Assumptions

• Memory to logic is fine pitch 40~50µm.

• Logic to substrate pitch >100 µm.

• Logic die size may be smaller than

wide I/O DRAM size

• Memory TSV die or cube being

sourced from memory suppliers

• 4L substrate

• Compression molding

memory

memory

memory

memory

Logic

• Supports digital low power / mobile

• Tier 2 could be a single die or a 4-tier

Wide IO DRAM

• Extendible to ≥ 2 tiers

• Tier 2 thicknesses ~50 µm, with

microbumps on front and back sides

MCC ~ 100 µm


Via material,

diameter

Barrier layer

material

Insulation liner

material and

thickness

TSV array

pitch, height

Silicon crystal

orientation, P/N

Cu TSV in silicon wafer

Xiaopeng Xu, Synopsys


2D stress solution of single TSV

(mm) (MPa)

Shear Stress sxy

Normal Stress sx

Infinite Si matrix

0

)1(2

2

zSi

rzSi

zSi

Sir

Si

r

R

v

TE

sss

ss

TSV:

radius R θ

r

Stress in Si

Stresses controlled by CTE

mismatch between TSV and Si;

via size, material and T important.

x y

No elastic mismatch between Si and Cu

P. S. Ho, UT Austin/TX


Expansion

Contraction

• Reliability Via material,

diameter

Barrier layer

material

Insulation liner

material and

thickness

TSV array

pitch, height

• Mobility change

- Radial tension

- Circumferential

compression

T > 0

T < 0

TSV extrusion and de-lamination - P. Ho, RTI 3D Symposium 2009

Performance shifting due to TSV stress - IMEC, VLSI 2010

Silicon crystal

orientation, P/N

TSV performance and reliability risks



Impact on TSV induced stress and transistor performance

(A): SXX [Pa] for isotropic

copper

(B): SXX [Pa] for anisotropic

copper

Thermo-mechanical stress

(A): P-mobility change [%]

for isotropic copper

(B): P-mobility change [%]

for anisotropic copper

7%

7%

-7% -7%

Carrier mobility variation

(A): N-mobility change along

x-axis

(B): P-mobility change along

x-axis

(C): N-mobility change along

y-axis

(D): P-mobility change along

y-axis

0

1

2

3

4

5

6

0.0 2.5 5.0 7.5 10.0 12.5

N-M

ob

ilit

y c

ha

ng

e [%

]

Distance along x-axis [mm]

isotropic

anisotropic

-50

-40

-30

-20

-10

0

0.0 2.5 5.0 7.5 10.0 12.5

P-M

ob

ilit

y c

han

ge

[%]

Distance along x-axis [mm]

isotropic

anisotropic

-4

-3

-2

-1

0

1

0.0 2.5 5.0 7.5 10.0 12.5

N-M

ob

ilit

y C

han

ge

[%]

Distance along y-axis [mm]

isotropic

anisotropic0

10

20

30

40

50

0.0 2.5 5.0 7.5 10.0 12.5

P-M

ob

ilit

y C

han

ge

[%]

Distance along y-axis [mm]

isotropic

anisotropic

Cu anisotropy significantly alters the carrier mobility variation.

A. P. Karmakar, X. Xu, K. B. Yeap, E. Zschech, IEEE DMR 12, 225 – 232 (2012),

Collaboration with Synopsis Inc. (TCAD simulation)


Performance assessment for 3D IC systems

Layout and process

information

Experiment

Materials properties

Performance

analysis

for 3D systems

Physics-based

model

Process Simulation /

Finite Element Analysis

Experiment

Model verification

E. Zschech et al., MRS Spring 2012


Layout and process

information

Experiment

Materials properties

Performance

analysis

for 3D systems

Physics-based

model

Process Simulation /

Finite Element Analysis

Experiment

Model verification

Strain measurement in

transistor channels Multi-scale

(thermo)mechanical

properties of materials

Multi-scale materials

characterization

E. Zschech et al., MRS Spring 2012

Performance assessment for 3D IC systems


Needed materials data: Packaging materials

Ma

teri

als

Tem

pe

ratu

re

de

pe

nd

en

t

Un

de

rfil

l

Cu

pil

lars

Mo

ldin

g

com

po

un

d

Fli

p-C

hip

ba

ll

(~ 1

00

µm

)

Mic

ro b

all

(

10

s o

f µ

m)

BG

A b

um

p

(>2

00

µm

)

Eff

ect

ive

in

terc

on

ne

ct

(lo

w-k

/Cu

)

Eff

ect

ive

b

ulk

o

f si

lico

n d

ie

(Si/

Cu

-TS

V)

Eff

ect

ive

p

ack

ag

e

sub

stra

te

(PC

B/C

u)

CTE (ppm/K) yes x x x x x x x x x

Young’s modulus (GPa)

yes x x x x x x x x x

Poisson’s ratio no x x x x x x x x x

Plasticity (MPa) yes x

Visco-plasticity (MPa)

yes x x x

Visco-elasticity (MPa)

yes x x x

Glass transition Tg (°C)

no x

Die attach Ta (°C) no x x x x


Needed materials data: Wafer-level materials

Materials Cu

(BEoL) ULK Cu (TSV)

SiO2 Liner

Barrier Si BRDL

CTE (ppm/K) x x x x x

Young’s modulus (GPa)

x x x x x x x

Plasticity (MPa) x x

Poisson’s ratio x x x x x x x


Model validation and calibration: Electrical vs. physical measurements

13

Electrical measurements: Ion, Vt, etc.

- Fast & accurate measurements

- Specially designed test-chip is needed –

expensive & time consuming

- Stress variation is not responsible for total

variation in electrical characteristics.

Other sources of variability should be accounted:

- sub-wavelength lithography

- random dopant fluctuation

- temperature fluctuation, etc.

Strain measurements inside

transistor silicon channel

- Direct but time consuming

measurements

- No test chip is needed

SiGe

NMOS PMOS

Stress Memory

electrons tensile holes compressive


High global strain in 3D TSV stacked structures requires new approach for preparation of TEM lamellae

2. 3.

Grinding and polishing with SiC paper to reduce sample size, polishing direction indicated.

Sample holder

4.

Cu Grid

5.

Gluing the specimen to a Cu half ring.

Chemical isolation of Tier 1 + Tier 2, mechanical removal of bumps, and gluing of a Si dummy wafer with epoxy to tier 1.

Tier 1

Dummy

ROI

1.

U. Mühle, Y. Ritz,

Fraunhofer IZFP Dresden


TEM dark-field holography is the technique of choice for strain analysis: Final strain map

For strain free Reference: Combine with point measurements by CBED

Deviation provides the strain map, overlay to TEM bright-field image

FOV CBED

U. Mühle, Fraunhofer IZFP Dresden


Thermal stress induced TSV pop-up

T > 0 T < 0

Shear Stress (MPa)

Large shear stress at TSV-silicon interface leads to de-bonding

Expansion Contraction



• Tomography of 4μm and 5μm TSVs

X-ray nanotomography @ TSVs: Nondestructive observation of damage mechanisms and failures


Materials data and characterization techniques needed

- Which MATERIALS DATA is needed, what needs to be measured?

- Input data for simulation - Model validation (and calibration)

- Which CHARACTERIZATION TECHNIQUES are needed?

- Multi-scale (thermo-)mechanical materials data - Strain in transistor channel

3D TSV technology and products: Process and materials characterization for performance and reliability

Metrology and failure analysis

- Which ANALYSIS TECHNIQUES are needed? - In-line: Optical, acoustic and X-ray techniques - FA Lab: SEM/FIB/TEM, nano X-ray tomography - Materials properties: FPB/DCB, Nanoindentation, AFM-based techniques, TEM (EEDX/EELS, CBED, …)


Summary: Materials challenges for 3D IC integration

3D chip stacking (new design, processes and materials) provides challenges to materials science and engineering.

Both performance and reliability requirements of microelectronic systems require multi-scale stress engineering (modeling + experiment).

3D chip stacking requires advanced techniques for process development, process control and quality control / failure analysis.

This decade is the decade of materials science in semiconductor industry!


Thank you!

< 100nm >

Picture: Novaled Picture: Fraunhofer IPMS Picture: GLOBALFOUNDRIES

Uwe Mühle, Jürgen Gluch, Rüdiger Rosenkranz, Yvonne Ritz, Kong Boon Yeap, Christoph Sander Fraunhofer IZFP Dresden Riko Radojcic, Qualcomm Valeriy Sukharev, Mentor Graphics Xiaopeng Xu, Synopsis Paul S. Ho, UT Austin/TX

www.nanoanalysis.fraunhofer.de

Contact: [email protected]

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