mb91f355a/f353a/f356b/355a/354a/ mb91353a/352a ......*: purchase of fujitsu i 2c components conveys...

DS07-16503-3EFUJITSU SEMICONDUCTORDATA SHEET

32-Bit Proprietary MicrocontrollerCMOS

FR60 MB91350A SeriesMB91F355A/F353A/F356B/355A/354A/MB91353A/352A/351A/V350A■ DESCRIPTION

The FR families are lines of standard single-chip microcontrollers each based on a 32-bit high-performance RISCCPU, incorporating a variety of I/O resources and bus control features for embedded control applications whichrequire high CPU performance for high-speed processing.

This FR60 is based on FR30 and FR40 CPU and enhanced bus access. The FR60 is a line of single-chip orientedmicrocontrollers incorporating a wealth of peripheral resources.

The FR60 family is optimized for embedded control applications requiring high processing power of the CPU,such as DVD player, navigation, high performance Fax machine, and printer controls.

■ FEATURES1. FR CPU

• 32-bit RISC, load/store architecture with a five-stage pipeline• Maximum operating frequency: 50 MHz (using the PLL at an oscillation frequency of 12.5 MHz)• 16-bit fixed length instructions (basic instructions), 1 instruction per cycle• Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift

etc.• Instructions adapted for high-level languages : Function entry/exit instructions, multiple-register load/store in-

structions• Register interlock functions: Facilitating coding in assemblers

(Continued)

Copyright©2003-2006 FUJITSU LIMITED All rights reserved

“Check Sheet” is seen at the following support pageURL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.

Be sure to refer to the “Check Sheet” for the latest cautions on development.

MB91350A Series

2

• On-chip multiplier supported at the instruction level. Signed 32-bit multiplication: 5 cyclesSigned 16-bit multiplication: 3 cycles

• Interrupt (PC, PS save): 6 cycles, 16 priority levels• Harvard architecture allowing program access and data access to be executed simultaneously

2. Bus interface• Maximum operating frequency: 25 MHz• 24-bit address full output (16M bytes space) capability

(21-bit address full output (2M bytes space) capability: MB91F353A/353A/352A/351A)• 8,16-bit data output• Built-in pre-fetch buffer• Non-used data and address pin are usable as general I/O port.• Capable of chip-select signal output for completely independent four areas settable in 64K bytes minimum• Support for various memory interfaces:

SRAM, ROM/Flashpage mode Flash ROM, page mode ROM interface

• Basic bus cycle : 2 cycles• Programmable automatic wait cycle generator capable of inserting wait cycles for each area• RDY input for external wait cycles• DMA support of fly-by transfer capable of wait control for independent I/O

(The MB91F353A/353A/352A/351A does not support fly-by transfer.)

3. Mounted memory

4. DMAC (DMA Controller) • Capable of simultaneous operation of up to 5 channels (external → external: 3 channels)• 3 transfer sources (external pin/internal peripheral or software):

Activation sources are software-selectable (transfer can be activated by UART0/1/2).• Addressing using 32-bit full addressing mode (increment, decrement, fixed)• Transfer modes (demand transfer, burst transfer, step transfer, block transfer)• Fly-by transfer support (external I/O and between memories)• Selectable transfer data size: 8, 16, or 32-bit• Multi-byte transfer enabled (by software)• DMAC descriptor in IO areas (200H to 240H, 1000H to 1024H)

(The MB91F353A/353A/352A/351A does not have an external interface.)External pin transfer is not supported. Demand transfer and fly-by transfer cannot be used.

5. Bit search module (for REALOS)• Search for the position of the bit 1/0-changed first in 1 word from the MSB

(Continued)

D-bus memory MB91V350A MB91F353AMB91F355A MB91F356BMB91353AMB91355A

MB91352AMB91354A MB91351A

ROM No 512 KB 256 KB 512 KB 384 KB 384 KB

RAM (stack) 16 KB 16 KB 16 KB 16 KB 8 KB 16 KB

RAM (Execute instruction) 16 KB 8 KB 8 KB 8 KB 8 KB 8 KB

MB91350A Series

6. Various timers• 4 channels of 16-bit reload timer (including 1 channel for REALOS) :

Internal clock frequency selectable from among divisions by 2/8/32 (division by 64/128 selectable only for ch.3)• 16-bit free-running timer : 1 channel.

Output compare : 8 channels (MB91F353A/353A/352A/351A: 2 channels) Input capture : 4 channels.

• 16-bit PPG timer : 6 channels (MB91F353A/353A/352A/351A: 3 channels)

7. UART• UART Full duplex double buffer: 5 channels (MB91F353A/353A/352A/351A: 4 channels)• Selectable parity On/Off• Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable• Internal timer for dedicated baud rate• External clock can be used as transfer clock• Assorted error detection functions (for parity, frame, and overrun errors)• Support for 115 Kbps

8. SIO• 8-bit data serial transfer: 3 channels (MB91F353A/353A/352A/351A: 2 channels)• Shift clock selectable from among internal three and external one• Shift direction selectable (transfer from LSB or MSB) selectable

9. Interrupt controller• Total number of external interrupts: 17 (MB91F353A/353A/352A/351A: 9)

(One non-maskable interrupt pin and 16/8 ordinary interrupt pins that can be used for wakeup in stop mode.) • interrupt from internal peripheral• Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt

10. D/A converter• 8-bit resolution: 3 channels (MB91F353A/353A/352A/351A: 2 channels)

11. A/D converter• 10-bit resolution: 12 channels (MB91F353A/353A/352A/351A: 8 channels)• Casting time for serial/parallel conversion: 1.48 µs• Conversion mode (single conversion mode, continuous conversion mode)• Activation source (software, external trigger, peripheral interrupt)

12. Other interval timer/counter• 8/16-bit up/down counter

The MB91F353A/353A/352A/351A supports only an 8-bit up/down counter.• 16-bit timer (U-TIMER): 5 channels (MB91F353A/353A/352A/351A: 4 channels)• Watch dog timer

13. I2C bus interface* (400 kbps supported)• 1 channel master/slave sending and receiving• Arbitration and clock synchronization

14. I/O port• 3 V I/O ports

(5 V input is supported for those ports that are also used for external interrupts (16 ports, MB91F353A/353A/352A/351A: 8 ports).

• Up to 126 ports (MB91F353A/353A/352A/351A: Up to 84 ports)(Continued)

3

MB91350A Series

4

(Continued)

15. Other features• Internal oscillator circuit as clock source, allowing PLL multiplication to be selected• Provided with INIT as a reset pin (The CPU operates without oscillation stabilization wait interval when the

INIT pin is reset.)• others, watch-dog timer reset, software reset enable• Support for stop and sleep modes for low power consumption, capable of saving power during CPU operation

at 32 kHz.• Gear function• Built-in time base timer• Package: MB91F355A/F356B/355A/354A: LQFP-176 (lead pitch 0.50 mm)

MB91F353A/353A/352A/351A: LQFP-120 (lead pitch 0.50 mm)• CMOS technology(0.35 µm)• Power supply voltage: 3.3 V ± 0.3 V

*: Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these compo-nents in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.

MB91350A Series

■ PIN ASSIGNMENTS• MB91F353A/353A/352A/351A

(TOP VIEW)

(FPT-120P-M21)

123456789101112131415161718192021222324252627282930

P20/D16P21/D17P22/D18P23/D19P24/D20P25/D21P26/D22P27/D23P30/D24P31/D25P32/D26P33/D27P34/D28P35/D29P36/D30P37/D31P40/A00

VSSVCC

P41/A01P42/A02P43/A03P44/A04P45/A05P46/A06P47/A07P50/A08P51/A09P52/A10P53/A11

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

P54

/A12

P55

/A13

P56

/A14

P57

/A15

P60

/A16

P61

/A17

P62

/A18

P63

/A19

P64

/A20 VS

S

PL1

/SC

LP

L0/S

DA

VS

S

VC

C

P80

/IN0/

RD

YP

81/IN

1/B

GR

NT

P82

/IN2/

BR

QP

83/R

DP

84/W

R0

P85

/IN3/

WR

1N

MI

MD

2M

D1

MD

0IN

ITV

CC

X1

X0

VS

S

X0A

AN

7A

N6

AN

5A

N4

AN

3A

N2

AN

1A

N0

VS

S

AV

SS/A

VR

LA

VR

HA

VC

C

DA

VC

DA

VS

DA

0D

A1

PH

5/S

CK

3P

H4/

SO

3P

H3/

SI3

PH

2/S

CK

2P

H1/

SO

2P

H0/

SI2

PO

2/O

C2

PO

0/O

C0

VS

S

VC

C

PI5

/SC

K1

PI4

/SO

1P

I3/S

I1P

I2/S

CK

0

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100 99 98 97 96 95 94 93 92 91

PI1/SO0PI0/SI0PK7/INT7/ATGPK6/INT6/FRCKPK5/INT5PK4/INT4PK3/INT3PK2/INT2PK1/INT1PK0/INT0PM5/SCK7PM4/SO7/TRG4PM3/SI7/TRG3VCCVSSPM2/SCK6/ZIN0/TRG2PM1/SO6/BIN0/TRG1PM0/SI6/AIN0/TRG0PN4/PPG4PN2/PPG2PN0/PPG0PA3/CS3PA2/CS2PA1/CS1PA0/CS0P94/ASP93P91P90/SYSCLKX1A

908988878685848382818079787776757473727170696867666564636261

5

MB91350A Series

6

• MB91F355A/F356B/355A/354A

(TOP VIEW)

(FPT-176P-M02)

133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176

PG5/SCK5NMIX1AVSSX0AMD2MD1MD0

X0VCCX1

INITVSSVCC

PC0/DREQ2PC1/DACK2

PC2/DSTP2/DEOP2PB0/DREQ0PB1/DACK0

PB2/DSTP0/DEOP0PB3/DREQ1PB4/DACK1

PB5/DSTP1/DEOP1PB6/IOWRPB7/IORDPA0/CS0PA1/CS1PA2/CS2PA3/CS3

VSSVCC

P80/IN0/RDYP81/IN1/BGRNT

P82/IN2/BRQP83/RD

P84/WR0P85/IN3/WR1P90/SYSCLK

P91P92/MCLK

P93P94/AS

VSSVCC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

P20

/D16

P21

/D17

P22

/D18

P23

/D19

P24

/D20

P25

/D21

P26

/D22

P27

/D23

P30

/D24

P31

/D25

P32

/D26

P33

/D27

P34

/D28

P35

/D29

P36

/D30

P37

/D31 VS

SV

CC

P40

/A00

P41

/A01

P42

/A02

P43

/A03

P44

/A04

P45

/A05

P46

/A06

P47

/A07

P50

/A08

P51

/A09

P52

/A10

P53

/A11

P54

/A12

P55

/A13

P56

/A14

P57

/A15 VS

SV

CC

P60

/A16

P61

/A17

P62

/A18

P63

/A19

P64

/A20

P65

/A21

P66

/A22

P67

/A23

PG

4/S

O5

PG

3/S

I5P

G2/

SC

K4

PG

1/S

O4

PG

0/S

I4P

H5/

SC

K3

PH

4/S

O3

PH

3/S

I3P

H2/

SC

K2

PH

1/S

O2

PH

0/S

I2P

I5/S

CK

1P

I4/S

O1

PI3

/SI1

PI2

/SC

K0

PI1

/SO

0P

I0/S

I0V

CC

VS

SP

J7/IN

T15

PJ6

/INT

14P

J5/IN

T13

PJ4

/INT

12P

J3/IN

T11

PJ2

/INT

10P

J1/IN

T9

PJ0

/INT

8P

K7/

INT

7/A

TG

PK

6/IN

T6/

FR

CK

PK

5/IN

T5

PK

4/IN

T4

PK

3/IN

T3

PK

2/IN

T2

PK

1/IN

T1

PK

0/IN

T0

VC

CV

SS

PL1

/SC

LP

L0/S

DA

VS

SP

M5/

SC

K7/

ZIN

1/T

RG

5P

M4/

SO

7/B

IN1/

TR

G4

PM

3/S

I7/A

IN1/

TR

G3

PM

2/S

CK

6/Z

IN0/

TR

G2

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100 99 98 97 96 95 94 93 92 91 90 89

PM1/SO6/BIN0/TRG1PM0/SI6/AIN0/TRG0PN5/PPG5PN4/PPG4PN3/PPG3PN2/PPG2PN1/PPG1PN0/PPG0VCCVSSPO7/OC7PO6/OC6PO5/OC5PO4/OC4PO3/OC3PO2/OC2PO1/OC1PO0/OC0PP3/TOT3PP2/TOT2PP1/TOT1PP0/TOT0VCCVSSAVSS/AVRLAVRHAVCCAN11AN10AN9AN8AN7AN6AN5AN4AN3AN2AN1AN0DA2DA1DA0DAVCDAVS

8887868584838281807978777675747372717069686766656463626160595857565554535251504948474645

MB91350A Series

■ PIN DESCRIPTION

(Continued)

Pin no.Pin name

I/O circuit type*3

FunctionLQFP*1 LQFP*2

1 to 8 1 to 8D16 to D23

C

Bits 16 to bit 23 of the external data bus.Valid only in external bus mode.

P20 to P27 Can be used as a port in external bus 8-bit mode.

9 to 16 9 to 16D24 to D31

C

Bits 24 to bit 31 of the external data bus.Valid only in external bus mode.

P30 to P37 Can be used as a port in single-chip mode.

19 to 26 17, 20 to 26A00 to A07

C

Bits 0 to bit 7 of the external address bus.Valid only in external bus mode.


27 to 34 27 to 34A08 to A15

C



37 to 41 35 to 39

A16 to A20

C


P60 to P64Can be used as a port in single-chip mode or when an external address bus is not used.

42 to 44 -

A21 to A23

C


P65 to P67Can be used as a port in single-chip mode or when an external address bus is not used.

47, 48 106,105 DA0, DA1 - D/A converter output pin

49 - DA2 - D/A converter output pin

50 to 57 113 to 120 AN0 to AN7 G Analog input pin

58 to 61 - AN8 to AN11 G Analog input pin

67 to 70 -

TOT0 to TOT3

D

Reload timer output ports.This function is valid when timer output is enabled.

PP0 to PP3General-purpose I/O ports.This function is valid when the timer output function is disabled.

71 97

OC0

D

Output compare output pin

PO0General-purpose I/O port.This function can be used as a port when output compare output is not used.

7

MB91350A Series

8

(Continued)

Pin no.Pin name

I/O circuit type*3


72 -

OC1

D



73 98

OC2

D



74 to 78 -

OC3 to OC7

D

Output compare output pins

PO3 to PO7General-purpose I/O ports.This function can be used as a port when output compare output is not used.

81 70

PPG0

D

PPG timer output pin

PN0General-purpose I/O port.This function can be used as a port when PPG timer output is not used.

82 -

PPG1

D



83 71

PPG2

D



84 -

PPG3

D



85 72

PPG4

D



86 -

PPG5

D



MB91350A Series

(Continued)

Pin no.Pin name

I/O circuit type*3


87 73

SI6

D

Data input for serial I/O6.Since this input is always used when serial I/O6 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation.

AIN0

Input for the up/down counter.Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation.

TRG0

External trigger input for PPG timer 0.Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation.

PM0General-purpose I/O port.This function can be used as a port when serial I/O, up/down counter, and PPG timer output are not used.

88 74

SO6

D

Data output from serial I/O6.This function is valid when data output from serial I/O6 is allowed.

BIN0


TRG1



89 75

SCK6

D

Clock I/O for serial I/O6.This function is valid when clock output from serial I/O6 is allowed or when external shift clock input is used.

ZIN0


TRG2



9

MB91350A Series

10

(Continued)

Pin no.Pin name

I/O circuit type*3


90 78

SI7

D


AIN1*4


TRG3



91 79

S07

D

Data output from serial I/O7.This function is valid when data output from serial I/O7 is allowed.

BIN1*4


TRG4



92 80

SCK7

D

Clock I/O for serial I/O7.This function is valid when clock output from serial I/O7 is allowed or when external shift clock input is used.

ZIN1*4


TRG5*4



MB91350A Series

(Continued)

Pin no.Pin name

I/O circuit type*3


94 42

SDA

F

DATA I/O pin for the I2C bus.This function is valid when the I2C is allowed to operate in standard mode.Output using the port must be stopped beforehand unless this operation is intended (open drain output).

PL0General-purpose I/O port.This function can be used as a port when I2C operation is not allowed (open drain output).

95 41

SCL

F

Clock I/O pin for the I2C bus.This function is valid when the I2C is allowed to operate in standard mode.Output using the port must be stopped beforehand unless this operation is intended (open drain output).

PL1General-purpose I/O port.This function can be used as a port when I2C operation is not allowed (open drain output).

98 to 103 81 to 86INT0 to INT5

E

External interrupt input.Since this input is always used when the corresponding exter-nal interrupt is allowed, output using the port must be stopped beforehand unless this operation is the intended operation.

PK0 to PK5 General-purpose I/O ports

104 87

INT6

E


FRCK

External clock input pin for the free-running timer.Since this input is always used when it is selected as external clock input for the free-running timer, output using the port must be stopped beforehand unless this operation is the intended operation.

PK6 General-purpose I/O port

105 88

INT7

E


ATG

External trigger for the A/D converter.Since this input is always used when it is selected as the source of A/D activation, output using the port must be stopped beforehand unless this operation is the intended operation.

PK7 General-purpose I/O port

11

MB91350A Series

12

(Continued)

Pin no.Pin name

I/O circuit type*3


106 to 113 -INT8 to INT15

E


PJ0 to PJ7 General-purpose I/O ports

116 89SI0

D

Data input for UART0.Since this input is always used when UART0 input is operat-ing, output using the port must be stopped beforehand unless this operation is the intended operation.

PI0 General-purpose I/O port

117 90SO0

D

Data output from UART0.This function is valid when UART0 data output is allowed.

PI1General-purpose I/O port.This function is valid when UART0 data output is not allowed.

118 91

SCK0

D

Clock I/O for UART0.This function is valid when UART0 clock output is allowed or when external clock input is used.

PI2General-purpose I/O port.This function is valid when UART0 clock output is not allowed or when external clock input is not used.

119 92SI1

D

Data input for UART1.Since this input is always used when UART1 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation.

PI3 General-purpose I/O port

120 93SO1

D


PI4General-purpose I/O port.This function is valid when UART1 data output is not allowed.

121 94

SCK1

D


PI5General-purpose I/O port.This function is valid when UART1 clock output is not allowed or when external clock input is not used.

122 99SI2

D


PH0 General-purpose I/O port

MB91350A Series

(Continued)

Pin no.Pin name

I/O circuit type*3


123 100

SO2

D


PH1General-purpose I/O port.This function is valid when UART2 data output is not allowed or when external shift clock input is used.

124 101

SCK2

D


PH2General-purpose I/O port.This function is valid when UART2 clock output is not allowed or when external clock input is not used.

125 102SI3

D


PH3 General-purpose I/O port

126 103

SO3

D


PH4General-purpose I/O port.This function is valid when UART3 data output is not allowed.

127 104

SCK3

D


PH5General-purpose I/O port.This function is valid when UART3 clock output is not allowed or when external clock input is not used.

128 -SI4

D


PG0 General-purpose I/O port

129 -

SO4

D

Data output from UART4.This function is valid when serial I/O4 data output is allowed.

PG1General-purpose I/O port.This function is valid when serial I/O4 data output is not allowed.

13

MB91350A Series

14

(Continued)

Pin no.Pin name

I/O circuit type*3


130 -

SCK4

D

Clock I/O for UART4.This function is valid when serial I/O4 clock output is allowed or when external clock input is used.

PG2General-purpose I/O port.This function is valid when serial I/O4 clock output is not allowed or when external clock input is not used.

131 -SI5

D


PG3 General-purpose I/O port

132 -

SO5

D

Data output from serial I/O5.This function is valid when serial I/O5 data output is allowed.

PG4General-purpose I/O port.This function is valid when serial I/O5 data output is not allowed.

133 -

SCK5

D

Clock I/O for serial I/O5.This function is valid when serial I/O5 clock output is allowed or when external shift clock input is used.

PG5General-purpose I/O port.This function is valid when serial I/O5 clock output is not allowed or when external clock input is not used.

134 51 NMI H NMI (non-maskable interrupt) input

135 61 X1A B Clock (oscillation) output (subclock)

137 60 X0A B Clock (oscillation) input (subclock)

138 to 140 52 to 54 MD2 to MD0

H Mode pins 2 to 0.These pins set the basic operating mode. Connect the pins to VCC or VSS.Input circuit type:The production version (mask ROM version) is the "H" type.The flash ROM version is the "J" type.

J

141 58 X0 A Clock (oscillation) input (main clock)

143 57 X1 A Clock (oscillation) output (main clock)

144 55 INIT I External reset input

147 -DREQ2

C

DMA external transfer request input.Since this input is always used when it is selected as the source of DMA activation, output using the port must be stopped beforehand unless this operation is the intended operation.

PC0 General-purpose I/O port

MB91350A Series

(Continued)

Pin no.Pin name

I/O circuit type*3


148 -

DACK2

C

DMA external transfer request acceptance output.This function is valid when DMA transfer request acceptance output is allowed.

PC1General-purpose I/O port.This function is valid when DMA transfer request acceptance output is allowed.

149 -

DEOP2

C

DMA external transfer end output.This function is valid when DMA external transfer end output is allowed.

DSTP2DMA external transfer stop input.This function is valid when DMA external transfer stop input is allowed.

PC2General-purpose I/O port.This function is valid when DMA external transfer end output and external transfer stop input are not allowed.

150 -DREQ0

C


PB0 General-purpose I/O port

151 -

DACK0

C


PB1General-purpose I/O port.This function is valid when DMA transfer request acceptance output is not allowed.

152 -

DEOP0

C



PB2General-purpose I/O port.This function is valid when DMA external transfer end output and external transfer stop input are not allowed.

153 -DREQ1

C


PB3 General-purpose I/O port.

15

MB91350A Series

16

(Continued)

Pin no.Pin name

I/O circuit type*3


154 -

DACK1

C


PB4General-purpose I/O port.This function is valid when DMA external transfer request acceptance output is not allowed.

155 -

DEOP1

C



PB5General-purpose I/O port.This function is valid when DMA external transfer end output and external transfer stop input are not allowed.

156 -

IOWR

C

Write strobe output for DMA fly-by transfer.This function is valid when write strobe output for DMA fly-by transfer is allowed.

PB6General-purpose I/O port.This function is valid when write strobe output for DMA fly-by transfer is not allowed.

157 -

IORD

C

Read strobe output for DMA fly-by transfer.This function is valid when read strobe output for DMA fly-by transfer is allowed.

PB7General-purpose I/O port.This function is valid when read strobe output for DMA fly-by transfer is not allowed.

158 66

CS0

C

Chip select 0 output.This function is valid in external bus mode.

PA0General-purpose I/O port.This function is valid in single-chip mode.

159 67

CS1

C

Chip select 1 output.This function is valid when chip select 1 output is allowed.

PA1General-purpose I/O port.This function is valid when chip select 1 output is not allowed.

160 68

CS2

C



MB91350A Series

(Continued)

Pin no.Pin name

I/O circuit type*3


161 69

CS3

C



164 45

RDY

D

External ready input.This function is valid when external ready input is allowed.

IN0

Input capture input pin.Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation.

P80General-purpose I/O port.This function is valid when external ready input is not allowed.

165 46

BGRNT

D

External bus open acceptance output.The “L” level is output when the external bus is open.This function is valid when output is allowed.

IN1


P81General-purpose I/O port.This function is valid when external bus open acceptance is not allowed.

166 47

BRQ

D

External bus open request input.Input to the high level if you want to open the external bus.This function is valid when input is allowed.

IN2


P82General-purpose I/O port.This function is valid when external bus open request is not allowed.

167 48

RD

D

External bus read strobe output.This function is valid in external bus mode.

P83General-purpose I/O port.This function is valid in single-chip mode.

17

MB91350A Series

18

(Continued)

*1 : FPT-176P-M02

*2 : FPT-120P-M21

*3 : Refer to “■ I/O CIRCUIT TYPE” about I/O circuit type.

*4 : These functions are not supported for the FPT-120P-M21.

Pin no.Pin name

I/O circuit type*3


168 49

WR0

D

External bus write strobe output.This function is valid in external bus mode.

P84General-purpose I/O port.This function is valid in single-chip mode.

169 50

WR1

D

External bus write strobe output.This function is valid when WR1 output in external bus mode is allowed.

IN3

Input capture input pin.Since this input is always used when it is selected for input capture input, output using the port must be stopped before-hand unless this operation is the intended operation.

P85General-purpose I/O port.This function is valid when external bus write enable output is not allowed.

170 62

SYSCLK

C

System clock output.This function is valid when system clock output is allowed. A clock having the same frequency as the external bus operat-ing frequency is output (stopped in stop mode).

P90General-purpose I/O port.This function is valid when system clock output is not allowed.

171 63 P91 C General-purpose I/O port

172 -

MCLK

C

Memory clock output.This function is valid when memory clock output is allowed. A clock having the same frequency as the external bus operat-ing frequency is output (stopped in sleep mode).

P92General-purpose I/O port.This function is valid when memory clock output is not al-lowed.

173 64 P93 C General-purpose I/O port

174 65

AS

C

Address strobe output.This function is valid when address strobe output is allowed.

P94General-purpose I/O port.This function is valid when address load output is not allowed.

MB91350A Series

[Power supply and GND pins]

*1 : FPT-176P-M02

*2 : FPT-120P-M21

Pin numberPin name Function

LQFP*1 LQFP*2

17, 35, 65, 79, 93, 96, 114, 136, 145, 162, 175

18, 40, 43, 59, 76, 96, 112

VSSGND pins. Use the same potential for all pins.

18, 36, 66, 80, 97, 115, 142, 146, 163, 176

19, 44, 56, 77, 95

VCC3.3 V power supply pins. Use the same potential for all pins.

45 107 DAVS D/A converter GND pin

46 108 DAVC D/A converter power supply pin

62 109 AVCC A/D converter analog power supply pin

63 110 AVRH A/D converter reference power supply pin

64 111 AVSS/AVRL A/D converter analog GND pin

19

MB91350A Series

20

■ I/O CIRCUIT TYPE

(Continued)

Type Circuit type Remarks

A

• Oscillation feedback resistance: approx. 1 MΩ

B

• Oscillation feedback resistance forlow speed (subclock oscillation): approx. 7 MΩ

C

• CMOS level output• CMOS level input

With standby controlWith Pull-up control

D

• CMOS level output• CMOS level hysteresis input

With standby controlWith Pull-up control

X1

Standby control

X0

Clock input

X1A

Standby control

X0A

Clock input

Standby control

P-chP-ch

N-ch

Digital input

Digital output

Digital output

Pull-up control

Standby control

P-chP-ch

N-ch

Digital input

Digital output

Digital output

Pull-up control

MB91350A Series

(Continued)


E

• CMOS level output• CMOS level hysteresis input

With stand voltage of 5 V

F

• N-ch (Open drain input)• CMOS level hysteresis input

With standby controlWith stand voltage of 5 V

G

• Analog inputWith switch

H

CMOS level hysteresis input

I

• CMOS level hysteresis input

With pull-up resistor

P-ch

P-chN-ch

Digital input

Digital output

Digital output

Standby control

N-ch

Digital input

Digital output

Control

P-ch

N-ch

Analog input

P-ch

N-ch

Digital input

P-ch P-ch

Digital input

21

MB91350A Series

22

(Continued)


J

• CMOS level input• Flash product only

N-ch

N-ch

N-ch

N-ch

N-ch

Diffused resistorMode inputControl signal

MB91350A Series

■ HANDLING DEVICES• Preventing Latch-up

Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or outputpin or if an above-rating voltage is applied between VCC and VSS. A latch-up,if it occurs, significantly increasesthe power supply current and may cause thermal destruction of an element. When you use a CMOS IC, don’texceed the absolute maximum rating.

• Treatment of Unused Pins

Do not leave an unused input pin open, since it may cause a malfunction. Handle by using a pull-up or pull-down resistor.

• About Power Supply Pins

In products with multiple VCC and VSS pins, the pins of the same potential are internally connected in the deviceto avoid abnormal operations including latch-up. However, you must connect the pins to external power supplyand a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signalscaused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pinsnear this device.

• About Crystal Oscillator Circuit

Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the printed circuit boardso that X0, X1, X0A, X1A, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground arelocated close to the device as possible.

It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded byground plane because stable operation can be expected with such a layout.

Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.

• Notes on Using External Clock

When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock toX0 must be supplied to X1 pin. However, in this case the stop mode(oscillator stop mode) must not be used.(This is because the X1 pin stops at High level output in STOP mode.)

Using an external clock (normal)

• Clock Control Block

Take the oscillation stabilization wait time during Low level input to the INIT pin.

X0

X1

Note: STOP mode (oscillation stop mode) cannot be used.

MB91350A series

23

MB91350A Series

24

• Notes on Using the Sub Clock

When no oscillator is connected to the X0A and X1A pins, pull down the X0A pin and open the X1A pin.

Using an external clock (normal)

• Treatment of NC and OPEN Pins

Pins marked as NC and OPEN must be left open-circuit.

• About Mode Pins (MD0 to MD2)

These pins should be connected directly to VCC or VSS pin.

To prevent the device erroneously switching to test mode due to noise, design the printed circuit board suchthat the distance between the mode pins and VCC or VSS pin is short as possible and the connection impedanceis low.

• Operation at Start-up

The INIT pin must be at Low level when the power supply is turned on.

Immediately after the power supply is turned on, hold the Low level input to the INIT pin for the settling timerequired for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit. (For INITvia the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value.)

• About Oscillation Input at Power On

When turning the power on, maintain clock input until the device is released from the oscillation stabilizationwait state.

• Caution on Operations during PLL Clock Mode

On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops whilethe PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at itsself-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.

• External Bus Setting

This model guarantees an external bus frequency of 25 MHz.Setting the base clock frequency to 50 MHz with DIVR1 (external bus base clock division setting register)initialized sets the external bus frequency also to 50 MHz. Before changing the base clock frequency, set theexternal bus frequency not exceeding 25 MHz.

• MCLK and SYSCLK

MCLK and SYSCLK has a difference that MCLK stops in SLEEP/STOP mode but SYSCLK stops only in STOPmode. Use either depending on each application.Upon initialization, MCLK becomes invalid (PORT) and SYSCLK becomes valid. To use MCLK, set the portfunction register (PFR) to select the use of that clock.

X0

X1OPEN MB91350A series

MB91350A Series

• Pull-up Control

Connecting a pull-up resistor to the pin serving as an external bus pin cannot a guarantee the “■ ELECTRICALCHARACTERISTICS 4. AC Characteristics (4) Normal Bus Access Read/Write Operation, (5) Multiplex BusAccess Read/Write operation and (7) Hold Timing”.Even the port for which a pull-up resistor has been set is invalid in stop mode with HIZ = 1 or in hardware standbymode.

• Sub Clock Select

Immediately after switching from main clock mode to subclock mode for the clock source, insert at least oneNOP instruction.

• Bit Search Module

The BSD0, BSD1, and BDSC registers are accessed only in words.

• D-bus Memory

Do not allocate the code area in memory on the D-bus because no instruction fetch takes place to the D-bus.Executing an instruction fetch to the D-bus area causes wrong data to be interpreted as code, possibly lettingthe device to run out of control.

• Low Power Consumption Mode

To enter the sleep or stop mode, be sure to read the standby control register (STCR) immediately after writing to it.Precisely, use the following sequence.Set the I flag, ILM, and ICR to, after returning from standby mode, branch to the interrupt handler having causedthe device to return.

• Switch Shared Port Function

To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR). Note,however, that bus pins are switched depending on external bus settings.

• Pre-fetch

When accessing a prefetch-enabled little endian area, be sure to use word access (in 32-bit, word length) only.Byte or halfword access results in wrong data read.

(Idi #0x0b, r0) (Idi #_CLKR, r12) stb r0, @r12 // sub-clock mode nop // Must insert NOP instruction

(Idi #value_of_standby, r0) (Idi #_STCR, r12) stb r0, @r12 // set STOP/SLEEP bit Idub @r12, r0 // Must read STCR Idub @r12, r0 // after reading, go into standby mode nop // Must insert NOP *5 nop nop nop nop

25

MB91350A Series

26

• I/O Port Access

Ports are accessed only in bytes.

• Built-in RAM

Immediately after a reset is canceled, the internal RAM allocation restricting function is still working, allowingonly 4 KB to be used for data and for program execution irrespective of the on-chip RAM capacity.To kill the restricting function, update the setting.When the above setting is updated, the instruction must be followed by at least one NOP instruction.

• Flash MEMORY

In programming mode, flash memory cannot be used as an interrupt vector table. A reset is possible.

• Notes on the PS Register

As the PS register is processed by some instructions in advance, exception handling below may cause theinterrupt handling routine to break when the debugger is used or the display contents of flags in the PS registerto be updated.

As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, itperforms operations before and after the EIT as specified in either case.

1. The following operations are performed when the instruction followed by a DIVOU/DIVOS instruction results in: (a) acceptance of a user interrupt or NMI, (b) single-stepping, or (c) a break at a data event or emulator menu.• The D0 and D1 flags are updated in advance.• An EIT handling routine (user interrupt, NMI, or emulator) is executed.• Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are

updated to the same values as in (1).2. The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed.

• The PS register is updated in advance.• An EIT handling routine (user interrupt, NMI, or emulator) is executed.• Upon returning from the EIT, the above instructions are executed and the PS register is updated to the

same value as in (1).

MB91350A Series

[Note on Debugger]• Step Execution of RETI Command

If an interrupt occurs frequently during single-stepping, the corresponding interrupt handling routine is executedrepeatedly. This will prevent the main routine and low-interrupt-level programs from being executed.(Whenever RETI is single-stepped when interrupts by the timebase timer have been enabled, for example, thetimebase timer routine causes a break at the beginning.)Disable the corresponding interrupt when the corresponding interrupt handling routine no longer needs debug-ging.

• Break Function

If the address at which to cause a hardware break (including a event break) is set to the address currentlycontained in the system stack pointer or in the area containing the stack pointer, the user program causes abreak after execution of one instruction.To prevent this, do not set (word) access to the area containing the address in the system stack pointer as thetarget of a hardware break (including an event break).

• Internal ROM area

Do not set an area of internal ROM as a DMAC transfer destination.

• Simultaneous Occurrences of a Software Break (INTE instruction) and a User Interrupt/NMI

When a software break and a user interrupt/NMI occur simultaneously, the emulator debugger may react asfollows.• The debugger stops pointing to a location other than the programmed breakpoints.• The halted program is not re-executed correctly.

If this symptom occurs, use a hardware break in place of a hardware break. When using a monitor debugger, do not set a break at the relevant location.

• A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a dataevent break to access to the area containing the address of a system stack pointer.

27

MB91350A Series

28

■ BLOCK DIAGRAMS

DMAC 5 channels

PORT

FR CPU

BusConverter

32 32

3232

32↔16Adapter

ROM 512 KB*

RAM 8 KB

16

4 channelsUART

4 channelsU-timer

2 channelsSIO

X0, X1

MD0 to MD2

INIT

X0A, X1A

INT0 to INT7

NMI

SI0 to SI3

SO0 to SO3

SCK0 to SCK3

SI6, SI7SO6, SO7

SCK6, SCK7

DA0, DA1DAVC, DAVS

8 channelsA/D converter

AN0 to AN7ATG

AVRH, AVCCAVSS/AVRL

A20 to A00D31 to D16

RDWR1, WR0

RDYBRQBGRNTSYSCLK

PORT

TRG0 to TRG4PPG0, PPG2, PPG4

FRCK

IN0 to IN3

OC0, OC2

AIN0BIN0ZIN0

1 channelI2C

SDASCL

2 channelsD/A converter

Bit search

RAM 16 KB (stack)*

Clockcontrol

Interrupt Controller

8 channelsExternal interrupt

2 channelsOutput compare

4 channelsInput capture

Free-run timer

4 channelsReload timer

3 channelsPPG

External memoryI/F

Clock timer

1 channel8-bit up/down counter

* : MB91352A : RAM 8 KB (stack) , ROM 384 KBMB91351A : RAM 16 KB (stack) , ROM 384 KB

• MB91F353A/353A/352A/351A

MB91350A Series

DMAC 5 channels

PORT

1 channelI2C

FR CPU

BusConverter

32 32

3232

32 ↔ 16Adapter

ROM/Flash

RAM(Execute instruction)

16

5 channelsUART

5 channelsU-Timer

X0, X1

MD0 to MD2

INIT

INT0 to INT15

NMI

SI0 to SI4

SO0 to SO4

SCK0 to SCK4

SI5 to SI7SO5 to SO7

SCK5 to SCK7

DA0 to DA2DAVC, DAVS

12 channelsA/D converter

AN0 to AN11ATG

AVRH, AVCCAVSS/AVRL

DREQ0 to DREQ2

DACK0 to DACK2

DEOP0/DSTP0 to DEOP2/DSTP2

IOWR

IORD

A23 to A00D31 to D16

RDWR1, WR0

RDYBRQBGRNTSYSCLK

PORT

TRG0 to TRG5PPG0 to PPG5

FRCK

IN0 to IN3

OC0 to OC7

AIN0, AIN1BIN0, BIN1ZIN0, ZIN1

SDASCL

TOT0 to TOT3

3 channelsSIO

X0A, X1A

3 channelsD/A converter

Bit search

RAM (stack)

Clock control

InterruptController

16 channelsExternal interrupt

8 channelsoutput compare

4 channelsinput capture

Free-run timer

2 channels8/16-bit up/down

counter

4 channelsreload timer

6 channelsPPG

External memoryI/F

Clock timer

• MB91F355A/F356B/355A/354A

MB91F355A MB91F356B MB91355A MB91354AROM/Flash 512 KB (Flash) 256 KB (Flash) 512 KB 384 KBRAM (stack) 16 KB 16 KB 16 KB 8 KBRAM (Execute instruction) 8 KB 8 KB 8 KB 8 KB

29

MB91350A Series

30

■ CPU AND CONTROL UNITInternal architecture

The FR family CPU is a high performance core based on a RISC architecture while incorporating advancedinstructions for embedded controller applications.

1. Features• RISC architecture employed. Basic instructions: Executed at 1 instruction per cycle• General-purpose registers: 32-bit × 16 registers• 4GB linear memory space• Multiplier integrated.

32-bit × 32-bit multiplication: 5 cycles. 16-bit × 16-bit multiplication: 3 cycles

• Enhanced interrupt servicing. Fast response speed (6 cycles). Multiple interrupts supported. Level masking (16 levels)

• Enhanced I/O manipulation instructions. Memory-to-memory transfer instructionsBit manipulation instructions

• High code efficiency. Basic instruction word length: 16-bit• Low-power consumption.

Sleep mode and stop mode• Gear function

MB91350A Series

2. Internal architectureThe FR-family CPU has a Harvard architecture in which the instruction and data buses are separated. The 32-bit↔16-bit bus converter is connected to a 32-bit bus (F-bus), providing an interface between the CPU and peripheral resources. The Harvard↔Princeton bus converter is connected to both of the I-bus and D-bus, providing an interface between the CPU and the bus controller.

FR CPU

DataRAM

32-bit

16-bitbus converter

Harvard

Princetonbus

converter

D-bus I-bus

D address

I address External address

External data

D data

Address

Data

16

16

24

32

32

32

32

32

32

I data

R-busF-bus

Peripherals resource Internal I/O bus controller

31

MB91350A Series

32

3. Programming model• Basic programming model

R0

R1

R12

R13

R14

R15

PC

PS ⎯ ILM ⎯ SCR CCR

TBR

RP

SSP

USP

MDH

MDL

AC

FP

SP

XXXX XXXXH

XXXX XXXXH

0000 0000H

32-bit[Initial Value]

GENERAL PURPOSE

REGISTERS

Program counter

program status

Table base register

Return pointer

System stack pointer

User stack pointer

Multiplication and division result register

MB91350A Series

4. Register• General purpose registers

Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memoryaccess pointers for CPU operations.

Of these 16 registers, the registers listed below are intended for special applications, for which some instructionsare enhanced.

R13: Virtual accumulatorR14: Frame pointerR15: Stack pointer

The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 00000000H (SSP value).

• PS (Program Status)

This register holds the program status and is divided into the ILM, SCR, and CCR.

The undefined bits in the following illustration are all reserved bits. Reading these bits always returns “0”. Writingto them has no effect.

R0

R1

R12

R13

R14

R15

AC

FP

SP

XXXX XXXXH

XXXX XXXXH

0000 0000H

32-bit[Initial Value]

PSbit 31 bit 20 bit 16

ILM SCR CCR

bit 10 bit 7bit 8 bit 0

⎯⎯

33

MB91350A Series

34

• CCR (Condition Code Register)

• SCR (System Condition code Register)

Flag for step dividing

Stores intermediate data for stepwise multiplication operations.

Step trace trap flag

A flag specifying whether the step trace trap function is enabled or not.Emulator use step trace trap function. The function cannot be used by the user program when using theemulator.

• ILM

This register stores the interrupt level mask value. The value in the ILM register is used as the level mask.Initialized to “15” (01111B) by a reset.

• PC (Program Counter)

The program counter contains the address of the instruction currently being executed.The initial value after a reset is indeterminate.

• TBR (Table Base Register)

The table base register contains the start address of the vector table used for servicing EIT events.The initial value after a reset is 000FFC00H.

S : Stack flag. Cleared to “0” by a reset.I : Interrupt enable flag. Cleared to “0” by a reset.N : Negative flag. The initial value after a reset is indeterminate.Z : Zero flag. The initial value after a reset is indeterminate.V : Overflow flag. The initial value after a reset is indeterminate.C : Carry flag. The initial value after a reset is indeterminate.

Initial ValueCCR - - 00XXXXB

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

⎯ ⎯ S I N Z V C

Initial Value

SCR XX0B

bit 10 bit 9 bit 8

D1 D0 T

Initial Value

ILM 01111B

bit 20 bit 19 bit 18 bit 17 bit 16

ILM4 ILM3 ILM2 ILM1 ILM0

Initial Value

XXXXXXXXH

bit 31 bit 0

PC

Initial Value

000FFC00H

bit 31 bit 0

TBR

MB91350A Series

• RP (Return Pointer)

The return pointer contains the address to which to return from a subroutine.When the CALL instruction is executed, the value in the PC is transferred to the RP.When the RET instruction is executed, the value in the RP is transferred to the PC.The initial value after a reset is indeterminate.

• SSP (System Stack Pointer)

The SSP is the system stack pointer and functions as R15 when the S flag is “0”.The SSP can be explicitly specified.The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT eventoccurs.The initial value after a reset is 00000000H.

• USP (User Stack Pointer)

The USP is the user stack pointer and functions as R15 when the S flag is “1”.The USP can be explicitly specified.The initial value after a reset is indeterminate.This pointer cannot be used by the RETI instruction.

• Multiply & Divide register

These registers hold the results of a multiplication or division. Each of them is 32-bit long.The initial value after a reset is indeterminate.

Initial Value

XXXXXXXXH

bit 31 bit 0

RP

Initial Value

00000000H

bit 31 bit 0

SSP

Initial Value

XXXXXXXXH

bit 31 bit 0

USP

bit 31 bit 0

MDH

MDL

35

MB91350A Series

36

■ MODE SETTINGSThe FR family uses mode pins (MD2 to MD0) and a mode register (MODR) to set the operation mode.

1. Mode Pins

The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.

Values other than those listed in the table are prohibited.

2. Mode Register (MODR)

The data written to the mode register at 000F FFF8H using mode vector fetch is called mode data.After an operation mode has been set in the mode register (MODR), the device operates in the operation mode.The mode register is set by any reset source. User programs cannot write data to the mode register.

Note : Conventionally the FR family has nothing at addresses (0000 07FFH) in the mode register.

[Register description]

[bit7-bit3] Reserved bit

Be sure to set this bit to “00000B”. Operation is not guaranteed when any value other than “00000B” is set.

[bit2] ROMA (internal ROM enable bit)

The ROMA bit is used to set whether to enable the internal F-bus RAM and F-bus ROM areas.

[bit1, bit0] WTH1, WTH0 (Bus width setting bits)

Used to set the bus width to be used in external bus mode.When the operation mode is the external bus mode, this value is set in bits BW1 and BW0 in AMD0 (CS0 area).

Mode PinsMode name Reset vector access area RemarksMD2 MD1 MD0

0 0 0 internal ROM mode vector Internal

0 0 1 external ROM mode vector ExternalThe bus width is specified by the mode register.

ROMA Function Remarks

0External ROM mode

Internal F-bus RAM is valid; the area (8 0000H to 10 0000H) of internal ROM is used as an external area.

1Internal ROM mode

Internal F-bus RAM and F-bus ROM become valid.

WTH1 WTH0 function Remarks

0 0 8-bit bus widthexternal bus mode

0 1 16-bit bus width

1 0 ⎯ Setting disabled1 1 single chip mode single chip mode

MODR Initial Value

000F FFF8H XXXXXXXXBbit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

0 0 0 0 0 ROMA WTH1 WTH0

Operation mode setting

MB91350A Series

■ MEMORY SPACE1. Memory space

The FR family has 4 G bytes of logical address space (232 addresses) available to the CPU by linear access.

• Direct Addressing Areas

The following address space areas are used as I/O areas.These areas are called direct addressing areas, in which the address of an operand can be specified directlyduring an instruction.The size of directly addressable areas depends on the length of the data being accessed as shown below.

→ Byte data access : 000H to 0FFH→ Half word data access : 000H to 1FFH→ Word data access : 000H to 3FFH

2. Memory Map

Memory Map of MB91F355A/F353A/355A/353A

• Each mode is set depending on the mode vector fetch after INIT is negated.• The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the

available area is updated, the instruction must be followed by at least 1 NOP instruction.

0008 0000H

0000 0000H

0000 0400H

0001 0000H

0003 E000H

0004 0000H

0004 4000H

0005 0000H

0010 0000H

FFFF FFFFH

I/O

I/O

I/O

I/O

I/O

I/O

Single chip mode

Internal ROM external bus mode

Access disallowed

Directaddressing area

Refer to “■ I/O MAP”.

Built-in RAM 8 KB(Execute instruction)

Built-in ROM512 KB

Access disallowed

Access disallowed


Built-in ROM512 KB

External area

Access disallowed


External area

Built-in RAM 16 KB (Stack)

Access disallowed

External ROM external bus mode

External area

Access disallowed

Access disallowed


Built-in RAM16 KB (Stack)

37

MB91350A Series

38

Memory Map of MB91354A



0000 0000H

0000 0400H

0001 0000H

0003 E000H

0004 0000H

0004 2000H

0010 0000H

FFFF FFFFH

I/O

I/O

I/O

I/O

I/O

I/O

000A 0000H

0005 0000H

0008 0000H




Single chip mode Internal ROM external bus mode

Access disallowed



Built-in ROM384 KB

Access disallowed

Access disallowed

Built-in ROM384 KB

External area

Access disallowed

External area


Access disallowed


External areaAccess

disallowed

Access disallowed



Access disallowed

MB91350A Series




000A 0000H

0000 0000H

0000 0400H

0001 0000H

0003 E000H

0004 0000H

0004 2000H

0005 0000H

0010 0000H

FFFF FFFFH

I/O

I/O

I/O

I/O

I/O

I/O

Single chip mode


Access disallowed




Built-in ROM384 KB

Access disallowed

Access disallowed


Built-in ROM384 KB

External area

Access disallowed


External area


Access disallowed


External area

Access disallowed

Access disallowed



39

MB91350A Series

40




000A 0000H

0000 0000H

0000 0400H

0001 0000H

0003 E000H

0004 0000H

0004 4000H

0005 0000H

0010 0000H

FFFF FFFFH

I/O

I/O

I/O

I/O

I/O

I/O

Single chip mode


Access disallowed




Built-in ROM384 KB

Access disallowed

Access disallowed


Built-in ROM384 KB

External area

Access disallowed


External area


Access disallowed


External area

Access disallowed

Access disallowed



MB91350A Series

Memory Map of MB91F356B



000C 0000H

0000 0000H

0000 0400H

0001 0000H

0003 E000H

0004 0000H

0004 4000H

0005 0000H

0010 0000H

FFFF FFFFH

I/O

I/O

I/O

I/O

I/O

I/O

0008 0000H




Single chip mode Internal ROM external bus mode

Access disallowed



Built-in ROM256 KB

Access disallowed

Access disallowed

Built-in ROM256 KB

External area

Access disallowed

External area


Access disallowed


External area

Access disallowed

Access disallowed



Access disallowed

41

MB91350A Series

42

■ I/O MAPThis shows the location of the various peripheral resource registers in the memory space.

[How to read the table]

Note: Initial values of register bits are represented as follows: “1” : Initial value is “1”.“0” : Initial Value is “0”.“X” : Initial value is “X”.“−” : No physical register at this location

AddressRegister

Block diagram + 0 + 1 + 2 + 3

000000HPDR0 [R/W] BXXXXXXXX

PDR1 [R/W] BXXXXXXXX



T-unitPort Data Register

Initial value after a reset

Register name (First-column register at address 4n; second-column register at address 4n + 2)

Read/write attribute, Access unit(B: Byte, H: Half Word, W: Word)

Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.)

MB91350A Series

(Continued)

AddressRegister

Block+0 +1 +2 +3

000000H ⎯⎯⎯⎯ ⎯⎯⎯⎯ PDR2[R/W]BXXXXXXXX

PDR3[R/W]BXXXXXXXX

T-unit port data

register*3

000004HPDR4[R/W]BXXXXXXXX

PDR5[R/W]BXXXXXXXX

PDR6[R/W]BXXXXXXXX

⎯⎯⎯⎯

000008HPDR8[R/W]B

--XXXXXXPDR9[R/W]B

---XXXXXPDRA[R/W]B

----XXXXPDRB[R/W]B*3

XXXXXXXX

00000CHPDRC[R/W]B*3

-----XXX⎯⎯⎯⎯

000010HPDRG[R/W]B*3

--XXXXXXPDRH[R/W]B

--XXXXXXPDRI[R/W]B--XXXXXX

PDRJ[R/W]B*3

XXXXXXXX

R-bus port data

register*3

000014HPDRK[R/W]BXXXXXXXX

PDRL[R/W]B------XX

PDRM[R/W]B--XXXXXX

PDRN[R/W]B--XXXXXX

000018HPDRO[R/W]BXXXXXXXX

PDRP[R/W]B*3

----XXXX⎯⎯⎯⎯ ⎯⎯⎯⎯

00001CH ⎯⎯⎯⎯

000020H ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ Reserved

000024HSMCS5[R/W]B,H*3

00000010_----00--SES5[R/W]B*3

------00SDR5[R/W]B*3

XXXXXXXXSIO5*3

000028HSMCS6[R/W]B,H00000010_----00--

SES6[R/W]B------00

SDR6[R/W]BXXXXXXXX

SIO6

00002CHSMCS7[R/W]B,H00000010_----00--

SES7[R/W]B------00

SDR7[R/W]BXXXXXXXX

SIO7

000030H ⎯⎯⎯⎯ ⎯⎯⎯⎯ CDCR5[R/W]B*3

0---1111⎯⎯⎯⎯ *1 SIO

prescaler 5*3

000034HCDCR6[R/W]B

0---1111⎯⎯⎯⎯ *1 CDCR7[R/W]B

0---1111⎯⎯⎯⎯ *1 SIO

prescaler 6, 7

000038H ⎯⎯⎯⎯ SRCL5[W]B*3

--------SRCL6[W]B

--------SRCL7[W]B

--------SIO5 to SIO7*3

00003CH ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ Reserved

000040HEIRR0[R/W]B,H,W

00000000ENIR0[R/W]B,H,W

00000000ELVR0[R/W]B,H,W

00000000

External interrupt

(INT0 to INT7)

000044HDICR[R/W]B,H,W

-------0HRCL[R/W]B,H,W

0--11111⎯⎯⎯⎯ Delay

interrupt

000048HTMRLR[W]H,W

XXXXXXXX_XXXXXXXXTMR[R]H,W

XXXXXXXX_XXXXXXXX Reload timer 0

00004CH ⎯⎯⎯⎯ TMCSR[R/W]B,H,W----0000_00000000

43

MB91350A Series

44

(Continued)

AddressRegister

Block+0 +1 +2 +3

000050HTMRLR[W]H,W



000054H ⎯⎯⎯⎯ TMCSR[R/W]B,H,W----0000_00000000

000058HTMRLR[W]H,W



00005CH ⎯⎯⎯⎯ TMCSR[R/W]B,H,W----0000_00000000

000060HSSR[R/W]B,H,W

00001000SIDR[R/W]B,H,W

XXXXXXXXSCR[R/W]B,H,W

00000100SMR[R/W]B,H,W

00--0---UART0

000064HUTIM[R]H(UTIMR[W]H)00000000_00000000

DRCL[W]B--------

UTIMC[R/W]B0--00001

U-TIMER/UART0


00001000

SIDR/SODR[R/W]B,H,WXXXXXXXX

SCR[R/W]B,H,W00000100

SMR[R/W]B,H,W00--0---

UART1

00006CHUTIM[R]H(UTIMR[W]H)00000000_00000000

DRCL[W]B--------

UTIMC[R/W]B0--00001

U-TIMER/UART1




00000100SMR[R/W]B,H,W

00--0---UART2

000074HUTIM[R]H(UTIMR[W]H)00000000_00000000

DRCL[W]B--------

UTIMC[R/W]B0--00001

U-TIMER/UART2

000078HADCS2[R/W]B,H,W

X000XX00ADCS1[R/W]B,H,W

000X0000ADCT[R/W]H,W

XXXXXXXX_XXXXXXXX

A/D converter

00007CHADTH0[R]B,H,W

XXXXXXXXADTL0[R]B,H,W

000000XXADTH1[R]B,H,W


000000XX

000080HADTH2[R]B,H,W


000000XXADTH3[R]B,H,W


000000XX

000084H ⎯⎯⎯⎯DACR2

[R/W]B,H,W*3

-------0

DACR1[R/W]B,H,W-------0

DACR0[R/W]B,H,W-------0

D/A converter*3

000088H ⎯⎯⎯⎯DADR2

[R/W]B,H,W*3

XXXXXXXX

DADR1[R/W]B,H,WXXXXXXXX

DADR0[R/W]B,H,WXXXXXXXX

00008CH ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ Reserved

000090H ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ *1 Reserved

000094HIBCR[R/W]B,H,W

00000000IBSR[R]B,H,W

00000000ITBA[R/W]B,H,W------00_00000000

I2C interface000098HITMK[R/W]B,H,W

00----11_11111111ISMK[R/W]B,H,W

01111111ISBA[R/W]B,H,W

-0000000

00009CH ⎯⎯⎯⎯ *2 IDAR[R/W]B,H,W00000000

ICCR[R/W]B,H,W0-011111

IDBL[R/W]B,H,W-------0

MB91350A Series

(Continued)

AddressRegister

Block+0 +1 +2 +3

0000A0H ⎯⎯⎯⎯ ⎯⎯⎯⎯*1 ⎯⎯⎯⎯ ⎯⎯⎯⎯ *1Reserved

0000A4H ⎯⎯⎯⎯ ⎯⎯⎯⎯ *1 ⎯⎯⎯⎯ *1 ⎯⎯⎯⎯ *1

0000A8HTMRLR[W]H,W



0000ACH ⎯⎯⎯⎯ TMCSR[R/W]B,H,W----0000_00000000

0000B0HRCR1[W]B,H,W*3

00000000RCR0[W]B,H,W

00000000UDCR1[R]B,H,W*3

00000000UDCR0[R]B,H,W

00000000 8/16-bit Up/Down counter 0, 1*3

0000B4HCCRH0[R/W]B,H,W

00000000CCRL0[R/W]B,H,W

00001000⎯⎯⎯⎯ CSR0[R/W]B,H,W

00000000

0000B8HCCRH1[R/W]B,H,W*3

00000000CCRL1[R/W]B,H,W*3

00001000⎯⎯⎯⎯ CSR1[R/W]B,H,W*

3

00000000

0000BCH ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ Reserved

0000C0HSSR[R/W]B,H,W



00000100SMR[R/W]B,H,W

00--0---UART3

0000C4HUTIM[R]H(UTIMR[W]H)00000000_00000000

⎯⎯⎯⎯ UTIMC[R/W]B0--00001

U-TIMER/UART3

0000C8HSSR[R/W]B,H,W*3

00001000SIDR[R/W]B,H,W*3

XXXXXXXXSCR[R/W]B,H,W*3

00000100SMR[R/W]B,H,W*3

00--0---UART4*3

0000CCHUTIM[R]H(UTIMR[W]H)*3

00000000_00000000⎯⎯⎯⎯ UTIMC[R/W]B*

3

0--00001U-TIMER/UART4*3

0000D0HEIRR1[R/W]B,H,W*3

00000000ENIR1[R/W]B,H,W*3

00000000ELVR1[R/W]B,H,W*3

00000000

External interrupt(INT8 to INT15)*3

0000D4HTCDT[R/W]H,W

00000000_00000000⎯⎯⎯⎯ TCCS[R/W]B,H,W

00000000

16-bit free-running

timer

0000D8HIPCP1[R]H,W

XXXXXXXX_XXXXXXXXIPCP0[R]H,W

XXXXXXXX_XXXXXXXX

16-bit input capture

0000DCHIPCP3[R]H,W

XXXXXXXX_XXXXXXXXIPCP2[R]H,W

XXXXXXXX_XXXXXXXX

0000E0H ⎯⎯⎯⎯ ICS23[R/W]B,H,W00000000

⎯⎯⎯⎯ ICS01[R/W]B,H,W00000000

45

MB91350A Series

46

(Continued)

AddressRegister

Block+0 +1 +2 +3

0000E4HOCCP1[R/W]H,W*3

XXXXXXXX_XXXXXXXXOCCP0[R/W]H,W

XXXXXXXX_XXXXXXXX

16-bit output

compare*3

0000E8HOCCP3[R/W]H,W*3

XXXXXXXX_XXXXXXXXOCCP2[R/W]H,W

XXXXXXXX_XXXXXXXX

0000ECHOCCP5[R/W]H,W*3

XXXXXXXX_XXXXXXXXOCCP4[R/W]H,W*3

XXXXXXXX_XXXXXXXX

0000F0HOCCP7[R/W]H,W*3

XXXXXXXX_XXXXXXXXOCCP6[R/W]H,W*3

XXXXXXXX_XXXXXXXX

0000F4HOCS23[R/W]B,H,W

11101100_00001100OCS01[R/W]B,H,W

11101100_00001100

0000F8HOCS67[R/W]B,H,W*3

11101100_00001100OCS45[R/W]B,H,W*3

11101100_00001100

0000FCH ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ Reserved

000100Hto

000114H⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ Reserved

000118HGCN10[R/W]H

00110010_00010000⎯⎯⎯⎯ GCN20[R/W]B

00000000PPG control 0

00011CH ⎯⎯⎯⎯ ⎯⎯⎯⎯ Reserved

000120HPTMR0[R]H,W

11111111_11111111PCSR0[W]H,W

XXXXXXXX_XXXXXXXXPPG0

000124HPDUT0[W]H,W

XXXXXXXX_XXXXXXXXPCNH0[R/W]B,H,W

00000000PCNL0[R/W]B,H,W

00000000

000128HPTMR1[R]H,W*3

11111111_11111111PCSR1[W]H,W*3

XXXXXXXX_XXXXXXXXPPG1*3

00012CHPDUT1[W]H,W*3

XXXXXXXX_XXXXXXXXPCNH1[R/W]B,H,W*3

00000000PCNL1[R/W]B,H,W*3

00000000

000130HPTMR2[R]H,W

11111111_11111111PCSR2[W]H,W


000134HPDUT2[W]H,W


00000000PCNL2[R/W]B,H,W

00000000


11111111_11111111PCSR3[W]H,W*3

XXXXXXXX_XXXXXXXXPPG3*3


XXXXXXXX_XXXXXXXXPCNH3[R/W]B,H,W*3

00000000PCNL3[R/W]B,H,W*3

00000000

000140HPTMR4[R]H,W

11111111_11111111PCSR4[W]H,W


000144HPDUT4[W]H,W


00000000PCNL4[R/W]B,H,W

00000000

MB91350A Series

(Continued)

AddressRegister

Block+0 +1 +2 +3


11111111_11111111PCSR5[W]H,W*3

XXXXXXXX_XXXXXXXX

PPG5*3


XXXXXXXX_XXXXXXXX

PCNH5[R/W]B,H,W*3

00000000

PCNL5[R/W]B,H,W*3

00000000

000150Hto

0001FCH⎯⎯⎯⎯ Reserved

000200HDMACA0[R/W]B,H,W *4

00000000_0000XXXX_XXXXXXXX_XXXXXXXX

DMAC

000204HDMACB0[R/W]B,H,W

00000000_00000000_XXXXXXXX_XXXXXXXX



00020CHDMACB1[R/W]B,H,W








00021CHDMACB3[R/W]B,H,W






000228H ⎯⎯⎯⎯

00022CHto

00023CH⎯⎯⎯⎯ Reserved

000240HDMACR[R/W]B

0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXXDMAC

000244Hto


000280HFRLR[R/W]B,H,W*2

------01⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯

Limit on F-bus RAM

capacity

47

MB91350A Series

48

(Continued)

AddressRegister

Block+0 +1 +2 +3

000284Hto


000390HDRLR[R/W]B,H,W*2

------01⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ Limit on D-bus

RAM capacity

000394Hto

0003ECH⎯⎯⎯⎯ Reserved

0003F0HBSD0[W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

Bit search module

0003F4HBSD1[R/W]


0003F8HBSDC[W]


0003FCHBSRR[R]


000400HDDRG[R/W]B*3

--000000DDRH[R/W]B

--000000DDRI[R/W]B

--000000DDRJ[R/W]B*3

00000000

R-bus data direction register*3

000404HDDRK[R/W]B

00000000DDRL[R/W]B

------00DDRM[R/W]B

--000000DDRN[R/W]B

--000000

000408HDDRO[R/W]B

00000000DDRP[R/W]B*3

---- 0000⎯⎯⎯⎯

00040CH ⎯⎯⎯⎯

000410HPFRG[R/W]B*3

--00-00-PFRH[R/W]B

--00-00-PFRI[R/W]B

--00-00-⎯⎯⎯⎯

R-bus port function register*3

000414H ⎯⎯⎯⎯ PFRL[R/W]B------00

PFRM[R/W]B--00-00-

PFRN[R/W]B--000000

000418HPFRO[R/W]B

00000000PFRP[R/W]B*3

----0000⎯⎯⎯⎯

00041CH ⎯⎯⎯⎯ Reserved

000420HPCRG[R/W]B*3

--000000PCRH[R/W]B

--000000PCRI[R/W]B

--000000⎯⎯⎯⎯

R-bus pull-up control

register*3000424H ⎯⎯⎯⎯ ⎯⎯⎯⎯ PCRM[R/W]B

--000000PCRN[R/W]B

--000000

000428HPCRO[R/W]B

00000000PCRP[R/W]B*3

----0000⎯⎯⎯⎯ ⎯⎯⎯⎯

00042CHto


MB91350A Series

(Continued)

AddressRegister

Block+0 +1 +2 +3

000440HICR00[R/W]B,H,W

---11111ICR01[R/W]B,H,W

---11111ICR02[R/W]B,H,W

---11111ICR03[R/W]B,H,W

---11111

Interrupt controller unit


---11111ICR05[R/W]B,H,W

---11111ICR06[R/W]B,H,W

---11111ICR07[R/W]B,H,W

---11111


---11111ICR09[R/W]B,H,W

---11111ICR10[R/W]B,H,W

---11111ICR11[R/W]B,H,W

---11111

00044CHICR12[R/W]B,H,W

---11111ICR13[R/W]B,H,W

---11111ICR14[R/W]B,H,W

---11111ICR15[R/W]B,H,W

---11111


---11111ICR17[R/W]B,H,W

---11111ICR18[R/W]B,H,W

---11111ICR19[R/W]B,H,W

---11111


---11111ICR21[R/W]B,H,W

---11111ICR22[R/W]B,H,W

---11111ICR23[R/W]B,H,W

---11111


---11111ICR25[R/W]B,H,W

---11111ICR26[R/W]B,H,W

---11111ICR27[R/W]B,H,W

---11111


---11111ICR29[R/W]B,H,W

---11111ICR30[R/W]B,H,W

---11111ICR31[R/W]B,H,W

---11111


---11111ICR33[R/W]B,H,W

---11111ICR34[R/W]B,H,W

---11111ICR35[R/W]B,H,W

---11111


---11111ICR37[R/W]B,H,W

---11111ICR38[R/W]B,H,W

---11111ICR39[R/W]B,H,W

---11111


---11111ICR41[R/W]B,H,W

---11111ICR42[R/W]B,H,W

---11111ICR43[R/W]B,H,W

---11111


---11111ICR45[R/W]B,H,W

---11111ICR46[R/W]B,H,W

---11111ICR47[R/W]B,H,W

---11111Interrupt

controller unit000470Hto

00047CH⎯⎯⎯⎯

000480HRSRR[R/W]B,H,W

10000000STCR[R/W]B,H,W

00110011TBCR[R/W]B,H,W

00XXXX00CTBR[W]B,H,W

XXXXXXXX

Clock control unit

000484HCLKR[R/W]B,H,W

00000000WPR[W]B,H,W

XXXXXXXXDIVR0[R/W]B,H,W

00000011DIVR1[R/W]B,H,W

00000000

000488H ⎯⎯⎯⎯ OSCCR[R/W]BXXXXXXX0

⎯⎯⎯⎯

00048CHWPCR[R/W]B

00---000⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ Watch timer

000490HOSCR[R/W]B

00---000⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯

Main clock oscillation

stabilization wait timer

000494HRSTOP0[W]B

00000000RSTOP1[W]B

00000000RSTOP2[W]B

00000000RSTOP3[W]B

-----000Peripheral

stop control

49

MB91350A Series

50

(Continued)

AddressRegister

Block+0 +1 +2 +3

000498H ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ Reserved

00049CHto

0005FCH⎯⎯⎯⎯ Reserved

000600H ⎯⎯⎯⎯ ⎯⎯⎯⎯ DDR2[R/W]B00000000

DDR3[R/W]B00000000

T-unit data direction register*3

000604HDDR4[R/W]B

00000000DDR5[R/W]B

00000000DDR6[R/W]B

00000000⎯⎯⎯⎯

000608HDDR8[R/W]B

--000000DDR9[R/W]B

---00000DDRA[R/W]B

----0000DDRB[R/W]B*3

00000000

00060CHDDRC[R/W]B*3

-----000⎯⎯⎯⎯

000610H ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯

T-unit port function register*3

000614H ⎯⎯⎯⎯ ⎯⎯⎯⎯ PFR6[R/W]B11111111

⎯⎯⎯⎯

000618HPFR8[R/W]B

--1--0--PFR9[R/W]B

---010-1PFRA[R/W]B

----1111PFRB1[R/W]B*3

00000000

00061CHPFRB2[R/W]B*3

00----00PFRC[R/W]B*3

---00000⎯⎯⎯⎯ ⎯⎯⎯⎯

000620H ⎯⎯⎯⎯ ⎯⎯⎯⎯ PCR2[R/W]B00000000

PCR3[R/W]B00000000

T-unit pull-up control

register*3

000624HPCR4[R/W]B

00000000PCR5[R/W]B

00000000PCR6[R/W]B

00000000⎯⎯⎯⎯

000628HPCR8[R/W]B

--000000PCR9[R/W]B

00000000PCRA[R/W]B

00000000PCRB[R/W]B*3

00000000

00062CHPCRC[R/W]B*3

-----000⎯⎯⎯⎯ ⎯⎯⎯⎯ ⎯⎯⎯⎯

000630Hto

00063CH________ Reserved

MB91350A Series

(Continued)

AddressRegister

Block+0 +1 +2 +3

000640HASR0[R/W]H,W

00000000_00000000ACR0[R/W]B,H,W

1111XX00_00000000

T-unit

000644HASR1[R/W]H,W

00000000_00000000ACR1[R/W]B,H,W

XXXXXXXX_XXXXXXXX

000648HASR2[R/W]H,W

00000000_00000000ACR2[R/W]B,H,W

XXXXXXXX_XXXXXXXX

00064CHASR3[R/W]H,W

00000000_00000000ACR3[R/W]B,H,W

XXXXXXXX_XXXXXXXX

000650HASR4[R/W]H,W

00000000_00000000ACR4[R/W]B,H,W

XXXXXXXX_XXXXXXXX

000654HASR5[R/W]H,W

00000000_00000000ACR5[R/W]B,H,W

XXXXXXXX_XXXXXXXX

000658HASR6[R/W]H,W

00000000_00000000ACR6[R/W]B,H,W

XXXXXXXX_XXXXXXXX

00065CHASR7[R/W]H,W

00000000_00000000ACR7[R/W]B,H,W

XXXXXXXX_XXXXXXXX

000660HAWR0[R/W]B,H,W

01111111_11111111AWR1[R/W]B,H,W

XXXXXXXX_XXXXXXXX


XXXXXXXX_XXXXXXXXAWR3[R/W]B,H,W

XXXXXXXX_XXXXXXXX



XXXXXXXX_XXXXXXXX

00066CHAWR6[R/W]B,H,W


XXXXXXXX_XXXXXXXX

000670H ⎯⎯⎯⎯

000674H ⎯⎯⎯⎯

000678HIOWR0[R/W]B,H,W

XXXXXXXXIOWR1[R/W]B,H,W

XXXXXXXXIOWR2[R/W]B,H,W

XXXXXXXX⎯⎯⎯⎯

00067CH ⎯⎯⎯⎯T-unit

000680HCSER[R/W]B,H,W

00000001⎯⎯⎯⎯ ⎯⎯⎯⎯ TCR[W]B,H,W

0000XXXX

000684Hto

0007F8H⎯⎯⎯⎯ Reserved

0007FCH ⎯⎯⎯⎯ MODR[W] *5

XXXXXXXX⎯⎯⎯⎯ ⎯⎯⎯⎯

000800Hto

000AFCH⎯⎯⎯⎯ Reserved

51

MB91350A Series

52

(Continued)

AddressRegister

Block+0 +1 +2 +3

000B00HESTS0[R/W]X0000000

ESTS1[R/W]XXXXXXXX

ESTS2[R]1XXXXXXX

⎯⎯⎯⎯

DSU (EVA chip

only)

000B04HECTL0[R/W]0X000000

ECTL1[R/W]00000000

ECTL2[W]000X0000

ECTL3[R/W]00X00X11

000B08HECNT0[W]

XXXXXXXXECNT1[W]

XXXXXXXXEUSA[W]

XXX00000EDTC[W]

0000XXXX

000B0CHEWPT[R]

00000000_00000000⎯⎯⎯⎯

000B10HEDTR0[W]

XXXXXXXX_XXXXXXXXEDTR1[W]

XXXXXXXX_XXXXXXXX

000B14Hto

000B1CH⎯⎯⎯⎯

000B20HEIA0[W]


000B24HEIA1[W]


000B28HEIA2[W]


000B2CHEIA3[W]


000B30HEIA4[W]

mb91f355a/f353a/f356b/355a/354a/ mb91353a/352a ......*: purchase of fujitsu i 2c components conveys...

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