566 Chapter 22

MREQTerminal G19

An external device activates the master request signal MREQ to take over control of the EISAbus as a busmaster. The system arbitrator detects MREQ and passes control if no other masteris active. Normally, the CPU on the motherboard is the active busmaster.

MSBURSTTerminal E9

An EISA master activates the master burst signal MSBURST to inform the EISA bus controllerthat the master can carry out the next bus cycle as a burst cycle. The bus transfer rate is thusdoubled. This is particularly advantageous for cache line fills and DMA transfers.

SLBURSTTerminal E8

An EISA slave activates the slave burst signal SLBURST to inform the bus controller that it canfollow a burst cycle. Typical EISA slaves that activate SLBURST are fast 32-bit main memories.

STAETTerminal E2

This signal serves for clock signal coordination at the beginning of an EISA bus cycle. STARTindicates the beginning of a cycle on the local bus.

W/RTerminal E10

The signal serves to distinguish write and read EISA bus cycles.

D32-D63 (I/O; corresponding to BED, BE1, LA2-LA31)Terminals C2-C8, E17-E18, E2Q-E23, E26^E29, E31, F18, F21, F23-F24, F26-F27, F31, Gl, G3-G4,H1-H3, H5

In an enhanced master burst the 30 address terminals LA2-LA31 and the two byte enableterminals BEO and BE1 transfer the 32 high-order data bits of a 64-bit data quantity.

All other contacts are reserved (res), are grounded (GND), or transfer supply voltages for chips(+5 V, -5 V) and Interfaces or drives (+12 V, -12 V).

Together with its new generation of PCs, the PS/2, IBM also implemented a new bus systemand a new PC architecture, the MicroChannel In view of its geometry as well as Its logicalconcept, this bus is a radical departure from the AT bus, which had been very successful upuntil that time. Hardware compatibility to previous PC models is no longer kept, but there aresome good reasons for this: the AT bus was only designed for 16-bit processors, but the new1386 and I486 CPUs run with 32 bits. Furthermore, because of its edge triggered interrupts, theAT bus is directed to singletasking operating systems such as DOS. The aim when designing thePS/2, on the other hand, was to go over to multitasking systems, particularly OS/2. Therefore,the problems are similar to those already mentioned in connection with EISA. It Is also inter-esting that the microchannel was presented much earlier than EISA. EISA was supposedlydesigned as a reaction to the microchannel, so as not to leave the 32-bit market all to IBM.Identical problems often lead to similar solutions, thus it is perhaps not surprising that themicrochannel (apart from the completely Incompatible bus slot) does not differ radically fromEISA. After all, at the operating system level, and especially at the application level, completecompatibility with the AT must be achieved. Programs that do not explicitly refer to the hard-ware registers also run on the PS/2 without any problems, and with no noticeable difference forthe users.

Figure 231 shows a schematic block diagram of the microchannel architecture (MCA). A signifi-cant difference from EISA is the separate system clock which supplies a frequency of 10 MHzat most for all microchannel components. Only the local bus between the CPU and the memoryoperates faster to carry out data accesses, of the CPU to main memory at a maximum speed.Thus the microchannel is an asynchronous bus system; the CPU is clocked by Its own CPU clock.The microchannel was Initially introduced with three different bus cycles:

- standard bus cycle,- synchronous extended bus cycle, and- asynchronous extended bus cycle.

The standard bus cycle corresponds to a conventional CPU bus cycle at 10 MHz with no waitcycles. In an extended bus cycle the device addressed inserts wait states by means of the CHRDYsignal If CHRDY becomes active synchronous to the data half-cycle of the MCA bus cycle, thisis called a synchronous extended bus cycle, otherwise It is an asynchronous extended bus cycle.CHRDY refers to the bus clock of 10 MHz but not to the CPU clock, which may be much higher,especially with 1386 or i486 processors. Because of their high clock rates, 1386 and i486 alwaysinsert several CPU wait cycles which are controlled by the bus controller using the READYprocessor signal. One MCA bus cycle without wait cycles lasts for two bus clock cycles with100 ns each. Thus the microchannel Is presently conceived for a maximum data transfer rate of20 Mbytes/s. The data transfer rate can be slightly increased by the so-called matched-memory cycles.These are only implemented with the 16 MHz model 80, and are controlled by the MMC andMMCR signals. To carry out a matched-memory cycle the bus controller of the motherboard

567

SystemClock

CPUClock

CPU

DRAyControl

10 MHz max.

DRAM

DMAController

InterruptController

Bus ArbiterCACP

Timer

NMI Logic

I/O SupportChip l

MCABus Buffer

MCA BusController

ParallelInterface

VGA

AuxiliaryInterface

SerialInterface

IfMCA Adapter

LocalCPU

LocalLogic

MicroChannel

Figure 23.1: The MCA architecture.

activates the MMC (matched-memory cycle) signal If the addressed device responds with anactive JvfMCR (matched-memory cycle return), the bus controller shortens the cycle time of theMCA bus clock to 93.75 ns. ADL and CMD are not generated here, but MMCCMD is. Becauseof the shorter cycle time, a data transfer rate of at most 21.4 Mbytes/s is possible; this is anincredible increase of 7%.

No wonder, then, that IBM mothballed the matched-memory cycle, and developed the streamingdata procedure (SDP) concept. Presently, three such SDPs have been designed:

- 32-bit SDP,- 64~bit SDP, and- extended 64-bit SDP.

IBM uses the microchannel not only in its PS/2 series but also in much more powerful RISCSystem/6000 workstations with a basis of RISC processors with the POWER architecture (Per-formance Optimization With Enhanced RISC).

In view of the signal course, the 32-bit SDP coincides with the I486 burst mode. To request a32-bit SDP the busmaster deactivates the BLAST signal. The device addressed responds with aBRDY to indicate that it is able to carry out 32-bit burst mode. With the 32-bit SDP four bytes

32-bit MicroChannel - Revolution 569

are transferred within a single MCA bus clock cycle. Using this the data transfer rate Increasesto 40 Mbytes/s for a short time. This Is even more than the 33 Mbytes/s for the EISA burstmode.

A further enhancement is possible with the. 64-bit SDP. Here, only during the first bus cycle Isthe address output. The addressed device accepts and stores It. Afterwards, the data Is trans-ferred not only via the 32-bit data bus, but also via the 32-bit address bus, that is, with a widthof 64 bits or 8 bytes in total. The device addressed comprises an address counter that counts upwith each 64-bit iSDP automatically. It therefore only needs the start address. With the 64-bitSDP a data transfer rate of 80 Mbytes/s can be achieved. The extended 64-bit SDP is even morepowerful. Here the bus cycle is reduced from 100 ns down to 50 ns, but the transfer itself isidentical to that of a normal 64-bit SDP. The data transfer rate doubles to 160 Mbytes/s, that is,a medium-sized hard disk could be read within one second.

232 Bus Arbitration

Like EISA, the MCA also supports external busmasters on adapter cards. Including the CPU, upto 16 different busmasters can be Integrated. For this purpose, IBM implemented a dedicatedchip, the so-called central arbitration control point (CACP), which carries out the bus arbitrationand passes control to a busmaster. With the MCA the motherboard's CPU, the refresh logic, theDMA controller and external busmasters on adapter cards can operate as busmasters. Table 23.1shows the priorities assigned to these busmasters.

Priority Device

-2d memory refresh

-1d NMIOOh DMA channel 0* }

•01 h DMA channel02h DMA channel03h DMA channel04h DMA channel 0*>05h DMA channel06h DMA channel07h DMA channel08h available for external busmaster09h available for external busmasterOah available for external busmasterObh available for external busmasterOch available for external busmasterOdh available for external busmasterOeh available for external busmasterOfh CPU on the motherboard

*' Priority can be programmed freely.

Table 23.1: Arbitration priorities in the PS/2

570Chapter 23 32-bit MicroChannel - Revolution 571

The -2 priority of the memory refresh means that the arbitration logic always passes control ofthe bus if a refresh Is requested. The memory refresh is located on the motherboard and drivesthe arbitration logic by an internal refresh request signal. The next lower priority, - 1 , of the NMlIs also processed internally. The source of an NMI is usually an error on an adapter card, a time-out In connection with bus arbitration, or another serious malfunction. The NMI may only beserviced by the CPU on the motherboard. However, for this the CPU needs to be In control ofthe system bus, because the program code of the accompanying Interrupt handler 2 must beread from memory. Therefore, an NMI always forces the CACP to snatch away the system busfrom another active busmaster, and to pass control to the CPU.

The lowest priority Ofh of the CPU means that the CPU on the motherboard is always In controlof the system bus if no other busmaster requests bus control No arbitration signal line isnecessary for this. Instead, the CACP automatically assigns the CPU control by means of theHOLD and HLDA processor signals, in this case.

All other busmasters can request control of the bus via the PREEMPT signal Then, by meansof ARB0-ARB3, the bus arbitration passes control to one of the requesting busmasters accordingto a strategy using a largely equal treatment. For this, the following steps are carried out:

- The busmasters that want to take over control of the system bus set PREEMPT to a lowlevel

- The CACP activates ARB/ GNT to indicate that an arbitration cycle Is In progress.- Each of the requesting busmasters outputs its priority code via ARBG-ARB3, and compares

Its code with the code on ARB0-ARB3, which consists of the priority code of all the request-Ing busmasters.

- If Its priority code Is lower then It deactivates Its code on ARB0-ARB3 and rules itself outof the competition, but continues to drive PREEMPT to indicate that it wants to take overcontrol in a later arbitration cycle.

- After a certain time period (in the PS/2 300 ns are usually available for this purpose), onlythe highest priority code is still present on ARB0-ARB3.

~ The CACP pulls ARB/GNT down to a low level to Indicate that the bus control has passedto a new busmaster (GNT = grant) whose priority code Is present on ARB0-ARB3.

- The new busmaster deactivates Its PREEMPT signal. All other busmasters which were unableto take over control continue to drive PREEMPT to a low level

- Now the new busmaster can control the bus for one bus cycle.- Burst busmasters that want to transfer a whole data block and are allowed to keep control

of the system bus for at most 7.8 us (the maximum allocation time for external busmasters)are an exception to this rule. Such busmasters activate the BURST signal to Inform the CACPthat an arbitration cycle shall not be carried out for every bus cycle. But if PREEMPT or arefresh request is active, an arbitration cycle is executed nevertheless. Thus, BURST only hasan effect if the current burst busmaster is the only one requesting control of the system bus.

- Afterwards, the CACP releases control to the CPU or starts a further arbitration cycle ifPREEMPT Is driven low by another busmaster.

Every busmaster adapter has a local bus arbitrator which drives the adapter card's PREEMPT andARB0-ARB3, and compares the priority code of the busmaster adapter with the overall codeARB0™ARB3.

If the busmaster does not release control after 7.8 us, the CACP Interprets this as a malfunction*It disconnects the busmaster from the bus, passes control to the CPU, and issues an NML

The CACP can be programmed via the arbitration register at I/O address 090h (Figure 23.2).

5 4 3 2 1 0O

o

}xPC: CPU cycles during arbitration cycle

1 =yes 0=no (standard)

MAS: mask

1 =ARB//GNT always high 0=normal arbitration

EXT: extended arbitration cycle

1=600ns 0=300ns

PC4-PC0: reading=priority code of the busmaster that won the last arbitration

writing=not defined, always equal 0

Figure 232: Arbitration register (Port 090h).

If you set bit uPC equal to 1, the CPU on the motherboard executes further bus cycles, forexample to fetch instructions while the CACP carries out an arbitration cycle. For the busarbitration only the lines PREEMPT and ARB0-ARB3 are required, which are not used duringa CPU bus cycle. Therefore, the two cycles do not affect each other. If MAS Is set the CACPalways drives the ARB /GNT signal high, that is, always Indicates an arbitration cycle. As longas MAS is set, only the CPU is In control of the system bus, and all other busmasters are lockedout. By means of EXT, the arbitration cycle can be enhanced from the standard 300 ns up to600 ns. This is' advantageous if slow devices are present in the system. Finally, the five bitsPC4-PC0 indicate the priority code of the device that last won the bus arbitration. When writinginto the register, bits PC4-PC0 have no meaning and should always be set equal to 0.

233 Memory System

The PS/2 memory system has also been improved with the development of the microchannel.If the startup routine of the PC detects a defect in main memory, the memory is reconfiguredin 64 kbyte blocks so that eventually a continuous and error-free main memory again becomesavailable. The block with the defect is logically moved to the upper end of the main memoryand locked against access. If such a defect occurs in the lower address area in an AT, the wholeof the main memory from the defective address upwards becomes unusable.

For the PS/2 models 70 and 80, two memory configuration registers at the port addresses eOhand elh are additionally available. Using these ports, the division of the first Mbyte in RAM canbe controlled so that, for example, the ROM BIOS is moved into the faster RAM (shadowing),or the memory is divided to be as RAM-saving as possible (split-memory option). These pos-sibilities are not discussed here in detail because these setups can usually be done with the helpof the extended PS/2 setup during the course of the boot process.

572 Chapter 23 32-bit MicroChannel - Revolution573

23.4

In terms of their functions, the microchannel's support chips differ very little from their EISAcounterparts, but they are completely harmonized with this new and advanced bus system.Thus, for example, the DMA controller always carries out a 32-bit DMA transfer for the com-plete address space if a 32-bit microchannel is present. There Is no 8237A-compatible DMAtransfer. Moreover, the microchannel architecture allows all eight DMA channels to be activesimultaneously. Thus, MCA Is really well suited for multitasking operating systems.

Originally, in the PS/2 only a 16-bit DMA controller was Intended, which could only serve thefirst 16 Mbytes of memory. Here again you can see the enormously fast development in the fieldof microelectronics. Although the microchannel and the PS/2 were intended as a new standardto replace the AT and last for years, the 16 Mbytes (which seemed astronomically large a fewyears ago) are no longer enough, since memory-eaters like OS/2 and Windows have appeared.Modern motherboards can usually be equipped with 128 Mbytes of memory.

As well as the bus system and the DMA controller, the interrupt controller was also harmonizedwith the new architecture. All interrupts are level-trigger invoked only. With EISA, on the otherhand, Interrupts can be level- or edge-triggered so that an ISA adapter can be operated as theserial interface adapter, which operates exclusively with edge-triggering in an EISA slot. Be-cause of the level-triggering used in MCA, various sources can share one interrupt line IRCx.Additionally, level-triggering is less susceptible to interference, as a noise pulse only leads to avery short voltage rise but level-triggering requires a lasting high level. For the microchannel,255 different hardware interrupts are possible; the AT allows only 15. The assignment of theIRQ lines and the correspondence of hardware interrupt and Interrupt vector coincides withthat In the AT and EISA.

Failsafe Timer

The MCA times comprises four channels in total, and is equivalent to an 8254 chip with fourcounters. The first three channels 0-2 are occupied by the internal system clock, memory refreshand tone generation for the speaker, as Is the case In the AT. The fourth timer Is used as afailsafe or watchdog timer In the same sense as for EISA. It issues an NMI If a certain timeperiod has elapsed, thus preventing an external busmaster from keeping control too long andblocking necessary interrupts or the memory refresh. If an external busmaster retains control ofthe MCA bus for too long, and thereby violates the bus arbitration rules, this Indicates a hard-ware error or the crash of an external busmaster. Then the failsafe timer Issues an NMI and thearbitration logic releases control to the CPU again so that it can handle the NMI.

On the PC/XT/AT, timer 1 for memory refresh Is programmable, but on the PS/2 It is not. IBMthus wants to avoid nosy users who like to experiment with changing the refresh rate and

crashing the PC because of too few refresh cycles. Programmers can access the timer via port041h, but passing new values doesn't have any effect on its behaviour.

23.7 I/O Ports and I/O Address Space

As for EISA, in the PS/2 the support and controller chips are also accessed via ports. Table 23.2lists the new I/O address areas for MCA. Unlike ISA, the MCA slots, and therefore also theinserted MCA adapters, can be addressed Individually. To do this, however, you must explicitlyactivate a slot for a setup. This is necessary to configure MCA adapters with no DIP switchesautomatically.

Address Meaning000h-01fh master DMA020h-021h master 8259A040h-043h timer 1044h-047h failsafe timer060h-064h keyboard/mouse controller070h-071h real-time clock/CMOS RAM074h-076h extended CMOS RAM080h-08fh DMA page register090h CACP091 h feedback register092h system control port A096h adapter activation/setup registerOaOh-Oafh slave 8259AOcOh-Odfh slave DMAOeOh-Oefh memory configuration registerOfOh-Offh coprocessor100h-107h POS registers 0 to 7200h-20fh game adapter210h-217h reserved220h-26fh available278h-27fh 2nd parallel interface2b0h-2dfh EGA2f8h-2ffh COM2300h-31fh prototype adapter320h-32fh available378h-37fh 1st parallel interface380h-38fh SDLC adapter3a0h-3afh reserved3b0h-3b3h monochrome adapter3b4h-3bah VGA3bch-3beh parallel interface3c0h-3dfh EGA/VAG3e0h-3e7h reserved3f0h-3f7h floppy controller3d8h-3ffh COM1

Table 232: MCA port addresses

574 Chapter 23 32-bit MicroChannel - Revolution 575

M POS register Bit

There Is also a significant advantage here compared to the old AT concept that of the automaticidentification of an adapter by the system, MicroChannel adapters, like their EISA counterpartsare no longer configured by jumpers. This can Instead be carried out In a dialogue with theaccompanying system software. For this purpose, IBM assigns every adapter an Identificationnumber which can be read and analysed by the system. Also, third-party manufacturers get anidentification number for their MCA products which is centrally managed by IBM, The configu-ration information is stored in an extended CMOS RAM (as is the case with EISA). Additionally,you may activate or disable Individual MCA slots, thus a defective or suspicious adapter canbe disabled until the maintenance technician arrives, without the need to open the PC andremove the adapter. This also allows you to operate two adapters alternately, which normallydisturb each other, without pottering around the PC all the time,

To achieve these advantages, all MCA adapters and the MCA motherboard hold so-calledprogrammable option select (POS) registers. They always occupy the I/O address area OlOOh to0107h. Table 233 lists the registers.

Number

01234567

3/0 address

OlOOh0101 h0102h0103h

0104h0105h0106h0107h

IVieariii/ig

adapter identification ID (low-byte)adapter identification ID (high-byte)option byte 1option byte 2option byte 3option byte 4

sub-address extension (low-byte)sub-address extension (high-byte)

Table 233: POS registers

During the boot process the POST routine of the BIOS reads the adapter Identification ID andcompares it with the configuration data which is held In the CMOS RAM. The adapter Identi-fication ID Is awarded centrally by IBM, that is, IBM assigns every manufacturer of an MCAadapter such a number for the product concerned. The four option bytes are available forthe adapter manufacturer to configure the Inserted adapter and thus fulfil the functions of theformer DIP switches. If the four option bytes are Insufficient, the manufacturer may implementan additional configuration register on the adapter card. They are accessed by means of the twosub-address extension registers.

Three bits In the POS registers are predefined, and are listed in Table 23.4. By means of the bitadapter activation In the POS register 2, the adapter concerned can be disabled or activated. If itis disabled the system behaves as if the adapter were not present. Therefore It is possible, forexample, alternately to operate two different graphics adapters with overlapping address areasIn a PS/2. Their addresses do not then disturb each other. If a hardware error occurs on anadapter which leads to an NMI, then bit 7 In POS register 5 is set to 0 and the adapter generatesan active CHCK signal. If additional status information is available in POS registers 6 and 7,

255

067

Meaning .

adapter enablestatus for channel check availablechannel check active

Table 23.4: Reserved POS register bits

the adapter also sets bit 6 to a value of 0. The remaining bits are freely available for Implement-ing software option switches which replace the previous DIP switches.

The POS registers are present at the same address on all adapters and the motherboard, thusaccess conflicts seem to be preprogrammed. To avoid this, two additional registers are Imple-mented, the adapter activation/setup register at I/O address 096h, and the motherboard acti-vation/setup register at I/O address 094k

Each adapter can be operated in two different modes:

- Active mode: the POS registers are not accessible and the adapter is operating normally. Youmay access the ordinary control registers (the DAC colour register on a VGA, for example).

- Setup mode: here only the POS registers are accessible, not the ordinary control registers.

Using the adapter activation/setup register you may activate a slot and thus an adapter well-suited for setup of and access to Its POS registers. Figure 23.3 shows the assignment of this8-bit register.

7 6 5 4|o:| I ig 1 Reserved

CHR: channel reset0=no reset 1 =reset all adapters

res: reserved (=0)SET: adapter setup

0=normal mode 1 =setup modeSL2-SL0: adapter/slot select

000=slot1 001=slot2 010=s!ot3

3H-LLJCO

2 1< N | ^

111

0

I o Ulil

=SlOt 8

Figure 23.3: Adapter activation/setup register (port 096h).

The three least-significant bits define the selected slot or adapter. A set adapter setup bit activatesthis adapter for a setup. The CDSETUP signal for a slot n is thus activated, and the adapter isready for a setup.

Example: Activate adapter in slot 3 (note: the slots are enumerated 1 to 8 but the slot

selection with 0 to 7).

MOV al, 0000 1010b ; slot select=2, setup active

OUT Q96h, al ; write register

Now you can access the POS registers of the selected adapter card and configure the adapteror read the channel check bit.

576ru 37-bit MicroChannel - RevolutionChapter 23 \S——~

577

If the channel reset bit is set in register 096h, the CHRESET signal is activated in the microcharineland all adapters are reset. Thus in the setup mode, channel reset must always be equal to 0.After completion of the configuration the adapter activation bit in POS register 2 must be set toenable normal functioning of the adapter. This only refers to the adapter's logic. Write the valueOOh into the adapter activation/setup register afterwards to enable the adapter (CDSETUP risesto a high level). This only refers to driving the adapter.

Besides the adapters, the motherboard also comprises various setup registers which may beactivated by means of the motherboard activation/setup register at I/O address 094h. Figure23.4 shows the structure of this register.

7 6 5 4 3 2 1 0

I H ReservedIco

STB: setup of board units except VGA

0=setup mode 1 =normal modeSTV: VGA setup

0=setup mode 1=normal moderes: reserved (=0)

Figure 23 A: Motherboard activation/setup register (Port 094h).

If you clear the STV bit (set equal to 0) then you can configure the VGA option bytes. With avalue of 1 in this register the VGA operates normally. To the board units belong the VGA, RAM,floppy controller, and serial and parallel interfaces. If the STB bit is set equal to 0 then you canaccess POS registers 2 and 3 of the motherboard units and configure them. As is the case withadapters, these POS registers are present at I/O addresses 102h and 103h. The structure of POSregister 2 is shown in Figure 23.5. POS register 3 serves to configure the RAM, and Is verymodel-dependent. Thus, only POS register 2 Is described in further detail here. Informationconcerning POS register 3 can be found In the technical reference manual for your PS/2. For allother users, this Information Is of no value.

In extended mode the parallel port can be operated bidirectionally. The remaining bits are self-evident.

The adapter activation/setup register (port 096h) structure ensures that you can only activatea single slot for a setup, thus setup conflicts on the adapters are Impossible. However, note thatyou may put an adapter and the motherboard simultaneously Into the setup mode. This inevi-tably leads to problems, and damage to chips may even occur. Therefore, be careful whenprogramming the setup!

As was the case for EISA, every MCA product comes with a configuration disk which holds afile containing the necessary Information. This file Is called the adapter description file (ADF). Thefilename has the format «@iiii.adf», where iiii Is the four-digit adapter identification number inhexadecimal notation. Like EISA, the ADF also uses a configuration language that reminds usof CONFIG.SYS commands.

— •

7

PP

X

6

PP

1

5Odd

4

PP

E

3

SP

S

2

SP

E

1

FLE

0

MB

E

ppX: extended mode of the parallel port0=no extended mode (standard) 1 =extended mode

PP1, PPO: parallel port select00=LPT1 (standard) 01 =LPT2 11 =LPT3

PPE: parallel port enable0=disabled 1 =enabled (standard)

SPS: serial port select0=GOM1 (standard) 1=COM2

SPE: serial port enable0=disabled 1 =enabled (standard)

FLE: floppy controller enable0=disabled 1 =enabled (standard)

MBE: motherboard unit enable (except VGA)0=disabled 1 =enabled (standard)

t

Figure 23.5: Motherbaord POS register 2 (Port 102h).

23.9 On-board VGA and External Graphics Adapters

A main emphasis of the PS/2 concept is the integration of many units on the motherboardwhich previously have been located on separate adapter cards in a bus slot. To these unitsbelong, for example, the serial and parallel interface, and especially the video graphics array(VGA). All these units are accessed by means of the local channel or the peripheral standard bus.The VGA is functionally identical to (and also available as) the video graphics adapter (VGA) forAT and EISA computers. Original VGA (that is, the video graphics array) is integrated on thePS/2 motherboard, but the video graphics adapter is implemented as an adapter for a bus slot.Thus, a PS/2 computer with an integrated VG array needs significantly fewer slots than an ATor EISA computer.

For some users even the video graphics array with a resolution of 640 * 480 pixels and 256 coloursis not sufficient. In particular, high-resolution graphics applications like CAD need-more power-ful adapters. These adapters may be inserted into a bus slot, of course, but the only problemis that the VGA on the motherboard is still present and must be disabled for correct operationof the new adapter. Removing the VGA is naturally impossible. Instead, IBM had a moreelegant idea. One MCA slot in every PS/2 comprises a so-called video extension (see Figure 23.6).An MCA graphics adapter must always be inserted into this slot to service the graphics signals.By pulling some of these signals to a low level, the inserted adapter can deactivate parts of theon-board VGA and generate the corresponding signals itself. For this purpose, the connectedmonitor need not even be plugged in differently (if it accepts the new video mode, of course);it is still driven by the same plug of the PS/2. Internally, though, the change can be immense.For example, the high-resolution 8514/A adapter with a dedicated graphics processor pulls theESYNC, EDCLK and EVIDEO signals to a low level. Then it generates its own synchronization,pixel clock and colour signals for the monitor which it transfers by means of the contacts

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uqYNC VSYNC BLANK, DCLK and P0-P7 to the motherboard's logic to drive the monitorThus the on-board VGA is more or less disabled and the monitor cut off. Only the DAC is sbUrunning, converting the digital video data P0-P7 to an analogue signal for the monitor. Allcontrol and pixel signals come from the 8514/A.

The PS/2 Model 30 occupies a special position. It is actually a hidden XT with the outwardaonearance of a PS/2 case. The model 30 thus has no microchannel, but instead the old XT bus.fhe only advantage is that the model 30 is already prepared for the 1.44 Mbyte floppy and harddisk drives, and thus also has a much more modern BIOS.

23.11 The IViCA Slot

After deciding to throw the AT concept overboard, IBM was of course free to redesign thelayout of the bus slots. Also, for a PS/2 there should be 8-bit adapters (for example, parallelinterface adapters), 16-bit adapters for models 50 and 60 with 80286 or ^ F " 0 * * ^32-bit adapters (for example, fast ESDI controllers for the PS/2 models with l386 or i486 CPUs).Thus 8- 16- and 32-bit slots are required, with the 8-bit slot already implementing all theimportant control lines. The result is the MCA slot with various slot extensions, as shown mFigure 23.6=

The kernel of the MCA slot is the 8-bit section with its 90 contacts. Unlike EISA, the MCA slotonly has contacts on a single layer, but they are much narrower and every fourth contact of arow is grounded or at the power supply level. The ground and supply contacts on both sidesare shifted by two positions so that, effectively, every second contact pair has a ground orsupply terminal. By the defined potential of these contacts, the noise resistance is significantlybetter than on an AT.

The AT had up to 31 succeeding signal contacts without any interposed ground or supplycontacts. With the EISA slot, the noise sensitivity is slightly reduced because the lower EISAcontact row has significantly more such contacts than the AT section of the EISA slot.Besides the 8-bit section there are various extensions: the 16-bit section for 16-bit MCA adapters;the 32-bit section for 32-bit MCA adapters; the video extension for additional graphics adapters;and the matched-memory extension for memories with a higher access rate. The 16-bit PS/2models do not have any 32-bit extensions, of course. Because of the narrow contacts, the MCAslot is nevertheless quite compact, although it holds up to 202 contacts.

Figure 23.6: The MCA slot. This section discusses the MCA contacts and the meaning of the signals which are supplied or

applied.

580 Chapter 23 32-bit MicroChannel - Revolution 581

Because the microchannel supports busmasters on external adapters without any restriction, allconnections are bidirectional To show the data and signal flow more precisely, 1 have assumedfor the indicated transfer directions that the CPU (or another device on the motherboard) rep-resents the current busmaster. The enumeration follows the original IBM convention; I indicatesthe (according to the figure) left contact, and r the right contact. The MCA connections aregrouped corresponding to their functions.

Video Extension

BLANK (I)Terminal V8r

A high-level signal from the inserted adapter blanks the screen.

DCLK (I)Terminal V4r

The data clock signal from the inserted adapter supplies the pixel clock for the OAC.

EDCLK (I)Terminal V5r

A low-level enable DCLK signal from the inserted adapter cuts the VGA on the motherboardoff from the pixel clock line to the video OAC. Instead, the DAC uses the clock signal DCLKfrom the inserted adapters.

ESYNC (I)Terminal VI01

A low-level enable synchronization signal from the inserted adapter causes the VGA on themotherboard to be cut off from the three synchronization signals VSYNC, HSYNC and BLANK.

EVIDEO (I)Terminal VI r

A low-level enable video signal from the inserted adapter cuts off the VGA on the motherboardfrom the palette bus. Using this, the inserted adapter can supply the video data P7-PD.

HSYNC (I)Terminal V9r

A high-level horizontal synchronization pulse from the inserted adapter causes a horizontalsynchronization, that is, a horizontal retrace of the electron beam.

P7-P0 (I)Terminals V21-V41, V61-V81, V2r, V6r

These eight signals form the binary video data for the video DAC (digital to analogue converter)on the motherboard, which then generates the analogue signal for the monitor. By means of theeight bits P7-PQ, the 256 simultaneously display able colours of the VGA can be encoded.

VSYNC (I)Terminal VI Or

A high-level vertical synchronization pulse from the inserted adapter causes a vertical synchro-nization, that is, a vertical retrace of the electron beam.

Matched Memory Extension

MMC, MMCCMD, MMCR (O, O, I)Terminals Mir, M3r M21

These three signals control the so-called matched-memory cycles. To carry out a matched memorycycle the bus controller activates the matched-memory cycle signal MMC. If the addressed unitsupports this cycle type, it returns an active matched-memory cycle return signal MMCR witha low level. Instead of CMD of the normal cycle, here the MMC command signal MMCCMD Isused for controlling the bus transfer.

8-bit, 16-bit and 32-bit Section

143 MHz (O)Terminal 41

This signal is the 14 317 180 Hz clock signal for timers and other components.

A31-AG (O)Terminals 61-81,101-121,141-161,181-201, 811-821, 841-861, 4r-6r, 8r-10r 12r-14r, 16r-18r, 82r-84r

These 32 connections form the 32-bit address bus of the microchannel.

AOL (O)Terminal 20r

A low-level address latch signal indicates that a valid address is present on the microchannel,and activates the address decoder latches.

ARBG-ARB3 (I/O)Terminals 24r-26r, 28r

These four arbitration signals Indicate (in binary-encoded form) which of the maximum 16possible busmasters has won the bus arbitration and gets control of the system bus.

ARB/GNT (O)Terminal 29r

If this arbitration/grant connection is on a high level, an arbitration cycle Is in progress. If ARB/GOT falls to a low level the arbitration signals ARB0-ARB3 are valid and Indicate the newbusmaster.

582 Chapter 23 32-bit MicroChannel - Revolution583

Audio, AudioGND (I, I)Terminals 11, 21

These two connections supply the tone signal and the accompanying tone signal ground to themotherboard. An adapter is thus able to use the speaker logic of the motherboard. The adapterapplies the tone signal which the system speaker outputs to the connection Audio.

BE0-BE3 (O)Terminals 761-781, 78r

These four byte enable signals indicate on which byte of the 32-bit data bus data is transferred.They correspond to the address bits AO and Al, therefore. The signals come directly from theCPU. BED refers to the least significant byte D0-D7 of the data bus, BE3 the high-order byteD24-O31.

BURST CO)Terminal 22r

A low-level signal instructs the bus system to carry out a burst cycle.

CHRDY (i)Terminal 36r

A high-level signal at this channel ready connection indicates that the addressed unit is ready,that is, has completed the intended access. Thus this contact transfers the ready signal fromaddressed devices on an adapter card. If CHRDY is low the processor or DMA chip extends thebus cycles; it inserts one or more wait states.

CHRDYRTN (i)Terminal 351

A high channel ready return level as the return signal from the addressed device indicates that

the I/O channel is ready.

1 CHRESET (O); Terminal 421

CDDS16 (I)Terminal 55r

The inserted adapter card applies a high-level signal to this card data size 16 connection to indicatethat it is running with a data width of 16 bits. Then the bus controller operates accordingly.

CDDS32 (I)Terminal 80r

If the inserted adapter card applies a low-level signal to this card data size 32 connection, it hasa data width of 32 bits.

COSETUP (iTerminal Ir

An active (low) card setup level instructs the addressed adapter to carry out a setup.

CDSFDBK (I)Terminal 361

An active (low) card select feedback level indicates that the addressed adapter card is ready.CDSFDBK is the return signal for the adapter selection.

CHCK (i)Terminal 321

Via this channel check contact the adapter cards apply error information to the motherboard toindicate, for example, a parity error on a memory expansion adapter, or a general error on anadapter card.

A high level at this channel reset connection resets all adapters.

CMD (O)Terminal 341

If the command signal CMD Is active (that is, low), the data- on the bus is valid.

O0-O31 (I/O)Terminals 381-401, 481-491, 511-531, 641-661, 681-691, 721-741, 37r-39r, 40r-42r, 49r-51r, 66r-68r,70r-72r, 74r-75r

These 32 connections • form the 32-bit data bus of the microchannel.

OS16RTN CDTerminal 44r

A data size 16 return signal with a low level from the addressed device indicates that the deviceis running at a data bus width of 16 bits. The bus controller thus splits 32-bit quantities into16-bit portions, and combines two 16-bit items into a single 32-bit quantity.

DS32RTN (I)Terminal 79r

A data size 32 return signal with a low level indicates that the addressed device is running at

the full data bus width of 32 bits.

IRQ3-IRQ7, IRQ9-IRQ12, IRQ14, IRQ15 (I)Terminals 221-241, 261-281, 551-571, 57r-58r

These 11 Interrupt request connections are available for hardware Interrupt requests fromperipheral adapters. The microchannel operates with level-triggered hardware Interrupts.IRQO (system clock), IRQ1 (keyboard), IRQ2 (cascading according to the second AT PIC), IRQ8

584 Chapter 23 32-bit MicroChannel - Revolution 585

(real-time clock) and IRQ13 (coprocessor) are reserved for components on the motherboard, andtherefore do not lead into the bus slots.

MADE 24 (O)Terminal 2r

A high-level memory address enable 24 signal activates the address line A24.

Terminal 34r

A high-level memory/IO signal indicates a memory cycle; a low-level signal an access to theI/O address space.

TR32 CDTerminal 801

A high-level translate 32 signal indicates that the external busmaster is a 32-bit device anddrives BE0-BE3 instead of SBHE.

For the extension of the standard MCA specification and the 32-bit streaming data proceduresto 64-bit SDPs the address contacts A0-A31 are used for data transfer and mapped onto the 32high-order data bits D32-D63.

All other contacts are reserved (res), are grounded (GND), or transfer supply voltages for chips(+5 V, -5 V) and interfaces or drives (+12 V, -12 V).

PREEMPT (I)Terminal 21 r

A low-level signal issues an arbitration cycle for passing the bus to various busmasters. Externalbusmasters activate PREEMPT to request control of the bus.

REF (O)Terminal 45r

The refresh signal is at a low level if the motherboard is currently executing a memory refresh.With this signal, the dynamic memory on adapter cards (for example, the video RAM) can alsobe refreshed synchronous to main memory. Thus the adapter does not need its own refresh logicand no additional time is wasted for refreshing DRAM on the adapters. The REF signal indi-cates that the address bus has a row address for the refresh.

SO, SI (O; O)Terminals 32r-33r

These two contacts transfer the corresponding status bits of the microchannel.

SBHE (O)Terminal 54r

A high-level system byte high enable signal indicates that the high-order data bus byte D8-D15of the 16-bit microchannel section transfers valid data.

Terminal 30r

A low-level signal at this terminal count pin indicates that the counter of the active DMAchannel has reached its terminal value and the DMA transfer is complete.