me 4447 / me 6405: introduction to mechatronics interrupts

Georgia Institute of Technology ME4447 / ME6405

Interrupts and Resets 1

ME 4447 / ME 6405: Introduction to Mechatronics

Interrupts and Resets

Rohan BansalEdward Chyau

Anirudh Rudraraju



Telephone Analogy

• How do we know if someone is calling?– Use polling

• Pick up the phone periodically and check if someone is there.

– Wait for an interrupt• Wait until the phone rings, then answer it.



Polling

• Loops and checks a register until a certain state is found

• Example – Wait for a 1 in the CCF bit of the ADCTL (from Lab 2):

LDX #$1030WAIT BRCLR 0,X #$80 WAIT



Interrupts

• A way to get the microcontrollers attention

• A signal is sent to the CPU when data arrives

• The CPU is free to execute other operations while waiting for data



Applications of Interrupts

• Critical signals– Switch power sources on power failure– Turn on fans when overheating– Notify the CPU when an error occurs

• Timers– Create interrupts at specified real times

• Receive input– Check when a button is pushed on a

controller



Drawbacks of Interrupts

• Interrupts can occur randomly– Makes testing and debugging difficult

• Additional hardware may be required to produce a proper interrupt signal



Interrupt Flow

1. Complete the current instruction

2. Save the current state to the stack

3. Identify the source of the interrupt

4. Activate Interrupt Service Routing (ISR)

5. Return to original program (RTI) and restore state



Interrupt Flowchart

SOFTWARE

INTERRUPT

COPY REGISTER CONTENTS TO

STACK

SET APPROPRIATE

BIT IN CCR

LOAD INTERRUPT VECTOR INTO

PROGRAM COUNTER

VECTOR TABLE

HARDWARE

INTERRUPT

MASK SET?

N

Y

EXECUTE INTERRUPT SERVICE ROUTINE

$FFC0

$FFFF

CONTINUE MAIN PROGRAM



Saving Current State to Stack

• Make sure the stack is the same at the end of your interrupt code

SP-9SP-8 CCRSP-7 ACCBSP-6 ACCASP-5 IXHSP-4 IXLSP-3 IYHSP-2 IYLSP-1 PCHSP PCL

SP After Operation

SP Before Operation



Interrupt VectorVector Address BUFFALO Address Interrupt Source CCR Mask Bit

FFC0 – FFC1 to FFD4 – FFD5 – Reserved –

FFD6 – FFD7 C4 – C6 SCI Serial System I

FFD8 – FFD9 C7 – C9 SPI Serial Transfer Complete I

FFDA – FFDB CA – CC Pulse Accumulator Input Edge I

FFDC – FFDD CD – CF Pulse Accumulator Overflow I

FFDE – FFDF D0 – D2 Timer Overflow I

FFE0 – FFE1 D3 – D5 Timer Input Capture 4/Output Compare 5 I

FFE2 – FFE3 D6 – D8 Timer Output Compare 4 I

FFE4 – FFE5 D9 – DB Timer Output Compare 3 I

FFE6 – FFE7 DC – DE Timer Output Compare 2 I

FFE8 – FFE9 DF – E1 Timer Output Compare 1 I

FFEA – FFEB E2 – E4 Timer Input Capture 3 I

FFEC – FFED E5 – E7 Timer Input Capture 2 I

FFEE – FFEF E8 – EA Timer Input Capture 1 I

FFF0 – FFF1 EB – ED Real-Time Interrupt I

FFF2 – FFF3 EE –F0 IRQ (external pin) I

FFF4 – FFF5 F1 – F3 XIRQ pin X

FFF6 – FFF7 F4 – F6 Software Interrupt None

FFF8 – FFF9 F7 – F9 Illegal Opcode Trap None

FFFA – FFFB FA – FC COP Failure None

FFFC – FFFD FD – FF Clock Monitor Fail None

FFFE – FFFF – RESET None



Interrupt Example

IRQ Handler Routine

Initialize Strings

Main IRQ Routine

Main Program Do Nothing Loop

IRQHANDLE ORG $3000LDAA COUNT * A <-- current countINCA * increment countSTAA COUNT * write back countLDX #MSG * print out msgJSR OUTSTRGLDX #COUNT * print out countJSR OUT1BYTRTI * all done – return

ORG $2000 * data sectionMSG FCC “Number of times button pressed:”

FCB $04COUNT FCB $00 * button counter

ORG $00eeJMP IRQHANDLE

ORG $2200 * main programCLI * enable interrupts

LOOP BRA LOOP * endless loopSWIEND



Types of Interrupts

• Non-Maskable Interrupts– Has priority over maskable interrupts– Always Interrupts program execution– 6 available non-maskable interrupts

• Maskable Interrupts– Adjustable priority level– Can be disabled by the I-bit of CCR– 15 available maskable interrupts



XIRQ

S X H I N Z V C

1 1

When a non-maskable interrupt occurs…

X-bit is set to 1, blocking other non-maskable interruptsI -bit is set to 1, blocking other maskable interrupts

X-bit cannot be set by software interrupt



IRQ

S X H I N Z V C

0 1

When a maskable interrupt occurs…

I -bit is set to 1, blocking other maskable interrupts

I-bit can be set by software in prevent the execution of interrupts using:

-SEI (Set Interrupt Mask)

I-bit can be cleared by software using:-CLI (Clear Interrupt Mask)



Copy Machine Analogy: Scenarios

Rohan (Student) Matt (TA) Dr. Ume

Regular Instruction IRQ XIRQ




S X H I N Z V C

0 0

S X H I N Z V C

0 1




S X H I N Z V C

0 1

S X H I N Z V C

1 1



Priority for Non-maskable Interrupts

1. Reset2. Clock Monitor3. COP Watchdog4. Illegal Opcode5. XIRQ6. SWI



Priority for Non-maskable Interrupts

7. IRQ8. Periodic Interrupt/Real-time Interrupt9. Timer Input Capture 110. Timer Input Capture 211. Timer Input Capture 312. Timer Output Capture 113. Timer Output Capture 214. Timer Output Capture 315. Timer Output Capture 416. Timer Output Capture 517. Timer Overflow18. Pulse Accumulator Overflow19. Pulse Accumulator Input Edge20. SPI Transfer Complete21. SCI Serial System



Highest Priority Interrupt Register (HPRIO)

• Used to increase the priority of 1maskable interrupt

• Located at $103C and set on pins 0-3• I-bit must be set to change priority• Default is IRQ



Highest Priority Interrupt Register (HPRIO)



IRQE in the OPTIONS

OPTION $10397 6 5 4 3 2 1 0

ADPU CSEL IRQE DLY CME CR1 CR0

0

1

IRQE = IRQ Select Edge Sensitive Only (Time Protected)

0 = IRQ configured for low LEVEL (default)1 = IRQ configured for falling EDGEs



What are Resets?

• Reset is used to force a microcontroller unit (MCU) to assume a set of initial conditions and to begin executing instructions from a predetermined starting address.

• Like interrupts, they fetch vectors to force a new starting point for further CPU operations.



Types of Interrupts• Power-On Reset (POR)• External RESET pin• COP Watchdog timer Reset.• Clock Monitor Reset• Interrupt vectors:



Power-On Reset (POR)

• Used only for power-up conditions to initialize MCU internal circuits.

• Applying VDD to the MCU triggers the POR circuit, initiates a reset sequence, and starts an internal timing circuit.

• A 4064 clock cycle delay after the oscillator becomes active, allows the clock generator to stabilize

• In some crucial applications which need a longer delay time, external POR circuits are used



COP Watchdog Timer Reset• COP is a timer system to detect software processing errors

• Software responsible for keep the watchdog timer from running out.

• Generates Reset request if it runs out.

• Watchdog Timing pulses are drawn from the E-clock.

• COP timer rate can be set by using CR1 and CR0 pins of System Configuration Options (OPTION) register.



Servicing the COP Timer

• 1. Write $55 to COPRST register to arm the clearing mechanism2. Write $AA to the COPRST register

• Any number of instructions can be performed between the above 2 steps

• Must be performed in the correct sequence before the timer times out

• Rates are set by bits CR1 and CR0 in COPRST register



Clock Monitor Reset• Detects a slow or stopped E clock• An E-clock frequency below 10 kHz is detected as a

clock monitor error• Enabled by setting the CME bit in OPTION• Useful as a backup for COP watchdog because CMR

requires no clock while COP does• CMR also provides additional level of protection by

generating a system reset if the MCU clocks are accidentally stopped.

• In case of systems where stop instruction is used, CME bit would first be cleared before calling the STOP command. After recover from STOP, it would be set back to 1 again.



External RESET• External Reset is generated when the user

manually presses the Reset button.• As soon as the RESET pin goes to Zero, and

internal Nchannel device is turned on.• This device holds the RESET pin to zero for 4 E-

clock cycles (Redundantly) after which it releases. • RESET pin is sampled after 2E clock cycles from

the time the Nchannel releases the pin. – If low : External Reset– If high: Internal Reset : either COP Watchdog or

Clock Monitor• Chance of Misinterpretation



Reset Priority

• If in case of External Reset, when RESET pin is not held long enough, the reset is tentatively assumed to have come from COP or Clock Monitor Systems.

• First checks for Clock monitor and then checks COP watchdog.

• If neither pending, normal reset vector is selected by default.



Central Processor Unit (CPU)

• CPU fetches reset vector from the appropriate address location(depends on the kind of reset; explained in detail later) during the first three cycles.

• Stack pointer and other CPU registers are indeterminate immediately after reset.

• X and I interrupt mask bits in the CCR are set to mask any interrupt requests.

• S bit in the CCR is set to disable the stop mode



Memory Map

• RAM and I/O mapping register (INIT) is initialized to $01, putting 256 bytes of RAM at locations $0000-$00FF and control registers at locations $ 1000-$103F.

• 8KB of ROM and 512 B of EEPROM may or may not be present depending on the values of the two bits in CONFIG register that enable them.

• CONFIG register being a EEPROM cell is not affected by reset or power-down.



(Reference: M68HC11E series Data Sheet)



Parallel Input/Output (I/O)• Strobe A Flag (STAF), strobe A interrupt (STAI), and handshake (HNDS) control bits in

parallel I/O control register are cleared (when operating in single chip mode).(This prevents interrupt from being enabled)

• PortC, Port D(bits 5-0), PortA(bits 0,1,2, and 7), and Port E are configured as general purpose high impedance inputs.

• Port B and bits 6-3 of PortA have their directions fixed as outputs and their reset state islogic 0.



Timer • Initialized to count of $0000• All output compare (OC) registers are

initialized to $FFFF• Use OC to program an action to occur at a specific time (when counter matches OC register, task is executed)

• Input capture registers are indeterminate.• IC records the time that an external event takes



• Real-Time Interrupt:– RTI interrupt flag is cleared, automatic

hardware interrupts are masked.

• Pulse Accumulator– Disabled (PAI pin defaults to a general

purpose input).



• Computer Operating Properly (COP) Watchdog– Enabled if NOCOP bit in CONFIG register is clear. Other wise

disabled.



• Serial Communications Interface (SCI)– Baud rate must be reestablished– Transmitter and receiver are disabled

• Serial Peripheral Interface (SPI)– Disabled by resetting

• Analog-to-Digital Converter (A/D)– Conversion complete flag is cleared by reset– ADPU bit is cleared, disabling A/D system



• Mode of operation– Determined by bits set in the HPRIO register



Process Flow out of Resets WhenTriggered

• Vector fetch (program counter• loaded with contents of specified• address)• S, X, and I bits set in the CCR• MCU hardware reset• Checks for interrupts



Low Power Mode

• To reduce power consumption of the controller

• Temporarily stops CPU operations until a reset or interrupt occurs

• 2 modes– WAIT– STOP



WAIT mode• Command: WAI• CPU always shut down during wait mode• CPU registers are stacked• Program is suspended until interrupted• On-chip crystal oscillator remains active• Power conservation depends on number of peripheral

systems shut down– A/D converter current can be eliminated by writing the ADPU bit

to 0– The SPI system is enabled or disabled by the SPE control bit– The SCI transmitter is enabled or disabled by the TE bit, and the

SCI receiver is enabled or disabled by the RE bit.



• Command: STOP + S bit of CCR is clear• Lowest possible power consumption• All clocks are stopped (crystal oscillator too)• Data in internal RAM is retained as long as• VDD power is maintained• Exit using RESET, XIRQ, or unmasked IRQ• XIRQ has 2 recover methods

– If X is set, returns to command following STOP– If X is clear, stacking sequence that leads to normal

XIRQ request



References• Interrupts made Easy by Mark Minasi (COMPUTE! ISSUE 149 / FEBRUARY 1993 / PAGE 60,

http://www.atarimagazines.com/compute/issue149/60_Interrupts_made_easy.php )

• http://coecs.ou.edu/Erik.E.Petrich/ddl/interrupts.html

• Previous Interrupts Lectures from ME 6405 (http://www.me.gatech.edu/mechatronics_course/ME4447_6405/ClassNotes.htm)

• Reference Manual, Technical Data, and User Guides for the HC11

me 4447 / me 6405: introduction to mechatronics interrupts

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