Memory in FPGAs

مرتضي صاحب الزماني

Inferring Memory

• Inferring Memory in XST:Distributed or block memory?

−XST implements small RAM components on distributed resources to achieve better performance.

−Small?− The threshold varies depending on:

− The device family− memory depth− The total number of memory bits

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Criteria for BRAM inferring

Use RAM Style to override these criteria and force implementation of small RAM and ROM components on Block RAMs.

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RAM Style

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attribute ram_style: string;

…attribute ram_style of {signal_name|entity_name}: {signal|entity} is"{auto|block|distributed|block_power1|block_power2}";

RAM Style• auto (default):

Looks for the best implementation for each inferred RAM, based on:

− Whether the description style allows block RAM implementation (synchronous data read)

− Available block RAM resources

• distributed:Manually forces to distributed RAM resources

• block:Manually forces to block RAM

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RAM Style• block_power1:

Minimally impacts performance

• block_power2:Provides more significant power reduction.Can significantly impact area and speed

Use block_power2 if:− Your primary concern is power reduction, and− You are willing to give up some degree of speed and

area optimization.

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BRAM Incorporation

• Three ways to incorporate BRAMs:1. Instantiate directly using primitives:

− Example: RAMB36E1 or RAMB18E1 in Virtex-6 and Virtex-7

− Enables low-level access to all BRAM features

2. CoreGen tool:− to generate a customizable core, such as

a FIFO, which includes BRAMs− BRAM contents can be initialized from a

file

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BRAM Incorporation

• Three ways to incorporate BRAMs:3. RTL inference:

− You must follow the synthesis tool coding style− Advantage: code portability to other chips (but

not to other tools)

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Modeling RAM in VHDL

• Single write port

• Two write ports

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type ram_type is array (0 to 255) of std_logic_vector (15 downto 0);

signal RAM : ram_type;

type ram_type is array (0 to 255) of std_logic_vector (15 downto 0);shared variable RAM : ram_type;

Modeling RAM in VHDL

• Write access (single write):

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use IEEE.std_logic_unsigned.allsignal addr : std_logic_vector(ADDR_WIDTH-1 downto 0); process (clk) begin if rising_edge(clk) then if we = ‘1’ then RAM(conv_integer(addr)) <= di; end if; end if;end process;

Modeling RAM in VHDL

• Write access (two write):

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use IEEE.std_logic_unsigned.allprocess (clk)begin if rising_edge(clk) then if we = ‘1’ then RAM(conv_integer(addr)) := di; end if; end if;end process;

Other forms in:

XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices

RAM Initialization• Example 1:

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type ram_type is array (0 to 31) of std_logic_vector(19 downto 0);signal RAM : ram_type :=(X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A", X"00300", X"08602",X"02310", X"0203B", X"08300", X"04002", X"08201", X"00500", X"04001", X"02500",X"00340", X"00241", X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021", X"0030D", X"08201");

RAM Initialization• Example 2:

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type ram_type is array (0 to 127) of std_logic_vector (15 downto 0);signal RAM : ram_type := (others => "0000111100110101");

• Example 3:

type ram_type is array (255 downto 0) of std_logic_vector (15 downto 0);signal RAM : ram_type:= ( 196 downto 110 => X"B8B8", 100 => X"FEFC" 99 downto 0 => X"8282", others => X"3344");

RAM Initialization• Example 4:

Read from a file

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type RamType is array(0 to 127) of bit_vector(31 downto 0);impure function InitRamFromFile (RamFileName : in string) return RamType is FILE RamFile : text is in RamFileName; variable RamFileLine : line; variable RAM : RamType;begin for I in RamType'range loop readline (RamFile, RamFileLine); read (RamFileLine, RAM(I)); end loop; return RAM;end function; signal RAM : RamType := InitRamFromFile("rams_20c.data");

Implementing General Logic with BRAM

If you cannot fit the design onto the device, place some of the logic into unused block RAM.XST does not automatically decide

which logic can be placed into block RAM

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Logic on BRAM

• To implement logic on BRAM1. Isolate the part of RTL code to be

placed into BRAM in a separate block.

2. Apply BRAM_MAP to the block− directly in HDL, or− In Constraint File (XCF)

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attribute bram_map: string;attribute bram_map of component_name: component is "{yes|no}";

Logic on BRAM

The logic must satisfy the following criteria:−All outputs are registered.−The block contains only one level of

Registers (Output Registers).−All Output Registers have the same

control signals.−The Output Registers have a

synchronous reset signal.

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