1K.Shibahara

Metal Gate and Junction Technologies for Leading Edge Devices

Kentaro Shibahara

Research Center for Nanodevices and Systems, Hiroshima Univ.

2K.Shibahara

3DCSSSystem

multi-chip information processing with wireless Interconnect

Tera-bit processing high RF performance devices

ggd

T

RCff

8max

gs

mT C

gf

2Parasitic series resistance should be low

Low resistive junction formationLaser Annealing

Gate resistance should be lowMetal gate

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Looking back the following 5 years activities for our COE Pj.

Metal Gate Technology

Shallow Junction Formation

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Recover EOT loss due to gate depletion.

Ion vs Jg trade-off

Lower resistivityRF application fmax

However, worfunctionappropriate to CMOS devices are needed.

Why metal gate?: Basic expectation

~ 0.4 nm (gate dope : 1 1020 cm-3)

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36404552596878901Metal ½ Pitch

.31.32.32.32.33.63.63.63EOT

1.31.41.41.51.61.92.02.1EOTLSTP

.32.32.32.32.32.64.65.65EOT

.9.9.91.01.11.21.31.4EOTLOP

.25.25.27.28.29.74.74.73EOT

.5.5.65.75.91.11.11.2EOTHP

20122011201020092008200720062005

Based on ITRS 2005 PIDS Table: Planar Bulk DevicesIntroduction Timing of Metal Gate

Shifted at 2006 update

Band edge workfunction is hard to obtain.6K.Shibahara

Tunable Workfunction: Single metal gate CMOS How?

by Pileup formation• Gate first process

Mo + N

• FUSI (Fully Silicided) gateNiSi and Pd2Si + P, As, Sb, B……

Our Target

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High density impurity pileup at metal/insulator interface

Dipole formation and Workfunction shift

Metal SiO2

X O SiO

O

_ +

Electron negativity difference Dipole formation

Workfunction Tuning by Pileup Formation

VG>0

Si-sub.

-----

+++++

SiO2Metal

Electric Dipole

oxFB tV /:Charge density

:Distancet

8K.Shibahara

P-18Workfunction Tuning of NiSi and Pd2Si Fully-Silicided Gates by PredopingT. Hosoi, K. Sano, M. Hino, and K. Shibahara

Evaluation of Chemical Structures and Work Function of NiSinear the Interface between NiSi and SiO2H. Murakami, H. Yoshinaga, D. Azuma, A. Ohta, Y. Munetaka, S. Higashi, S. Miyazaki, T. Aoyama, K. Hosaka, and K. Shibahara

Related PresentationFUSI

First, Mo results, then FUSI briefly

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Categollization: Processes for Metal/Metal Compound

Motolora+STM IEDM03

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Mo Fine patterning

Easy Fine PatterningHigh Selectivity against Oxide

Oxide 2 nm

Suitable for Gate First ProcessIn addition, workfunction tunable

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Nitrogen Solid-Phase Diffusion into Mo Gatep-Si (100)

Gate oxidation (5 nm)

Mo & TiN sputter (50 & 30 nm)

Nitrogen Solid-Phase Diffusion(800 C, 1min)

TiN removal

S/D implantation

Al wiring and PMA

LOCOS formation

( As : 5x1015 cm-2, 30 keV )

Gate formation

S/D activation annealing(900 C, 1min)

diode

MOSFET

Mo~ EV

Formation of N pileupMo~ -0.46eV

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Nitrogen Solid-Phase Diffusion into Mo Gate

10-14

10-12

10-10

10-8

10-6

10-4

0 1 2 3

w/o N-SPDMOSFETexpected (diode)

I d (A

)

Vg (V)

L/W : 1/10 mTox : 5 nm

Vd : 0.05 V

diodeMOSFET -0.1 eV

-0.46 eVMo

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Nitrogen Redistribution by S/D Activation Annealing

1019

1020

1021

0 10 20 30 40

Nitr

ogen

Con

cent

ratio

n (c

m-3

)

Relative Depth (nm)

Mo SiO2 Si

diode MOSFET

Reduction of N concentration in bulk Mo (N out-diffusion)

Mo-gate MOSFET

back-side SIMS

Modified Process Oxide Cover & TiN Cap

Reversible workfunction shift(-0.46 eV -0.1 eV)

Pileup reduction &

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Vth Dependence on Gate Length

1

1.2

1.4

1.6

1.8

2

0 5 10 15 20

V th (V

)

Lg ( m)

w/o N-SPD

oxide-cover

TiN-cap

Vth = -0.5V

Oxide cover: Vth ~0.15 VTiN Cap: Vth decreased as Lg decreased

Wg : 10 mTox : 5 nm

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Nitrogen Redistribution in Mo Gate (oxide-cover)

just after N-SPD

after S/D activation annealing

N pileup formation at Mo/SiO2interface

N pileup at bottom Mo/SiO2Interface redistributes to top and two side interfaces.

small Vth shift16K.Shibahara

Mechanism of Vth shift decrease (TiN-cap)

Nitrogen atoms distributed to bottom interface reduces as Lg reduced.

N pileups are also formed at side interfaces of Mo.

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Thus, combining Mo+N process to MOSFET fabrication process maintaining expected workfucntion value is a tough issue.

How about other metals?

Control of Workfunction

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04EDL Vol25 p337 C.Ren et al. Thermal Stability of Metal Workfunction

Important Issue for Gate First Devices.Integration scheme of dual metal is also ….

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Fabrication Flow for FUSI Gate

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FUSI Gate MOS Diode Fabrication with Predoping

p-Si(100)Gate oxidationPoly-Si deposition

P, As, Sb, B …. Predoping by Ion Implantation

Ni or Pd sputter depositionFull-Silicidation

Gate patterning

Activation annealing

Impurities

Impurities Solubility: Silicide << poly-SiImpurity CondensationPileup formation at Oxide Interface

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Workfunction Tunable Range of FUSI Gate

• Pd2Si that can be processed at lower temperature provided wide workfunction tunable range.• What is the origin of different results for NiSi?

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Characterization of NiSi FUSI MOS Interface

Source: Dr. Murakami’s presentationSpecimen: Made in Fujitsu

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Sb-O signal was disappeared after Ar+ sputteringnecessary for workfunction evaluation.

Oxidized Sb in SiO2 is essential for NiSi workfunction shift.Specimen: Made in Hiroshima Univ.

Quite different conclusion. Why?

Another Characterization of NiSi FUSI MOS Interface

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Influcence of Process Condition on Pileup Formation

450 C : M = -0.32eV500 C : no M shift

Source: Dr Hosoi’s Poster

Pileup peak concentration : 450 C > 500 CFUSI Workfunction Tuning: Sensitive to process condition

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Hot-Plate 250oC

Void

Needle Growth

metal

poly-SiSiO2

Silicide

Stage Heating

HighPd

LowSi

Silicidation TemperatureDiffusion Specie

Hot-Plate 300oC Undoped,P,Sb

UndopedP,As,Sb

As

Undoped, P,As,Sb

Heating Apparatus

Influence of Temperature and Doping: Pd2Si

Slow Heat up

Silicidation is sensitive to temperature and doping

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Jan. 27, 2007http://www-03.ibm.com/press/us/en/pressrelease/20980.wss

IBM Advancement to Spawn New Generation of Chips: “First fundamental change to basic transistor in forty years”

http://www.intel.com/pressroom/archive/releases/20070128comp.htm

Intel Transistor Technology Breakthrough Represents Biggest Change to Computer Chips In 40 Years

Press Release From IBM and Intel: Metal+high-k in 2008

Intel’s new gate stack???

Even if they really ship products in 2008, research on metal gate should be continued. We have not understand well nature of the new gate stack yet.

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Metal Gate Technology

Shallow Junction Formation

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Optimized Spike Annealing

(sub-seconds RTA by halogen lamp heating)

Ohuchi et al., 2002 IEDM(Toshiba)

Shallow Junction: Key Technology for MOSFET Scaling

"Diffusion Less"

"Diffusion Less" is the key word that represents a demand for post-spike annealing technologies.

We need this range!

Xj (Junction Depth) increase by diffusion

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Low temperature & Long durationSolid phase regrowth: hr-min

High temperature & Short durationFlash lamp: ms – sCW Laser Annealing: ms – sPulse Laser Annealing: ns

Candidates of Post-Spike Annealing

What is the best scheme for pulse laser?Our Target

LSA

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Summary of our activities on LA (Laser Annealing)

KrF Excimer Laser

HALA:Heat-assited LA

PMLA: Partial Melt LA

Solid State Green Laser

LA with light absorbing layer

Analysis of LA with phase switch

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Merits of Excimer Laser

Penetration DepthGreen (532 nm): 927 nmKrF Excimer Laser 5.5 nm

LA KrF Eximer Laser ( : 248 nm)Pulse Width: 38 ns

200 W Laser(1 J/pulse, 200 Hz)

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Schemes for Conventional Laser Annealing

a-Si

c-Si

liq.-Si

c-Si

c-SiFast re-crystallizationnon-equiribrium

Activation

solid-phaseepitaxy

c-SiMelt

non-Melt

Laser Irradiation= Heating Up

IonImaplantation

Cooling Down

Melting pointa-Si: 1100oC, c-Si: 1400oC

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HALA & PMLA Time Sequence

Substrate Temperature (Tsub): 250 – 525oC• Laser Energy Density (EL) : 200 – 600 mJ/cm2

• FWHM of Laser Pulse: 38 ns, Pulse Number: 1 Pulse

Temperature Profile

10 5 10

Tsub

Time [min]

Laser Irradiations (EL)Heating Up Cooling Down

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102

103

104

200 300 400 500 600 700

450oC

250oC

RT

She

et R

esis

tanc

e R

s [sq

.]

Laser Energy Density EL [mJ/cm2]

Tsub

Xj=21nm Xj>21nmA B C

Region B(300-400 mJ/cm2)Good activationwithout increasing Xj

Region Anonmelt

Region CXj > as Implantedbecause of c-Si melt

Sheet Resistance and Energy Density for HALA

TSUB: 450oC

HALA: Reduction of EL

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15352510.2450

RegrowthThickness

[nm]

RegrowthRate

[nm/min]

Tsub

[oC]

a-Si thickness ~ 11 nm

450oC: Partial Melt

525oC: non-Melt

SIMS Profile: 300 mJ/cm2

0 10 200

0.2

0.4

0.6

0.8

1

450oC525oC

Depth [nm]

SbCo

ncen

tratio

n[x

1021

cm

-3] EL: 300mJ/cm2SiO2 Si

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Basic Ideas of Schemes

PMLA: melt(Good activation) + non-melt(Diffusion less)

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Xj~ta, tEOR

melt LA

ta: Amorphizedlayer thickness

tEOR:Extendeddefects depth

tatEOR

SPE

Xj

PMLA

PMLA: Amorphization depth is free from junction depth

Advantage of PMLA

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XTEM before Laser Irradiation

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1017

1018

1019

1020

1021

-2 0 2 4 6 8 10 12 14XJ: 10.5 nm

2.5 nm/dec

No irradiation360 mJ/cm2

600 /sq.

Depth [nm]

Sb

Con

cent

ratio

n [c

m-3

]

10 nm Junction Formation with Sb and B

40K.Shibahara

Conclusions

• Achievements on metal gate and LA obtained during our COE Pj. term were reviewd.

• Metal gate and LA technologies are still exotic ones for Si LSIs. However, introduction to products is approaching.

• We will continue research to support industries by supplying better understandings on process, materials and so on related to these fields.

41K.Shibahara

Acknolowdgements

This work was a result of effort of many students and researchers at RCNS and adsm of Hiroshima Univ.