micro unit 2

8/12/2019 Micro Unit 2

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Chapter Objectives

Stored ProgramConcept

Addressing

AddressDecoding

CommodityMemories

Using MemoryChips

Timing


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Chapter Objectives

Reality of MemoryDecoding

Filling theMemory Map

Memory MapDetails

Separate I/O AddressSpace

EndiannessMemoryHierarchy


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Chapter Objectives

CachesHarvard

Architecture

Read OnlyMemory (ROM)

Current MemoryTechnology

Punch Cards ROM / PROM


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Chapter Objectives

More ElectrostaticMemories

MagneticMemories

More MagneticMemories

Optical Memories

Full AddressDecoding

Partial AddressDecoding


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Chapter Objectives

Designing Address Decoders

AddressDecoding withRandom Logic

Address Decoding with m-line-to-n-line Decoders

Address Decoding withPROM

Address Decoding withFPGA, PLA and PAL


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MEMORY

SECTION 1:


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The Stored Program Concept

The concept of a stored program is

attributed to John von Neumann.

Put simply it says: Instructions can be

represented by numbers and stored in the same

way as data.

Thus a bit pattern 01000001 could eitherrepresent the number 65 or a JUMP

instruction.


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The Stored Program Concept cont

Whilst it is rare that the same memory

locations are used as instructions and data it

does happen. Eg. When a program is loaded

and executed

Question: what is the difference between the von

Neumann architecture and the stored programconcept


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Determining Addressable Memory

A processor with a 12-bit address bus can

address up to 4Kwords of memory.

ARM produces byte addresses and has a 32-

bit address space, which allows the addressing

of 232separate bytes.


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Commodity Memories

All von Neumann computers need memory (some small

others large)

Small memories (a few Kbytes) are often on-chip withprocessors, etc.

Large memories could be in one or more modules

Several types of memory exist (cost trade-offs varyaccording to the system requirement)


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Memory Chips

The memory device shown is a 628512. This is a 4MbitSRAM chip organized as 512 Kwords of 8 bits each.

It therefore requires nineteen address lines and eightdata lines.


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Memory Chips (contd) The following table defines the memory chips behaviour.

Points to note:

All the control signals are active low

If the chip is not selected (/CS = H), nothing happens

Write enable overrides read operations

The data bus is bidirectional (either read or write saves pins)


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Timing Issues

When writing to memory it is important thatthe correct data is written to the correct

location; it is also important to ensure that no

other memory locations are corrupted.

It is important that the address is stable

during the write operation; if it is not, other

locations may also be affected. (see timing

diagram)


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Timing Issues (2)

The actual write strobe is a logical AND of the

write enable and chip select signals; both

must be active for data to be written.

The timing diagram shown is therefore only

one possible approach to strobing the

memory.


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Timing (contd)

Thetimingdiagram


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Timing cont(2)

Different processors (& different

implementations) encode timing differently.

This is okay, as long as timing is included

somewhere.


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Addressing

Some definitions: Bytenow standardized as eight bits.

Wordthe natural size of operands, whichvaries from processor to processor (16 bits inMU0, 32 bits in ARM). Usually the width of thedata bus.

Nibblefour bits or half a byte


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Definitions cont

Widththe number of bits in a bus or a register

Address rangethe number of elements which can beaddressed.

Typewhat the data represents.

This is really a software concept in that the hardware(usually) does not care whether a word is to be

interpreted as an instruction, an integer, a float, anaddress . This may, however, influence the size of thetransfer.


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Addressing cont

Because only one operation is happening at a

time the control signals and the data bus can

be shared over the whole memory.

The address bus provides a code to specify

which location is being used (addressed).


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Commodity Memories

D-type flip-flops

Convenient for synchronous logic (e.g. FSMs)

Very large area per bit

Transparent latches

Okay for logic but not as convenient

Smaller than D-types, but still large


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Commodity Memories (2)

SRAM Small area per bit

Need (shareable) interface logic

Simple to use

DRAM

Very small area per bit Need considerable interface logic

Many awkward timing constraints


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Memory Decoding

In reality a memory address may not always

refer to one memory location.

For example an ARM processor can address

memory in 32-bit words or 8-bit bytes (or 16-

bit halfwords) and the memory system must

be able to support all access sizes.


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Memory Decoding (2)

Addresses are decoded to the minimum

addressable size (in this case bytes).

Thus the least significant bit used by the

address decoder is A[2];

A[1] and A[0] act as byte selects, which willbe ignored when performing word-wide

operations.


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Memory Decoding (3)

Bus addressing is normally written in the

format N[X,Y]

Notice that when the processor reads word

00000000 it receives data on all its data lines

(D[31:0]).


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Memory Decoding (4)

When the processor reads byte 00000000 it

receives data only on one quarter of the data

bus (D[7:0]).

Evidently, the last two bit positions determine

the subset of the data bus which should be

used.


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Separate I/O Space

I/O access patterns different from memory accesses I/O access being rarer

Separate address space for I/O (e.g. x86 architecture)

Cleaner address space left just for true memory

I/O space referenced with different instructions (e.g. INand OUT ) limited addressing modes and,

possibly, a smaller address range

Same bus (with an added address line IO/mem)


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Endianness

Refers to the way sub-elements are numberedwithin an element, for example the way bytes arenumbered in a word.

Two typesLittle endian and Big endian

By convention the bytes-in-a-word definition

tends to dominate, thus a big-endian processorwill typically still number its bits in a little-endianfashion .


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Little Endian Addressing

The LSB is at the lowest address.

Pick a word address; say 00001000, in a 32-bit

byte-addressable address space. Lets store a

word (say, 12345678) at this address.

Address 1000 contains byte 78



address 1003 contains byte 12


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Big Endian Addressing

The MSB is at the lowest address.

Using the same word address (00001000) forthe same word (12345678).






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Big Endian Addressing cont

This has the effect that, if displayed as bytes, amemory dump would look like: 00001000 1234 56 78

If a byte load was performed on the sameaddress the result would be: 00000012

NB: Choice of endianness in a given processoris arbitrary.


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Memory Hierarchy

For a given price big memory = slow memory

small memory = fast memory

If a programme has to run from main memory it

will only run at the speed at which its instructions

can be read.


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Memory Hierarchy cont

In reality typical programmes show a great dealof locality

If the critical 10% of the code is placed in a small,fast memory then the performance of the overallprogramme can be significantly increased.

Depending on the implementation it may beknown as caching orvirtual memory.


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Caches

Two observations: Large memories (at an economical price) tend to

be slower than small ones.

A program spends 90% of its time using 10% ofthe available address space.

Memory need not be homogenous


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Caches cont

If you can organize things so that the most

used address space is in fast memory, then

you can get startling improvements at

relatively small cost.

This is sometimes manually possible. Eg.

Embedded controllers where software is fixed.


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Caches cont(2)

In general purpose machines (e.g. PCs) the code isdynamic .

A cachememory adapts itself to prevailing

conditions by allowing the addresses it occupies to

change as the program runs. It relies on

Spatial Localityguessing that if an address is used others

nearby are likely to be wanted.

Temporal Localityguessing that if an address has been

used it is likely to be used again in the near future.


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Cache Hierarchies

Caches work so well that it is now commonpractice to have a cache of the cache.

This introduces several levels of cache or acache hierarchy.

The first level (or L1) cache will beintegrated with the processor silicon(onchip).


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Caches Hierarchies cont

There will be a second level of the cache

(L2); this may be on the PCB or on the CPU

Further cache levels are also possible; L3 is

increasingly common in high-performance

systems.


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Harvard Architecture

Normally refers to stored program computers with

separate instruction and data buses.

This separation may apply to the entire memoryarchitecture or may be limited to the cache

architecture . (see next two slide)

The Harvard architecture logically separates the

fetching of instructions from data reads and writes.


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You might like to identify and label the buses here. Where should the I/O be in

each?


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Memories

RAMRandom Access Memory (by convention usedfor memory which is readable and writeable)

RAM forgets when the power is turned off

The address space of a computer will normally containRAM

ROMRead Only Memory (cannot be written to) Used to hold fixed programs


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Memory Technology- Static RAM (SRAM)

Fast Truly random access

Relatively expensive per bit

simple interface

Reasonable storage density

Consumes little power when not in use

Typical application: cache (speed), memory on

a mobile phone (low power)


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Memory Technology- Dynamic RAM (DRAM)

Significantly slower than a fast processor

Faster if addressed in bursts of addresses

Medium cost per bit

Complex interface forgets over time (in order of milliseconds)

needs to be constantly read and rewritten (refresh)

consumes power even when idle

Its big advantage is that it gives very dense storage Typical application: main memory of a PC (large, cost-

effective)


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Memory Technology- ROM

Mask programmed ROMs are

programmed during chip

manufactureCheap for large quantities

Used in ASIC1 applications


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PROMs are Programmable after

manufacture, using programming

equipment.

Each individual IC is separately programmed

(a manual operation).

Contents cannot be changed after

programming.


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EPROMs are Erasable and Programmable

(usually by exposure to strong ultra-violet

light) (1970s-1990s)

A technology in decline


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EEPROMs are Electrically Erasable. (1990s todate)

One of the most popular ROM technologies

Can be altered in-circuit

Require much more time to alter a location(writes take >100x the read time) than RAM


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Memory Technology- ROM (2)

Some require bulk erasure

Widely used for non-volatile store in

consumer applications such as telephones, TV

remote controls, digital cameras et al.

Flash Memory falls into this category


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Memory Technology- ROM (3)

Reprogrammable devices suffer a small but

cumulative amount of damage each time

they are erased/reprogrammed

Are only guaranteed for a limited number

(say, 100 000) of write operations


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Memory Technology- Magnetic Storage

Very slow (compared to processor speeds)

Variable in their access times (think of the

mechanics involved)

Read/writeable only in blocks

Cheap per bit


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Memory Technology- Optical storage

Very slow (compared to processor speeds)

Variable in their access times (think of themechanics involved)

Primarily (but not exclusively) read only

Extremely cheap per bit

Cheap to make as ROMs (think CDs, DVDs, )


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ADDRESS DECODING STRATEGIES

SECTION 2


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Address Decoding

Although memory space is said to be flat, itdoes not mean the physical implementation ishomogenous

Different portions of memory are used fordifferent purposes: RAM, ROM, I/O

Even if all the memory was of one type, westill have to implement it using multiple ICs


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Address Decoding

This means that for a given valid address, one

and only one memory-mapped component

must be accessed

Address decoding is the process of generating

chip select (CS*) signals from the address bus

for each device in the system

Arrangement of 2KB Memory Blocks


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Arrangement of 2KB Memory Blocks


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Decoding Logic for M1 and M2

000 000

000 7FF

000 800

000 FFF

001 000


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Address decoding methods

There are two types of address decoding:

Full address decoding

Partial address decoding


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Full address decoding

All the address lines are used to specify a

memory location

Each physical memory location is identified by

a unique address


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Recall

An Example


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An Example

using Binary Decoder

Lets assume a very simple microprocessor

with 10 address lines (1KB memory)

Lets assume we wish to implement all its

memory space and we use 128x8 memory

chips


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Solution

We will need 8 memory chips (8x128=1024)

We will need 3 address lines to select each

one of the 8 chips

Each chip will need 7 address lines to address

its internal memory cells

With this example, all the address space was

implemented. However this might not always

be the case.


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An Example


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An Example

using Random Logic

Lets assume the same microprocessor with

10 address lines (1KB memory)

However, this time we wish to implement only

512 bytes of memory

We still must use 128-byte memory chips

Physical memory must be placed on the upper

half of the memory map


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Solution using Decoding Table


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A More Difficult ExampleDevice Device Amount of

Description Name Memory toAddress .

ROM chip ROM1 4KBRAM chip RAM 4KBROM chip ROM2 8KBPeripheral 1 PERI1 2 bytes

Peripheral 2 PERI2 2 bytes


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Address Decoding Table

DEVICE ADDRESS LINE

23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

ROM1 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X X X

RAM 0 0 0 0 0 0 0 0 0 0 0 1 X X X X X X X X X X X X

ROM2 0 0 0 0 0 0 0 0 0 0 1 X X X X X X X X X X X X X

PERI1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 X

PERI2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 X

Full Address Decoding Schematic Diagram


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Full Address Decoding Schematic Diagram

Corresponding to Table


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Partial address decoding

Since not all the address space is

implemented, only a subset of the address

lines are needed to point to the physical

memory locations Each physical memory location is identified by

several possible addresses (using all

combinations of the address lines that werenot used)


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Example

Lets assume the same microprocessor with

10 address lines (1KB memory)

However, this time we wish to implement only

512 bytes of memory

We still must use 128-byte memory chips

Physical memory must be placed on the upper

half of the memory map

l


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Solution

i l dd di


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Partial Address Decoding


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Memory Map

Address Decoding Table for Partial


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Address Decoding Table for Partial

Address Decoding

DEVICE ADDRESS LINE

23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

ROM1 0 0 0 X X X X X X X X X X X X

RAM 0 0 1 X X X X X X X X X X X X

ROM2 0 1 X X X X X X X X X X X X X

PERI1 1 0 X

PERI2 1 1 X

Improved Partial Address Decoding Scheme


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Improved Partial Address Decoding Scheme

DEVICE A23 A22 A21 A20ROM1 0 0 0 0

RAM 0 0 0 1

ROM2 0 0 1

PERI1 0 1 0

PERI2 0 1 1

SPACE 1


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D i i Add D d


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Designing Address Decoders

Address Decoding with Random Logic

Address Decoding with m-line-to-n-line

Decoders

Address Decoding with PROM

Address Decoding with FPGA, PLA and PAL

m-line-to-n-line Decoders


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m line to n line Decoders

(e.g. 74LS138 Decoder)


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Al ll


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Also, recall

Ad

DEVICE MEMORYSPACE (BYTES)

ADDRESSRANGE


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ddressDecodingwith

PROM

ROM1 4K 000000000FFF

ROM2 4K 001000001FFF

ROM3 4K 002000002FFF

RAM 2K 00C00000C7FF

PERI1 256 00E00000E0FF

PERI2 256 00E10000E1FF

PERI3 256 00E20000E2FF

P


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PRO

M-based

Address

Decod

er

Im

plemen

tation


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Programming

of the

Address Decoding PROM

Address range of

CPU

System Address Lines System Device Enables

A15 A14 A13 A12 A11 PROM1 PROM2 PROM3 RAM1 PERIs

PROM Address Input PROM Data Output


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PROM Address Input PROM Data Output

A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

000000-0007FF 0 0 0 0 0 0 1 1 1 1 1 1 1

000800-000FFF 0 0 0 0 1 0 1 1 1 1 1 1 1

001000-0017FF 0 0 0 1 0 1 0 1 1 1 1 1 1

001800-001FFF 0 0 0 1 1 1 0 1 1 1 1 1 1

002000-0027FF 0 0 1 0 0 1 1 0 1 1 1 1 1

002800-002FFF 0 0 1 0 1 1 1 0 1 1 1 1 1

003000-0037FF 0 0 1 1 0 1 1 1 1 1 1 1 1

003800-003FFF 0 0 1 1 1 1 1 1 1 1 1 1 1

---------- - - - - - -do- -do- -do- -do- -do- -do- -do- -do-

00B800-00BFFF 1 0 1 1 1 1 1 1 1 1 1 1 1

00C000-00C7FF 1 1 0 0 0 1 1 1 0 1 1 1 1

00C800-00CFFF 1 1 0 0 1 1 1 1 1 1 1 1 1

00D000-00D7FF 1 1 0 1 0 1 1 1 1 1 1 1 1

00D800-00DFFF 1 1 0 1 1 1 1 1 1 1 1 1 1

00E000-00E7FF 1 1 1 0 0 1 1 1 1 0 1 1 1

00E800-00EFFF 1 1 1 0 1 1 1 1 1 1 1 1 1

00F000-00F7FF 1 1 1 1 0 1 1 1 1 1 1 1 1

00F800-00FFFF 1 1 1 1 1 1 1 1 1 1 1 1 1

Address Decoding with FPGA, PLA


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g ,

and PAL

Address decoding using general purposeprogrammable logic elements

the speed of random logic, and

the flexibility of the PROM

micro unit 2

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