micro unit 6

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PREMIER INSTITUTE OFFERING TECHNICAL EDUCATION FOR ENGINEERING STUDENTS IIT,AIEEE,PUC & GATE,IES,PSU [MICROPROCESSOR (UNIT-6)] (Memory Interface-1) Guided By:Anurag Trigun

1. With a neat diagram, explain the working of 8086 in the minimum mode. Also give the timing diagram of I/O write operation. [VTU 2010]

Mode of operation for Intel 8086 namely the minimum mode. When only one 8086 CPU is to be used in a micro computer system the 8086 is used in the minimum mode of operation. In this mode the CPU issues the control signals required by memory and I/O devices. The level of the pin MN/MX (active low) decides the operating mode of 8086. When MN/MX (active low) is high the CPU operates in a minimum mode. From pin 24 to 31 issue two different sets of signals. One set of signals is issued when the CPU is operating in the minimum mode.

Pin description for minimum mode

8086 Minimum Mode Block diagram

For the minimum mode of operation the pin MN/MX (active low) is connected to 5V DC supply that is MN/MX (active low) is equal to Vcc. The description of the pins from 24 to 31 for the minimum mode is as follows:

INTA (active low)(output) Pin No 24. Interrupt Acknowledge. On receiving interrupt signal the processor issues an interrupt acknowledge signal.

ALE (output) Pin No 25. Address Latch Enable. It goes high during T1. The microprocessor sends the signal to latch the address in to the Intel 8282/8283 latch.

DEN (output) Pin No 26. Data Enable. When Intel 8286/8287 octal bus transceiver is used, this signal acts as an output enable signal. It is active low.

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DT/R (active low)(output) Pin No 27. Data Transmit/Receive. When Intel 8286/8287 octal bus transceiver is used, this signal controls the direction of data flow through the transceiver. When it is high data are sent out. When it is low data are received.

N/IO (active low)(output) Pin No 28. Memory or I/O access. When it is high the CPU wants to access memory. When it is low, the CPU wants to access IO device.

WR (active low)(output) Pin No 29. Write. When it is low the CPU performs memory or I/O write operation.

HLDA (output) Pin No 30. Hold Acknowledge. It is used by the processor when it receives hold signal. When hold request is removed, HLDA goes low.

HOLD (input) Pin No 31. Hold. When another device in the complex microcomputer system wants to use the address and the data bus, it sends a hold request through this pin.

8086 system in the minimum mode configuration :

The microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1 .

In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. The remaining components in the system are latches, trans receivers, clock generator, memory and I/O devices. Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for




separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086.

Transreceivers are the bidirectional buffers and some times they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals. They are controlled by two signals namely, DEN and DT/R.

The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage. Usually, EPROM are used for monitor storage, while RAM for users program storage. A system may contain I/O devices.

The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle.

The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. During the negative going edge of this signal, the valid address is latched on the local bus.

The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a memory or I/O operation.

At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The read (RD) control signal is also activated in T2.

The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus.

The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tristate its bus drivers.

A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is again

asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location.

The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).

The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write.

The M/IO, RD and WR signals indicate the type of data transfer as specified in table below.

2. Write the note on the read bus cycle for the 8086 microprocessor with the timing diagram.




Timing diagram refers to the pictorial representation of the status of various pins during the different cycles of a bus cycle.The basic operation of reading/writing a byte from/to a memory location/a port is called a machine cycle. The time taken to complete a machine cycle is represented as T cy. A machine cycle is made up of many states.

Timing Diagram for Memory Read Machine Cycle

Instruction Cycle


S7 BHE

DEN

DT/R

RD

BHE/S7

ALE

IOM/

MN/MX

S6-S3 9AD1-AD16

Status Address Out

AD15-AD0 Data In Out

Address

CLK T4 T3 T2 T1 One Bus Cycle



The time taken to fetch and execute an entire instruction is referred to as an instruction cycle. An instruction cycle consists of one or more machine cycles.

In 8086, the concept of a machine cycle is not so relevant. The Execution Unit (EU) executes instruction in certain clock periods. These clock cycles do not constitute any form of machine cycles. The Bus Interface Unit (BIU) fetches instructions and operands from the memory. Any external access either to the memory or I/O device requires four clock periods. This group of four clock cycles is called the bus cycle. There is memory or I/O read bus cycle; memory or I/O write bus cycle.

• The 4 processor clock cycles are called T states. Four cycles is the shortest time that the processor can use for carrying out a read or an input cycle.

• At the beginning of T1, the processor outputs S2, S1, S0, A16/S3…A19/S6, AD0..AD15 and BHE#/S7.

• The 8288 bus controller transitions the ALE signal from low to high, thereby allowing the address to pass through the transparent latches (74HC373). The address, along with the BHE# signal is latched when ALE goes low, providing the latched address A0..A19.

• During T2 the processor removes the address and data. S3..S6 status is output on the upper 4 address/status lines of the processor.

• The AD0..AD15 signals are floated as inputs, waiting for data to be read. • Data bus transceivers (74HC245) are enabled towards the microprocessor (the READ direction)

by the DT/R# and DEN signals. • The MRDC# (ie MEMR#) or IORC# (IOR#) signal is asserted. • The signals are maintained during T3. At the end of T3 the microprocessor samples the input

data. • During T4 the memory and I/O control lines are de-asserted.

3. Write the note on the read bus cycle for the 8086 microprocessor with the timing diagram.

The bus cycle starts with the transition of ALE high and the generation of valid status bits S2:0. The bus cycle ends when WR transitions high (inactive), although data remains valid for one additional clock. The two types of write bus cycles are as follows.




Write Bus Cycle

The various events that take place in the write cycle (memory or I/O) can be summarized as follows.

• The 4 processor clock cycles are called T states. Four cycles is the shortest time that the processor

can use for carrying out a write or an output cycle. • At the beginning of T1, the processor outputs S2, S1, S0, A16/S3…A19/S6, AD0..AD15 and

BHE#/S7. • The 8288 bus controller transitions the ALE signal from low to high, thereby allowing the address

to pass through the transparent latches (74HC373). The address, along with the BHE# signal is latched when ALE goes low, providing the latched address A0..A19.

• During T2 the processor removes the address and data. S3..S6 status is output on the upper 4 address/status lines of the processor.

• Output data is driven out on the AD0..AD15 lines. • Data bus transceivers (74HC245) are enabled away from the microprocessor (the WRITE

direction) by the DT/R# and DEN signals. • The MWRC# (ie MEMW#) or IOWC# (IOW#) signal is asserted at the beginning of T3. • The signals are maintained during T3.




• During T4 the memory and I/O control lines are de-asserted. In simple Intel Architecture systems, the data is usually written to the memory or output device at the rising edge of the MWRC# or IOWC# signal.

4. With a neat diagram, explain the working of 8086 in the maximum mode. Also give the timing diagram of I/O write operation.

The maximum mode of operation the pin MN/MX (active low) is made low. It’s grounded. The major difference between the minimum mode and the maximum mode configurations is the need for the additional circuitry to translate the control signals. The circuitry is for converting the status bits S1 (Active Low), S2 (Active Low) and S3 (Active Low) into the I/O and memory transfer signals needed to direct data transfers, and for controlling the 8282 latches and 8286 transceivers. From the status the 8288 is able to originate the address latch enable signal to the 8282s, the enable and direction signals to the 8286 transceivers and the interrupt acknowledge signal to the interrupt controller. The description of the pins from 24 to 31 is as follows:

Maximum mode of 8086




QS1, QS0 (output) Pin no 24 and 25. Instruction Queue Status. These two pins allow the system external to the processor to interrogate the status of the processor instruction queue so that it can determine which instruction it is currently executing. The meaning of QS1 and QS0 are as follows:

QS1 QS0 Meaning 0 0 No operation 0 1 1st byte of opcode from queue 1 0 Empty the queue 1 1 Subsequent byte from queue

S0, S1, S2 (active low) (output) Pin No 26, 27 and 28. Status Signals. These signals are connected to the bus controller Intel 8288. The bus controller generates memory and I/O access control signals

8086 system in maximum mode:8086 system in the maximum mode configuration. In maximum mode configuration, in addition to the latches and bus transceivers, a bus controller is also employed for this configuration. The bus controller provides control signals as shown in figure. The important signals are

MRDC (Active Low) Memory Read Command




MWTC (Active Low) Memory Write Command IORC (Active Low) I/O Read Command IOWC (Active Low) I/O Write Command AMWC (Active Low) Advanced Memory Write Command. It is a memory write command issued earlier in the machine cycle. It gives memory an early indication of a write instruction. AIOWC (Active Low) Advanced I/O Write Command

5. Differentiate between 8086 and 8088 microprocessor.

8086 It has 16 data lines D0-D15

The instruction queue is of 6 bytes. From the memory the fetching of a

program is performed only once there are 2 byte empty in queue.

The BIU of 8086 is not as same as in the 8088 but the EU is similar.

8088 It has only 8 data lines D0-D7

it requires a 1 byte data width which is generated after the de multiplexing of AD0 to AD7 pins.

The instruction queue is 4-bytes.

Program fetching is performed as soon as there is a byte empty in queue


micro unit 6

Engineering