Microcomputer Systems 1Introduction to Blackfin DSPs

Veton Kpuska

*Veton Kpuska*DSP HardwareData Manipulation:IO & Memory IntensiveLow ALU utilization

Examples:Word ProcessingDatabase ManagementSpreadsheets

Typical Operations:Data MovementValue Testing

CharacteristicsNot real-time criticalNot predictableMathematical Calculations:Not IO & Memory intensiveHigh ALU utilization

Examples:Digital Signal ProcessingMotion ControlEngineering SimulationsReal-Time Processing

Typical Operations:AdditionMultiplicationVectorized Operations and Architectures

CharacteristicsExecution time crucialPredictable operations.Typically Computers are designed for:IO & Memory intensiveHigh ALU utilization

Veton Kpuska

*Veton Kpuska*General Categorization of Digital Processing HardwareMicrocontrollersI/O CapabilitySpeed not a critical factorLimited functions:AdditionMultiplicationDivisionCompact Instruction SetApplications:Industrial Process ControlElectronic ToysAppliancesExamplesPIC, Analog Devices 8051, TI TMS470

Veton Kpuska

*Veton Kpuska*General Categorization of Digital Processing HardwareMicroprocessorsSingle Chip CPUsComplex Architectures to allow for:Variety of applicationsGeneralityFlexibilitySpeedI/OGraphicsComputationsComplex Instruction Sets (CISC)To bridge the gap between hardware and software development needs.Reduced Instruction Sets (RISC)Highly optimized small number of instructions.Focus on speed of execution and structured architecture.Examples:CISC: Intel Pentium, Xeon, AMD Athlon RISC: Dec Alpha, PowerPC, ARM, SPARC

Veton Kpuska

*Veton Kpuska*General Categorization of Digital Processing HardwareDigital Signal Processors (DSPs)Highly specialized hardware architectures to perform:Multiply-add-accumulate (MAC) operationsExecution in one Clock cycleRepetitive operations with minimum or no overheadBasic Requirements:Fast ArithmeticExtended PrecisionDual Operand FetchCircular BufferingZero-overhead Looping

Veton Kpuska

*Veton Kpuska*Basic Processor Architectures Memory: Data & InstructionsAddress BusData Bus CPU Program Memory: InstructionsPM Address BusPM Data Bus CPU DM Address BusDM Data BusData Memory: DataVon Neumann ArchitectureHarvard ArchitectureProgram Memory: InstructionsPM Address BusPM Data Bus CPU DM Address BusDM Data BusData Memory: DataModified Harvard ArchitectureInstruction Cache

Veton Kpuska

*Veton Kpuska*Blackfin Processor ArchitectureThe Blackfin architecture was crafted with the requirements of a Controller and a DSP in mind 16/32-bit Embedded ProcessorProcessor designed for high signal processing performance.Utilizes RISC programming model. Hardware is based on Micro Signal Architecture (MSA) developed jointly by Intel Corporation and Analog Devices.MSA combines 32-bit RISC instruction set, 16-bit fixed-point dual multiply-accumulate (MAC) digital signal processing functionality8-bit video processing through four 8-bit ALUsUnified architecture provides both Microcontroller (MCU) & DSP functionality.

Veton Kpuska

*Veton Kpuska*Blackfin FeaturesEthernet, CAN (Controller Area Network), GPIO (General purpose Programmable Input Output), SPI (Serial Peripheral Interface), USB (Universal Serial Bus), UART (Universal Asynchronous Receiver Transmitter), TWI (Twin Wire Interface, RTC (Real Time Clock), SPORT (Serial Ports), Timers, WatchdogOptimized to perform EQUALLY well on both control and/or numeric algorithmsDynamic Power Management Glueless interface to many converter devices or LCDs through Parallel Peripheral Interface (PPI)

Veton Kpuska

Representation of Numbers & ArithmeticNumber Systems

Veton Kpuska

*Veton Kpuska*Time Quantization (Sampling) of Analog SignalsAnalog-to-Digital Conversion. Continuous Signal x(t). Sampled signal with sampling period T satisfying Nyquist rate as specified by Sampling Theorem. Digital sequence obtained after sampling and quantization x[n]

Veton Kpuska

*Veton Kpuska*ExampleAssume that the input continuous-time signal is pure periodic signal represented by the following expression:

where A is amplitude of the signal, 0 is angular frequency in radians per second (rad/sec), is phase in radians, and f0 is frequency in cycles per second measured in Hertz (Hz).

Assuming that the continuous-time signal x(t) is sampled every T seconds or alternatively with the sampling rate of fs=1/T, the discrete-time signal x[n] representation obtained by t=nT will be:

Veton Kpuska

*Veton Kpuska*Example (cont.)Alternative representation of x[n]:

reveals additional properties of the discrete-time signal.

The F0= f0/fs defines normalized frequency, and 0 digital frequency is defined in terms of normalized frequency:

Veton Kpuska

*Veton Kpuska*Reconstruction of Digital SignalsDigital-to-Analog Conversion. Processed digital signal y[n]. Continuous signal representation ya(nT). Low-pass filtered continuous signal y(t).

Veton Kpuska

Numbers and Their RepresentationHistorical View

Veton Kpuska

*Veton Kpuska*Representation of NumbersThe way we do arithmetic is intimately related to the way we represent the numbers. [D. Knuth The Art of Computer Programming, Volume 2, Seminumerical Algorithms, Third Edition]The development of civilization is closely followed by the development of number representations. Early Days:One pile of items replaced by another pile of different number of items of different kind.Standardization of valueA fixed number of items of one kind (e.g., 10 or ) placed in a special corresponding placeEquivalent to one item of special kind in other place .

Lead to earlier ways of representing numbers in written form.

Veton Kpuska

*Veton Kpuska*Representation of NumbersEarlier Number Systems:BabilonianEgyptian,Greek,Chinese, andRoman numerals.

Such notations inconvenient for performing arithmetic operations with exemption to the simplest cases.

Veton Kpuska

*Veton Kpuska*Earlier Days: Floating Point vs. Fixed Point NotationBabylonian Systems:Everyday system for relatively small numbers inherited from Mesopotamian civilizations:Based on grouping by tens, hundreds, etc.Large numbers seldom used.More difficult mathematical problems were considered by using sexadecimal (radix 60) positional notation. Sexadecimal notation was highly developed as early as 1750 B.C.This notation was unique in that it was actually a floating point form of representation with exponentials omitted.Proper scale factors or power of sixty was to be supplied by the context, so that, for example the numbers 2, 120, 7200, 1/30 were all written in an identical manner.

Veton Kpuska

*Veton Kpuska*Earlier Days: Floating Point vs. Fixed Point NotationMaya Indians Fixed Point Notation - 1 century A.D.Radix-20 SystemZero introduced ~ 200 A.D.

Veton Kpuska

*Veton Kpuska*Computing Devices - ArithmeticGreek Abacus at 2 century B.C.Row and Columns of pebbles correspond to our decimal system.Written form did not follow the positional notation of the decimal system.Greek astronomers make use of a sexadecimal positional notation. For fractions adapted from Babylonians.

Veton Kpuska

*Veton Kpuska*Modern Positional Number SystemsNumbers are represented by numerals[1]. In the past there were several kinds of numeral notations. More distinct ones are sign-value notation (e.g., Roman Numeral System) and positional notation or place-value notation that is commonly used today.

In the positional notation, the value of a number depends on the numeral as well as its position. Typically, the value of the position is the power of ten. For example, number represented by the numeral 1957 is equal to 7 ones, 5 tens, 9 hundreds, and 1 thousands. This concept leads to generalization of the value represented by a numeral as follows:

where: is sign of the number, are the set of numerals, is decimal, or in general radix point, and B is the base of the number system.------------------------------------------------- [1] Webster Dictionary defines numeral as: Function: noun 1 : a conventional symbol that represents a number

Veton Kpuska

*Veton Kpuska*Positional Number SystemsThe numerals are also called the digits. A digit dk for large k is often said to be more significant than the digits dk for small k:Most significant digit leading or the leftmost digitLeast significant digit traling or the rightmost digit.

In binary system (B=2), the binary digits are often referred as bits.In hexadecimal system (B=16) the hexadecimal digits are usually denoted by:0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F

Veton Kpuska

*Veton Kpuska*Digital Computing Devices - ComputersComputers, can only use a finite subset of the numbers due to finite resources available to represent a number. Consequently, only finite and limited set of numbers can be represented. This set is defined by the total number of elements that it can represent as well as the range of values that it covers.

Native representation of a numeral in a computer is in Binary system, or base B=2.

Veton Kpuska

*Veton Kpuska*Digital Computing Devices - ComputersThe numerical value in our custom reference base 10 number system of a base 2 (or binary) number is given by the following expression:

where: is sign of the number, take values from the set of binary numerals, and is binary point.

Veton Kpuska

*Veton Kpuska*DSPs and Fixed Point & Floating Point NotationsThe DSPs, similarly to general computer processors, support a number of data formats. The variety of data formats and computational operations determine DSP capabilities. Most general classification of DSP processors is in terms of their support of data types for various operations (e.g., addition, subtraction, multiplication and division). DSPs are thus categorized as fixed-point or floating-point devices.

Fixed-point data are computer representations of integer numbers. Floating-point data types are computer representations of real numbers.

Veton Kpuska

*Veton Kpuska*Computer Fixed Point RepresentationsIn theory of mathematics the range of values that a number can take is unlimited. That is, an integer number can take values ranging from to :Due to limitations of the hardware, the integer representations in a computer are restricted to a range that is directly dependent on the number of bits allocated for the numbers. For example, if a processor uses 4 bits to represent a number, there are total of 24 = 16 possible distinct combinations. If one would use those 4 bits to represent positive integers (called unsigned data type), the range of values that can be represented is thus 0,, 15. If positive as well as negative numbers are needed, half of the bits are used to represent positive and the remaining half represent negative numbers. It is necessary, therefore to use one bit from the set of bits allocated (e.g., typically Most Significant Bit or MSB is used, in this case bit number 3) to represent the sign of a number.

Veton Kpuska

*Veton Kpuska*Computer Fixed Point RepresentationsThere are several different binary number representational conventions [ref] for signed and unsigned numbers. Most notable are:Sign MagnitudeOnes ComplementTwos Complement

Example of 4-bit signed numbers is presented in the Table 5- 1 below for three formats listed above:

Veton Kpuska

*Veton Kpuska*Fixed Point Representations

Decimal ValueSign MagnitudeOnes ComplementTwos Complement+7011101110111+6011001100110+5010101010101+4010001000100+3001100110011+2001000100010+1000100010001+0000000000000-010001111--1100111101111-2101011011110-3101111001101-4110010111100-5110110101011-6111010011010-7111110001001-8--1000

Veton Kpuska

*Veton Kpuska*Fixed Point DSPsThe fixed-point DSPs hardware supports only fixed-point data types. Their hardware is thus more restrictive performing basic operations only on fixed-point data types. With software emulation, the fixed-point DSPs can execute floating-point operations. However, floating-point operations are done at the expense of the performance due to lack of floating point hardware.

Veton Kpuska

*Veton Kpuska*Fixed Point DSPsLower-end fixed point DSPs are 16-bit architectures. That is, the processors word length is 16 bit and its basic operations use 16-bit data types.

Typically, 16-bit DSP hardware also supports double precision 2x16=32-bit data type. (e.g., BF533 DSP)

This extended support may come at the expense of performance of the DSP depending on their hardware architecture and design. The 16-bit signed and unsigned data types format is given below in the Figure 5- 3

Veton Kpuska

*Veton Kpuska*Fixed Point DSPs

Veton Kpuska

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

215

214

213

212

211

210

29

28

27

26

25

24

23

22

21

20

Bit Position

Position Value

RadixPoint

Unsigned Number Representation

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

-215

214

213

212

211

210

29

28

27

26

25

24

23

22

21

20

Bit Position

Position Value

Sign Bit

RadixPoint

Signed Number Representation

*Veton Kpuska*Fixed Point DSPsThere are a number of possible fixed-point representations that DSP hardware may support. One example was presented in a Table in the previous slide. For 16 bit representations the ranges of numbers are given in the following Table in the next slide. Note that Analog Devices BF533 family architecture supports 2s complement integer formats. Clearly, the range of values (commonly referred in the literature as dynamic range) is proportional to the number of bits used to represent a number.

If the result of the operation exceeds the precision of the data type, in the worst case scenario the resulting number will overflow/underflow and wrap around generating a large error, or at best if it is handled (by hardware or software) it will be saturated to the maximal/minimal value of corresponding data type leading to truncation error.

Since most common DSP operations require multiply and accumulate operations, these kinds of representations where the magnitude of the number is directly mapped in the processor requires special handling to avoid truncation effects. In addition, exceeding the precision provided by the dynamic range of the data type typically introduces non-linear effects with large errors and sometimes breaks the algorithm.

Veton Kpuska

*Veton Kpuska*Range of Numbers of BF533 Fixed Point Representation

Unsigned Fixed Point Numbers16-bitsSign MagnitudeOnes ComplementTwos ComplementMIN VALUE20=0N/AN/AMAX VALUE216=65536N/AN/A32-bitsMIN VALUE20=0N/AN/AMAX VALUE232=4294967296N/AN/ASigned Fixed Point Numbers16-bitsSign MagnitudeOnes ComplementTwos ComplementMIN VALUE-216-1+1=-32767-216-1+1=-32767-216-1=-32768MAX VALUE+216-1-1=+32767+216-1-1=+32767+216-1-1=+3276732-bitsMIN VALUE-232-1+1 = -2147483647-232-1+1 = -2147483647-232-1 = -2147483648MAX VALUE+232-1-1 = +2147483647+232-1-1 = +2147483647+232-1-1 = +2147483647

Veton Kpuska

*Veton Kpuska*Fixed-Point Representations Based on Radix-Point One way to view possible fixed-point representations by a processor is based on the implied position of radix point. In the examples of integer fixed-point representations discussed previously, zero bits were used after the radix point. This implies the following representation depicting the integer formants in DSP:

Veton Kpuska

*Veton Kpuska*Alternative Fixed Point RepresentationsThere are alternative representations that have better properties then the common integer formats presented in previous sections. One such representation requires all numbers to be scaled in the range from [-1 to 1).

This is all fractional representation using fixed-point architecture. Note, this representation is not to be confused with floating point number representations which use different format and hardware to perform floating point operations.

Veton Kpuska

*Veton Kpuska*Alternative Fixed Point RepresentationsIn all fractional representation, allocated bits are used to cover fixed dynamic range between [-1 and 1).Clearly, larger the number of bits used for fractional numbers finer the representation (finer granularity). This stands in contrast to previous magnitude representation where the granularity is fixed and is equal to 1 constant difference of any two consecutive numbers. Imposing a constant range may potentially be considered a drawback of this fractional representation since it may require keeping track of the scaling factor used to translate the original range of values to fixed [-1, 1) range. On the other hand, this representation provides much better properties in terms of truncation error as well as overflow.

Veton Kpuska

*Veton Kpuska*Alternative Fixed Point RepresentationsTruncation error and overflow requires special consideration in fixed point integer representation discussed earlier. The 16-bit fractional representations do not require overflow handling. The only consideration is underflow (repetitive multiplication of numbers that are |x|

*Veton Kpuska*General Notation of Fractional RepresentationThe general notation of this fractional representation is:

Veton Kpuska

*Veton Kpuska*All Fractional Representation

Veton Kpuska

2-16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10

2-11

2-12

2-13

214

2-15

Bit Position

Position Value

RadixPoint

Unsigned Number Representation

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

-20

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10

2-11

2-12

2-13

2-14

2-15

Bit Position

Position Value

Sign Bit

RadixPoint

Signed Number Representation

*Veton Kpuska*Qp.q Fractional RepresentationPresented integer and fractional fixed-point representations depict two possible number representational schemes utilizing two extreme positions of implied radix-point. Since radix-point position defines the notation, a formal definition of such representational scheme is based precisely on it. Let N be the total number of bits used to represent a number. Also let p denote the number of bits to the left of the radix point specifying the integral portion of a number, and with q number of bits to the right of radix-point specifying the fractional portion of a number. Notation Qp.q specifies the format of the representation used as well as the position the implied radix-point as well as the precision of the representation. For example, the unsigned integer fixed-point format is expressed as Q16.0 since all bits lay to the left of radix-point. Consequently, signed 16-bit integer fixed-point format is denoted by Q15.0 with 1 bit used to represent the sign of a number. The all fractional representation uses Q0.16 and Q0.15 format for unsigned and signed numbers respectively.

Veton Kpuska

*Veton Kpuska*Qp.q Fractional RepresentationIn general, for unsigned numbers the relationship between total number of bits N and p, q is:For signed numbers the following relationship holds:

For unsigned numbers the following expression can be used:

Veton Kpuska

22

21

2-1

2-2

2-4

2-5

...

2-q-3

2-q-2

2-q-1

2-q

Position Value

Most Significant Bit

RadixPoint

2-3

Qp.q

20

2p

...

2p-1

Unsigned Fractional Representation of N=p+q bit Number

N

N-1

...

N-p+2

N-p+1

N-p

N-p-1

N-p-2

N-p-3

N-p-4

N-p-5

...

3

2

1

0

Bit Position

Position Value

Sign Bit

RadixPoint

Qp.q

22

Signed Fractional Representation of N=p+1+q bit Number

21

2-1

2-2

2-4

2-5

...

2-q-3

2-q-2

2-q-1

2-q

2-3

20

-2p

...

2p-1

N

N-1

...

N-p+2

N-p+1

N-p

N-p-1

N-p-2

N-p-3

3

2

1

0

Bit Position

N-p-4

N-p-5

...

*Veton Kpuska*Qp.q Fractional RepresentationIn light of introduced notation, a number represented by Qp.q of a binary signed format has a value that can be computed by the following expression:

For unsigned numbers the following expression can be used:

Veton Kpuska

*Veton Kpuska*Fixed-Point vs Floating Point DSPsFixed-Point DSPsNumbers represented as 16/32 bits:216=65,536 or 232=4,294,967,296 bit patterns.Unsigned Integer FormatStored Value: 16-bit: (0..65,536) or 32-bit: (0..4,294,967,296)Signed Integer FormatStored Value: 16-bit: (-32,768..32,767) or 32-bit: (-2,147,483,648..2,147,483647)Unsigned Fractional FormatStored Value: 16-bit: (0..1) 65,536 levels or 32-bit: (0..1) 4,294,967,296 levelsSigned Fractional FormatStored Value: 16-bit: (-1..1) 65,536 levels or 32-bit: (-1..1) 4,294,967,296 levels

Veton Kpuska

*Veton Kpuska*Blackfin Fixed-Point Representation ADI DSPs including Blackfin use Fractional Format Representation; 16-bit Example in 1.15 Format:-202-12-22-32-42-52-62-72-82-92-102-112-122-132-142-15MSBLSB

HEXBINARYDECIMAL7FFF0111111111111111+0.99996900010000000000000001+0.00003100000000000000000000+0.000000FFFF1111111111111111-0.00003180001000000000000000-1.000000

Veton Kpuska

Blackfin Family DSPs

Veton Kpuska

*Veton Kpuska*PerformanceBlackfin Processor Family Roadmap

Veton Kpuska

*Veton Kpuska*Summary of Blackfin Processor Family

FeatureADSP-BF535ADSP-BF531ADSP-BF532ADSP-BF533ADSP-BF561ADSP-BF536ADSP-BF537ADSP-BF534Max. Clock Speed (MHz)350400400750600400600500Memory (kBytes)3085284148328100132132External Memory (Bus)32-bit16-bit16-bit16-bit32-bit16-bit16-bit16-bitParallel Peripheral InterfaceNoYesYesYesYes(2)YesYesYes

Veton Kpuska

*Veton Kpuska*Summary of Blackfin Processor FamilyUART - Universal Asynchronous Receiver-Transmitter TWI - Twin-Wire InterfaceSPORT 100 Mbps Serial Port RTC- Real-Time Clock

FeatureADSP-BF535ADSP-BF531ADSP-BF532ADSP-BF533ADSP-BF561ADSP-BF536ADSP-BF537ADSP-BF534UARTs, TimersYesYesYesYesYesYesYesYesSPORTs, SPIYesYesYesYesYesYesYesYesProgrammable FlagsYesYesYesYesYesYesYesYesTWI- CompatibilityNoNoNoNoNoYesYesYesWatchdog TimerYesYesYesYesYesYesYesYesRTCYesYesYesYesNoYesYesYesCore Voltage RegulationNoYesYesYesYesYesYesYes

Veton Kpuska

*Veton Kpuska*Blackfin ADSP-BF531/2/3: Hand-Held and Portable ApplicationsKey FeaturesCode-compatible & pin-compatible family52Kbytes to 148Kbytes of on-board memoryParallel Peripheral InterfaceDynamic Power Management varies frequency and voltageInterfaces to External FLASH and SDRAM

Performance 400 MHz to 756 MHz16/32-bit CorePower @ 1.2V @ 1.0V 265mW, 600 MHz

*Veton Kpuska*Blackfin ADSP-BF536/537: For Embedded Network ConnectivityKey FeaturesEmbedded 10/100 Ethernet MACEmbedded CAN 8 timers & 48 GPIOsDynamic Power Management varies frequency and voltageInterfaces to External FLASH and SDRAMTestControlEmulationControlEvent ControllerWatchdogTimerMemory DMASystem Control BlocksPeripheral BlocksPLLProcessor CoreSystem Interface UnitL1ScratchPad4KB

SRAM SRAM/Cache 48KB 16KB 48KB 16KBUp to 64KB Inst.16-bitExternalMemory10/100 EthernetMAC/ 16 GPIOUp to 64KB DataRTC32 GPIOSPORT1, UART0-1, SPI, Timer0-7, PPI*SPORT0 / TWI *CANSRAM SRAM/Cache 16KB 16KB 32KB 32KB * Peripherals Available in Various Combinations; NOT all simultaneously

Performance 300 MHz to 600 MHz 16/32-bit CorePower @ 1.2V @ 1.0V 265mW, 600 MHz

*Veton Kpuska*ADSP-BF534: For Automotive and Industrial AppsKey FeaturesEmbedded CAN8 timers & 48 GPIOsIndustrial and Automotive temperature rangeDynamic Power Management varies frequency and voltageInterfaces to External FLASH and SDRAMTestControlEmulationControlEvent ControllerWatchdogTimerMemory DMASystem Control BlocksPeripheral BlocksPLLProcessor CoreSystem Interface UnitL1ScratchPad4KB

64KB Inst.16-bitExternalMemory16 GPIO64KB DataRTC32 GPIOSPORT1, UART0-1, SPI0, Timer0-7, PPI*SPORT0 / TWI / CAN*SRAM SRAM/Cache 32KB 32KBSRAM SRAM/Cache 48KB 16KB* Peripherals Available in Various Combinations; NOT all simultaneously

Performance 400 MHz to 500 MHz16/32-bit CorePower @ 1.2V @ 1.0V

*Veton Kpuska*Blackfin Dual Core ADSP-BF561: For Symmetric Multi Processing ApplicationsKey FeaturesHigh-performance dual-core328Kbytes of on-chip memoryThree independent DMA systemsDynamic Power Management varies frequency and voltageInterfaces to external FLASH and SDRAM

Performance 500 MHz to 600 MHz2 x 500-600 MHz16/32-bit CorePower @ 1.2V400mW, 500MHzAddress Range 768 MBytesOn-Chip SRAMOn-Chip L1 SRAMOn Chip L2 SRAM328 Kbytes100 KB per core (200 KB total)Shared 128 KbytesPeripherals 2 SPORTsUARTSPI12 Timers2 PPIsVoltage 0.85V to 1.32V (INT)2.25V to 3.6V (EXT)Temperature Range 0C to +70C Ambient -40C to +85C Ambient Package 256 MBGA297 PBGA Lead-free versions available

Veton Kpuska

*Veton Kpuska*Key FeaturesSupports USB full-speed devicePCI308Kbytes of on-board memoryDynamic Power Management varies frequency and voltageInterfaces to external FLASH and SDRAMBlackfin CoreUp to 350 MHzSystem Interface UnitL1L2High Speed I/O32-bit ExternalBusInterfaceEmulator& Test ControlEvent ControllersWatchdogTimerMemory DMASystem Control Blocks256 KB SRAMPCI v2.2 Master/SlaveRealTimeClockPLLSRAM / Cache16KBInst.32KBDataUSB v 1.1UART1UART0IrDAGPIO (16)Blackfin ADSP-BF535: For High-Performance PCI-Connected Appliances

Performance 200MHz to 350MHz 16/32-bit Core

Power @ 1.5 V @ 1.0 V600mW, 300 MHz100mW, 100 MHzAddress Range 768 MBytesOn-Chip SRAM308 KbytesInstruction / Data Cache48 KbytesOn-Chip RAM260 KbytesPeripherals PCI USB Device2 SPORTs2 SPIs & 2 UARTs3 32-bit TimersVoltage 1.0 V to 1.6 VTemperature Range 0C to +70C Ambient -40C to +85C Ambient Package 260 PBGA

Veton Kpuska

*Veton Kpuska*Summary of Blackfin BF531/2/3 DSPs176 LQFP176 Lead-free LQFP160 MiniBGA 160 Lead-free MiniBGA169 Lead-free PBGA52 KBytes400 MHz, 800 MMACsADSP-BF531Package OptionsOn-Chip RAMPerformance176 LQFP176 Lead-free LQFP160 MiniBGA 160 Lead-free MiniBGA169 Lead-free PBGA84 KBytes400 MHz, 800 MMACsADSP-BF532160 MiniBGA160 Lead-free MiniBGA 169 Lead-free PBGA148 KBytes500 / 600 / 756 MHz, 1000 / 1200 / 1512 MMACsADSP-BF533

Veton Kpuska

*Veton Kpuska*Flexible SMP (Symmetric MultiProcessors) Programming ModelsFirst Model (RISC/DSP) Core A runs OS, network and control-related tasksCore B runs signal processing

Second Model (Pure SMP)Signal processing split across each core, for example:Even frames to core A, odd frames to core BMulti-channel streams to cores A and BSequential M-stage processing on each buffere.g, steps 1.. N on core A & steps (N+1) .. M on core B

Veton Kpuska

*Veton Kpuska*ADDS-BF537-EZLITEKey Features ADSP-BF537 Blackfin Processor (600Mhz) 64 MB (32 M x 16) SDRAM 4 MB (2 M x 16) flash memory SMSC LAN83C185 10/100 PHY with RJ45 connector CAN TJA1041 transceiver with two modular connectors AD1871 96 kHz stereo DAC with 3.5 mm jack connector AD1854 96 kHz stereo ADC with 3.5 mm jack connector RS-232 UART line driver/receiver National Instruments Educational Laboratory Virtual Instrumentation Suite (NI ELVIS) interface Advanced USB-based debugger interface JTAG ICE 14-pin header Evaluation suite of VisualDSP++ development tools Flash utility for writing application boot code and data to flash Six general-purpose LEDs, four general purposepush-buttons Expansion Board Interface Cluster for evaluating and interfacing with the processors peripheral interfaces Discrete IDC Expansion ports for all processor peripherals

Veton Kpuska

*Veton Kpuska*ADDS-HPUSB-ICEHP USB-Based Emulator Key Features High speed USB 2.0 interface enablingdownload speeds of up to 1.5 MB/sec Background Telemetry Channel (BTC) support enabling nonintrusive data exchange at up to 2.0 MB/sec Support for all ADI JTAG processorsand DSPs Multiple processor and DSP I/O voltage support with automatic detection 1.8V, 2.5V, and 3.3V compliant and tolerant 5V tolerant and 3.3V compliant for 5V processors and DSPs JTAG clock operation up to 50 MHz 14-pin JTAG connector 3-meter USB cable for difficult-to-reach targets

Veton Kpuska

*Veton Kpuska*Linux Open Source Communitywww.blackfin.uclinux.org

Veton Kpuska

Blackfin Architecture

Veton Kpuska

*Veton Kpuska*Blackfin Architecture DetailsBlackfin Core DetailsRegistersALU, MAC, ShifterSequencer, Pipeline, Event Controller Blackfin MemoryMemory ArchitectureCachePeripheralsGeneral Peripherals:Parallel Peripheral Interface (PPI)Serial Ports (SPORTs)Serial Peripheral Interface (SPI)General Purpose TimersUniversal Asynchronous Receiver Transmitter (UART)Twin-Wire Interface (TWI)Real Time Clock (RTC)Watchdog Timer (WDT)Ethernet, CANDMAPeripherals listed in Blue are included in BF531/532/533 Family

Veton Kpuska

*Veton Kpuska*FeaturesIntegrated instruction set architectureSingle instruction set for signal processing and controlProgrammable interrupt levelsReal-time tasks get the highest priority levelMemory protection with an MMURegions of memory can be protected from accessNetworked peripherals in addition high speed connectivity to ADC, DAC and video peripherals Unified address space and byte addressableSupport for User and Supervisor modesRobust ALU including both signal processing functions as well as traditional MPC/MPU functions

Veton Kpuska

*Veton Kpuska*Blackfin ADSP-BF531/2/3 Architecture OverviewProcessor CoreRegistersALU, MAC, ShifterData Addressing ModesProgram SequencerEvent ControllerPeripheralsInstruction Set OverviewMemoryArchitectureCache

Veton Kpuska

*Veton Kpuska*ADSP-BF533 Processor

Veton Kpuska

*Veton Kpuska*Processor Core Architecture2 16-bit Multipliers2 40-bit Arithmetic Logic Units (ALU) 2 40-bit Accumulators 1 40-bit Shifter4 8-bit Video ALUs

Processor Unit Performs Operations on 8-bit,16-bit, &32-bit dataFrom Register File:8 32-bit Registers R0-R7

888816164040ACC1ACC0Barrel Shifter

Veton Kpuska

Register File

Veton Kpuska

*Veton Kpuska*RegistersBlackfin processors are register-intensive devicesAll computations are performed on data contained in registersAll peripherals are setup using registersMemory is accessed using pointers in address registersThere are two types of Blackfin processor registersCore registersMemory-Mapped Registers (MMRs)

Veton Kpuska

*Veton Kpuska*Blackfin Core RegistersCore registers are accessed directly by nameData Registers: R0-R7Accumulator Registers: A0, A1Pointer Registers: P0-P5, FP, SP,USPData Address GeneratorDAG Registers: I0-I3, M0-M3, B0-B3, L0-L3(Index, Modify, Base, Length registers for circular buffers)Cycle Counters: CYCLES, CYCLES2Program Sequencer: SEQSTATSystem Configuration Register: SYSCFGLoop Registers: LT[1:0], LB[1:0], LC[1:0]Interrupt Return Registers: RETI, RETX, RETN, RETE

Example (Assembly): R0 = SYSCFG; // Load data register with contents of SYSCFG register

Veton Kpuska

*Veton Kpuska*Blacfin Core RegistersLT0LB0Loop CounterLoop TopLoop Bottom

ASTATRETSRETIRETXRETNRETEArithmetic StatusSubroutine ReturnInterrupt ReturnException ReturnNMI ReturnEmulation ReturnLT1LB1System ConfigSequencer StatusSYSCFGSEQSTATLC0LC1Shaded registers only accessible in Supervisor mode

Veton Kpuska

*Veton Kpuska*Memory-Mapped Registers (MMR)A majority of registers are memory-mapped and must be accessed indirectlyCore MMRs are used to configure the core registersThey are listed in Appendix A of the HRM: 892485982bf533_hwr.pdfAll Core MMRs must be accessed with 32-bit reads or writesSystem MMRs are used to configure all other peripheralsThey are listed in Appendix B of the HRM: 892485982bf533_hwr.pdfSome System MMRs must be accessed with 32-bit reads or writes and others with 16-bit reads or writes (See the HRM for details)

MMR addresses are defined in header filesdefBF53x.h for assemblycdefBF53x.h for C/C++

MMRs can only be accessed in Supervisor mode

Veton Kpuska

*Veton Kpuska*Code ExamplesAssembly Example:P0.H = HI(SPI_RDBR); // load upper 16-bits of SPI // Receive Register address to // pointer registerP0.L = LO(SPI_RDBR); // load lower 16-bits of SPI // Receive Register address to // pointer registerR0 = W[P0] (z); // read 16-bit SPI Receive Register // (SPI_RDBR) into data register

C/C++ Example:short temp;// define variable to store // contentstemp = *pSPI_RDBR;// read 16-bit SPI Receive// Register contents into data // elementZero Extended

Veton Kpuska

Arithmetic Logic Units

Veton Kpuska

*Veton Kpuska*Data Arithmetic Logic Unit (ALU)Data Arithmetic UnitA140barrelshifterA04016168888LD0 32-bitsLD1 32-bitsSD 32-bitsR0R1R2R3R4R5R6R7R0.LR1.LR2.LR3.LR4.LR5.LR6.LR7.LR0.HR1.HR2.HR3.HR4.HR5.HR6.HR7.H

Veton Kpuska

*Veton Kpuska*Arithmetic Logic Unit (ALU)Two 40-bit ALUs operate on 16-bit, 32-bit, and 40-bit input data and output 16-bit, 32-bit, and 40-bit results.FunctionsFixed-point addition and subtractionAddition and subtraction of immediate valuesAccumulation and subtraction of multiplier resultsLogical AND, OR, NOT, XOR, bitwise XOR (LFSR), NegateFunctions: ABS, MAX, MIN, Round, division primitivesSupports conditional instructionsFour 8-bit video ALUs

Veton Kpuska

*Veton Kpuska*Arithmetic Logic Unit (ALU)40-bit ALU operations support the following combinations:Single 16-Bit OperationsDual 16-Bit OperationsQuad 16-Bit OperationsSingle 32-Bit OperationsDual 32-Bit Operations

Veton Kpuska

Multiply Accumulators (MAC)

Veton Kpuska

*Veton Kpuska*Multiply Accumulators (MAC)Data Arithmetic UnitA140barrelshifterA04016168888LD0 32-bitsLD1 32-bitsSD 32-bitsR0R1R2R3R4R5R6R7R0.LR1.LR2.LR3.LR4.LR5.LR6.LR7.LR0.HR1.HR2.HR3.HR4.HR5.HR6.HR7.H

Veton Kpuska

*Veton Kpuska*Multiply-Accumulate (MAC)Two identical MACsEach performs fixed-point multiplication and multiply-accumulate operations on 16-bit fixed-point input data and outputs 32-bit or 40-bit results.FunctionsMultiplicationMultiply-accumulate with additionMultiply-accumulate with subtractionDual versions of the aboveFeaturesSaturation of accumulator resultsOptional rounding of multiplier results

Veton Kpuska

Barrel Shifter

Veton Kpuska

*Veton Kpuska*Barrel ShifterData Arithmetic UnitA140barrelshifterA04016168888LD0 32-bitsLD1 32-bitsSD 32-bitsR0R1R2R3R4R5R6R7R0.LR1.LR2.LR3.LR4.LR5.LR6.LR7.LR0.HR1.HR2.HR3.HR4.HR5.HR6.HR7.H

Veton Kpuska

*Veton Kpuska*Barrel Shifter FunctionsPerforms bitwise shifting for 16-bit, 32-bit or 40-bit inputs and yields 16-bit, 32-bit, or 40-bit outputs.

Shift FunctionsArithmetic Shifts preserve the sign of the original number. The sign bit value back-fills the left-most bit positions vacated by the arithmetic right shift.Logical Shifts discard any bits shifted out of the register and back-fills vacated bits with zeros.

Veton Kpuska

*Veton Kpuska*Barrel Shifter FunctionsAdditional FunctionsRotate: Rotates a registered number through the CC bit a specified distance and direction.

Bit Operations Set, Clear, Toggle, Test

Field Extract and Deposit

Veton Kpuska

Program Sequencer

Veton Kpuska

*Veton Kpuska*Program SequencerControls all program flow

Contains a 10-stage instruction pipeline

Maintains in-program branchingSubroutinesJumpsInterrupts and Exceptions

Maintains loopsIncludes zero-overhead loop registersNo cost for wrapping from loop bottom to loop top

Veton Kpuska

*Veton Kpuska*Program Sequencer10-stage super-pipeline

Sequencer ensures that the pipeline is fully interlocked and that all the data hazards are hidden from the programmer

If executing an instruction that requires data to be fetched, the pipeline will stall until that data is availableSee EE-197 application note for a complete list of stalls and multi-cycle instructions: http://www.analog.com/ee-notes

Veton Kpuska

*Veton Kpuska*Program SequencerMost common numeric operations have no instruction latencyVisualDSP++ Pipeline Viewer highlights Stall and Kill conditions

Veton Kpuska

*Veton Kpuska*Sequencer Related Registers

Veton Kpuska

*Veton Kpuska*SEQSTAT RegisterThe Sequencer Status register (SEQSTAT) contains information about the current state of the sequencer as well as diagnostic information from the last event. SEQSTAT is a read-only register and is accessible only in Supervisor mode.

Veton Kpuska

*Veton Kpuska*Zero-Overhead Loop Registers (LC, LT, and LB)Two sets of zero-overhead loop registers implement loops, using hardware counters instead of software instructions to evaluate loop conditions. After evaluation, processing branches to a new target address. Both sets of registers include the Loop Counter (LC), Loop Top (LT), and Loop Bottom (LB) registers.

RegistersDescriptionFunctionLC0, LC1Loop CountersMaintains a count of the remaining iterations of the loopLT0, LT1Loop TopsHolds the address of the first instruction within a loopLB0, LB1Loop BottomsHolds the address of the last instruction of the loop

Veton Kpuska

*Veton Kpuska*SYSCFG RegisterThe System Configuration register (SYSCFG) controls the configuration of the processor. This register is accessible only from the Supervisor mode.

Veton Kpuska

Event Controller

Veton Kpuska

*Veton Kpuska*Event ControllerThe Event Controller manages 5 types of Events:Emulation (via JTAG interface)Reset (via SW or external pin)Non-Maskable Interrupt (NMI) - for events that require immediate processor attention (via SW, external pin, or Watchdog)Exception Synchronous to program flow. The exception is taken before the instruction is allowed to complete. Interrupts Asynchronous to program flow; caused by input pins, timers, and other peripherals:Hardware ErrorCore Timer9 General-Purpose Interrupts for servicing peripheralsCan be custom prioritized for optimal system performanceAll events can be serviced by Interrupt Service Routines (ISR)

Veton Kpuska

*Veton Kpuska*Event Controller - SummaryThe Event Controller of the processor manages five types of activities or events:EmulationResetNonmaskable interrupts (NMI)ExceptionsInterrupts (11)

Note the word event describes all five types of activities. The Event Controller manages fifteen different events in all: Emulation, Reset, NMI, Exception, and eleven Interrupts.

Veton Kpuska

*Veton Kpuska*Interrupts vs. ExceptionsINTERRUPTSHardware-generatedAsynchronous to program flowRequested by a peripheralSoftware-generatedSynchronous to program flowGenerated by RAISE instructionAll instructions preceding the interrupt in the pipeline are killed

EXCEPTIONSService ExceptionReturn address (RETE) is the address following the excepting instructionNever re-executedEXCPT instruction is in this categoryError Condition ExceptionReturn address (RETE) is the address of the excepting instructionExcepting instruction will be re-executed

The Blackfin is always in Supervisor Mode while executing Event Handler software can be in User Mode only while executing application tasks.

Veton Kpuska

*Veton Kpuska*Event ControllerAn interrupt is an event that changes normal processor instruction flow and is asynchronous to program flow.

In contrast, an exception is a software initiated event whose effects are synchronous to program flow.

The event system is nested and prioritized. Consequently, several service routines may be active at any time, and a low priority event may be pre-empted by one of higher priority.

Veton Kpuska

*Veton Kpuska*Processor Event ControllerProcessor Event Controller Consists of 2 stages:The Core Event Controller (CEC)System Interrupt Controller (SIC)

Conceptually:Interrupts from the peripherals arrive at SICSIC routes interrupts directly to general-purpose interrupts of the CEC.

Veton Kpuska

*Veton Kpuska*Core Event Controller (CEC)CEC supports 9 general-purpose interrupts: IVG15-7IVG15-14 2 lowest priority interrupts for software handlers.IRVG13-7 7 highest to support peripherals.Additional dedicated interrupt and exception events.

Veton Kpuska

*Veton Kpuska*System Interrupt Controller (SIC)SIC provides mapping and routing of events:From: Peripheral interrupt sourcesTo: Prioritized general-purpose interrupt inputs of the CEC.Processor default mapping can be altered by the user via Interrupt Assignment Register (IAR).

Veton Kpuska

*Veton Kpuska*BF533 System & Core Interrupt ControllersEvent SourceIVG #Core Event NameSystem Interrupt SourceIVG # 1 P r i o r i t yHighestLowest

Emulator0EMUReset1RSTNon Maskable Interrupt2NMIExceptions3EVSWReserved4-Hardware Error5IVHWCore Timer6IVTMRGeneral Purpose 77IVG7General Purpose 88IVG8General Purpose 99IVG9General Purpose 1010IVG10General Purpose 1111IVG11General Purpose 1212IVG12General Purpose 1313IVG13General Purpose 1414IVG14General Purpose 1515IVG15

PLL Wakeup interruptIVG7DMA error (generic)IVG7PPI error interruptIVG7SPORT0 error interruptIVG7SPORT1 error interruptIVG7SPI error interruptIVG7UART error interruptIVG7RTC interruptIVG8DMA 0 interrupt (PPI)IVG8DMA 1 interrupt (SPORT0 RX)IVG9DMA 2 interrupt (SPORT0 TX)IVG9DMA 3 interrupt (SPORT1 RX)IVG9DMA 4 interrupt (SPORT1 TX)IVG9DMA 5 interrupt (SPI)IVG10DMA 6 interrupt (UART RX)IVG10DMA 7 interrupt (UART TX)IVG10Timer0 interruptIVG11Timer1 interruptIVG11Timer2 interruptIVG11PF interrupt AIVG12PF interrupt BIVG12DMA 8/9 interrupt (MemDMA0)IVG13DMA 10/11 interrupt (MemDMA1)IVG13Watchdog Timer InterruptIVG13

Veton Kpuska

*Veton Kpuska*Interrupt Processing Block DiagramSIC_ISR logs the request and keeps track of system interrupts that are asserted but not yet serviced (that is, an interrupt service routine hasnt yet cleared the interrupt).SIC_IWR checks to see if it should wake up the core from an idled state based on this interrupt request.SIC_IMASK masks off or enables interrupts from peripherals at the system level. If Interrupt A is not masked, the request proceeds to Step 4.The SIC_IARx registers, which map the peripheral interrupts to a smaller set of general-purpose core interrupts (IVG7 IVG15), determine the core priority of Interrupt A.ILAT adds Interrupt A to its log of interrupts latched by the core but not yet actively being serviced. IMASK masks off or enables events of different core priorities. If the IVGx event corresponding to Interrupt A is not masked, the process proceeds to Step 7.The Event Vector Table (EVT) is accessed to look up the appropriate vector for Interrupt As interrupt service routine (ISR).When the event vector for Interrupt A has entered the core pipeline, the appropriate IPEND bit is set, which clears the respective ILAT bit. Thus, IPEND tracks all pending interrupts, as well as those being presently serviced.When the interrupt service routine (ISR) for Interrupt A has been executed, the RTI instruction clears the appropriate IPEND bit. However, the relevant SIC_ISR bit is not cleared unless the interrupt service routine clears the mechanism that generated Interrupt A, or if the process of servicing the interrupt clears this bit.It should be noted that emulation, reset, NMI, and exception events, as well as hardware error (IVHW) and core timer (IVTMR) interrupt requests, enter the interrupt processing chain at the ILAT level and are not affected by the system-level interrupt registers (SIC_IWR, SIC_ISR, SIC_IMASK, SIC_IARx).

Veton Kpuska

*Veton Kpuska*Interrupt Service RoutineISR address is stored in the Event Vector TableUsed as the next fetch address when the event occursProgram Counter (PC) address is saved to a registerRETI, RETX, RETN, RETE, based on eventAlways concludes with Return InstructionRTI, RTX, RTN, RTE (respectively)When executed, PC is loaded with address stored in RETI, RETX, RETN, or RETE to continue app code Optional nesting of higher-priority interrupts possibleSee app. note EE-192, which covers writing interrupt routines in C (http://www.analog.com/ee-notes)

Veton Kpuska

Blackfin Peripherals

Veton Kpuska

*Veton Kpuska*Blackfin Peripherals & Power ManagementCommon Peripherals (All Blackfins)SPI, UART, SPORT, WD, RTCPPI

BF534/BF536/BF537 PeripheralsTWI, CAN (Controller Area Network)

BF536/BF537 PeripheralEthernet

DMA and Handshake DMA

Power Manager

Veton Kpuska

*Veton Kpuska*Serial Communication PeripheralsSPI (Serial Peripheral Interface)High-Speed SPI port (up to SCLK/4, max 33.25 MHz)Master/Slave compatible with control of up to 7 slave-selectsSingle-Duplex DMA (Either TX or RX)Typically used to interface with serial EPROMS, CPUs, converters, and displays

Veton Kpuska

*Veton Kpuska*Serial Communication PeripheralsUART (Universal Asynchronous Receiver/Transmitter)PC-style UART port (baud rate up to SCLK/16, max 8.3125 MHz)Supports half-duplex IrDA SIR (9.6/115.2 Kbps rate)Autobaud detection support through the use of the TimersSeparate TX and RX DMA supportTypically used for maintenance port or interfacing with slow serial peripherals

Veton Kpuska

*Veton Kpuska*Serial Communication PeripheralsSPORTs (Synchronous Serial Ports)High Speed Serial Port (up to SCLK/2, max 66.5 MHz)Variable word length support (3 - 32 bits)I2S-CompatibleSeparate TX and RX DMA support128 Channels out of 1024-Channel Window for TDM supportPrimary and Secondary Data channelsTypically used for interfacing with CODECs and TDM data streams

Veton Kpuska

*Veton Kpuska*Real-Time Clock FeaturesUsed to implement real-time watch or life counterTime of day, alarm, stopwatch count-down, and elapsed time since last system resetUses four counters - Seconds, Minutes, Hours, DaysEquipped with two alarm featuresDaily and Day-And-TimeUses dedicated 32.768 kHz crystal to RTXI / RTXOCan be pre-scaled to 1 Hz to count in real-time secondsUses dedicated power supply pinsIndependent of any resetCan take processor out of all low-power states

Veton Kpuska

*Veton Kpuska*Parallel Peripheral Interface - PPIParallel Peripheral Interface Programmable bus width (from 8 16 bits in 1-bit steps)Bidirectional (half-duplex) parallel interfaceSynchronous Interface Interface is driven by an external clock (PPI_CLK)Up to 66MHz rate (SCLK/2)Asynchronous to SCLKIncludes three frame syncs to control the interface timingApplicationsDriving LCD InterfaceGeneral Purpose Interface to outside worldHigh speed data convertersVideo CODECs

Veton Kpuska

*Veton Kpuska*Two Wire Interface - TWIFully compliant to the Philips I2C bus protocolSee Philips I2C Bus Specification version 2.1 7-bit addressing100 Kb/s (normal mode) and 400Kb/s (fast mode) data ratesGeneral call address support

Supports Master and Slave operationSeparate receive and transmit FIFOs

SCCB (Serial Camera Control Bus) supportOnly in Master modeSlave mode cannot be used because the TWI controller always issues an Acknowledge in slave mode

Veton Kpuska

*Veton Kpuska*Controller Area Network (CAN)Adheres fully to CAN V2.0B standardSupports both standard (11-bit) and extended (29-bit) IdentifiersData Rates up to 1Mbit/second

32 Configurable Mailboxes 8 dedicated transmitters and 8 dedicated receivers16 configurable (transmit or receive)

Dedicated Acceptance Mask for each Mailbox

Data Filtering (first two bytes) can be used for Acceptance Filtering

CAN wakeup from Hibernation (lowest static power consumption) Mode

CAN Protocol StacksAutomotive: CAN drivers and protocol stacks through Vector CANtech Industrial: Leading third parties will provide a full Industrial suite for CANOpen, DeviceNet, etc.

Veton Kpuska

*Veton Kpuska*Ethernet MAC FeaturesADSP-BF536/537 Ethernet MAC has advanced features beyond IEEE 802.3: For improved performance: Automatic Checksum Computation for IP Header and Payload on RX Frames Programmable RX Data Alignment Mode for 32-bit Alignment Independent RX & TX DMA Channels with Delivery of Frame Status to Memory System Wakeup on Magic Packet for 4 User-Definable Wakeup Frame Filters

For lower overall system cost: No PHY XTAL required Buffered XTAL output from processor feeds PHY Connection to either MII or RMII PHY

ADSP-BF536/537 enhances throughput and dataflow via these features: Enhanced DMA channels allow for processor core independence Direction Control to exploit SDRAM physics Four SDRAM rows can be open at any given time

ADSP-BF536/537 overall networking bandwidth:Full 100Mbps wire speed on 1400-bit payload with an optimized networking stackUDP : ~44% processor core loadingTCP/IP: ~75% processor core loading

Veton Kpuska

DMA Support

Veton Kpuska

*Veton Kpuska*DMA SupportMultiple Independent DMA controllersDMA transfers can occur between:Internal memories and any of its DMA -capable peripherals, andDMA peripherals and external devices connected to external memory interfaces including SDRAM controller and Asynchronous Memory Controller.DMA capable peripherals:SPORTsSPI PortUART &PPI.Each individual DMA peripheral has at least one dedicated DMA channel.

Veton Kpuska

*Veton Kpuska*DMA Support (cont)DMA controller supports:1 - dimensional (1D) &2 - dimensional (2D) DMA transfers.2D DAM supports arbitrary: Row and Column sizes up to 64K x 64K elements.Row and Column Step Sizes up to +/- 32K elements.Column size < Row size Interleaved data.Useful in video applications.

Veton Kpuska

*Veton Kpuska*DMA Enhancements4 additional DMA channelsAll 12 peripheral DMA channels can be assigned to any of the peripherals

Provides MAC further control over the assigned DMA channelsCan reload DMA registers if incorrect checksum is detected

Two External Handshaking Memory DMA ControllersGood for asynchronous FIFOs or off-chip interface controllers between Blackfin memory and hardware buffers

Veton Kpuska

Dynamic Power Management

Veton Kpuska

*Veton Kpuska*Dynamic Power ManagementFull On Mode (Maximum Performance)Active Mode (Moderate Power Savings)Sleep Mode (High Power Savings)Deep Sleep Mode (Maximum Power Savings)Hibernate State

Veton Kpuska

*Veton Kpuska*Dynamic Power ManagementVariable FrequencyClock dividers (1x to 63x) enable low latency changes in system performanceVariable VoltageOn-Chip Voltage Regulator generates accurate voltage from 2.25 3.6V inputCore voltage programmable from 0.8V to 1.2V (50 mV increments)Maximum 40usec latency for PLL to relock (Frequency or Voltage changes)System Cost Reduction200 MHz, 0.8V, 90 mW

Veton Kpuska

Instruction Set Overview

Veton Kpuska

*Veton Kpuska*Instruction Set DescriptionFull-featured flexible multifunction instructions

Employs an algebraic-style syntax

Optimized to allow access to many of the processor core resources within a single instruction

Compiled C and C++ source code makes optimal use of instructions

Format designed for ease of coding and readability

Tuned to generate dense code (small memory size footprint)

Veton Kpuska

*Veton Kpuska*Blackfin Assembly Language FeaturesMulti-issue load/store modified-Harvard architecture supports Two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle.Unified 4G byte memory space All registers, I/O, and memory are mapped to a unified 4G byte memory spaceProviding a simplified programming modelMicrocontroller features:Arbitrary bit and bit-field manipulation, insertion, and extractionInteger operations on 8-, 16-, and 32-bit data-typesSeparate user and supervisor stack pointersCode density enhancementsIntermixing of 16- and 32-bit instructions (no mode switching, no code segregation)Frequently used instructions are encoded in 16 bits.

Veton Kpuska

*Veton Kpuska*Blackfin Code DensityInstruction Set Tuned for Compact CodeMulti-length Instructions16, 32-bit OpcodesLimited Multi-IssueCompact Call/Return

No Memory Alignment Restrictions for CodeTransparent Alignment HWBlackfin Supports 16 and 32-bit Memory Systems

Veton Kpuska

*Veton Kpuska*Blackfin Code Density FeaturesFree intermixing of 16/32-bit instructions - no mode switching, no code segregationFrequently used instructions encoded as 16-bits3-bit register fieldsConditional movesPush/Pop multiple registersThree operand instructionsSingle condition bit and evaluation

Veton Kpuska

*Veton Kpuska*Blackfin Dual Operational ModelData MovementLD, ST, 8,16,32 bitsUnsigned, Sign-extendRegister moves, P-D-DAG,Push, Pop, Push/PopmultCC to dreg, etc.

Addressing ModesAuto incr, Auto decr,Pre-decr store on SP,IndirectIndexed w/immed offsetPost-incr w/ nonunity strideByte addressable

Program ControlBRCC, UJUMP,Call, RETS, Loop SetupArithmetic+,-,*,/,>>>, Negate2 and 3 operand instructs

LogicalAND, OR, XOR, NOTBITtst,set,tgl,clr, CC ops

VideoSAA, Byteops: Residual calc,Spatial Interpolation, SpatialFilter

Cache ControlPrefetch, FlushA DSP with a RISC instruction set and a MMU, an Event Controller and a wide range of peripheralsSupervisor/user modesMemory managementWide range of peripheralsEvent control

Veton Kpuska

*Veton Kpuska*Blackfin Microcontroller FeaturesArbitrary bit and bit-field manipulation, insertion and extractionInteger operations on 8/16/32-byte data-typesMemory protection and separate user and supervisor stack pointersScratch SRAM for context switchingPopulation and leading digit countingByte addressing DAGsCompact Code Density

Veton Kpuska

Blackfin Memory

Veton Kpuska

*Veton Kpuska*Blackfin Memory OverviewBlackfinProcessorL1Instruction

L1Data A64 bit25MHzXTALEnetPHY25MHzEnet DataSDRAMExtBus

W/directionControl

No need for second XTALPLLVCO1:64X131MHzDMA2 core fetchesor 1 fetch and 1 store16 Max Bandwidth 266MB/sec32 Makes best use of SDRAM525 MHzLarge enough to run application codeCache available if operations from SDRAM are desiredProgrammable frequency and voltage controlRows are open in 4 SDRAM banksreducespage activation

Veton Kpuska

*Veton Kpuska*Blacfin Memory HierarchyAs processor speeds increase (300Mhz 1 GHz), it becomes increasingly difficult to have large memories running at full speed.The BF5xx uses a memory hierarchy with a primary goal of achieving memory performance similar to that of the fastest memory (i.e. L1) with an overall cost close to that of the least expensive memory (i.e. L2)L2 Memory

External Larger capacityHigher latencyL1 Memory

InternalSmallest capacitySingle cycle accessCORE

(Registers)L3 Memory

External Largest capacityHighest latencyOn-Chip

Veton Kpuska

*Veton Kpuska*Basics of Blackfin Memory ArchitectureCoreL1 Instruction MemoryL1 Data Memory

External MemoryL1 Data Memory

External MemoryExternal MemoryUnified L3External MemoryUnified L2Single cycle toaccess

10s of Kbytes

Several cycles to access 100s of Kbytes

Several system cycles to access

100s of Mbytes

>600MHz

>600MHz

>300MHz

*Veton Kpuska*Configuration of MemoryBest system performance can be achieved when executing code or fetching data out of L1 memoryTwo methods can be used to fill L1 memory Caching and Dynamic Downloading Blackfin Processor supports bothGeneral Purpose processors have typically used the caching method, as they often have large programs residing in external memory and determinism is not as important.DSPs have typically used dynamic downloading, as they need direct control over which code runs in the fastest memory.Blackfin processors allow the programmer to choose one or both methods to optimize system performance.

Veton Kpuska

*Veton Kpuska*What is Cache?In a hierarchical memory system, cache is the first level of memory reached once the address leaves the core (i.e L1)

If the instruction/data word (8, 16, 32, or 64 bits) that corresponds to the address is in the cache, there is a cache hit and the word is forwarded to the core from the cache.

If the word that corresponds to the address is not in the cache, there is a cache miss. This causes a fetch of a fixed size block (which contains the requested word) from the main memory.

Veton Kpuska

*Veton Kpuska*What is Cache?The Blackfin allows the user to specify which regions (i.e. pages) of main memory are cacheable and which are not through the use of CPLBs (more on this later).If a page is cacheable, the block (i.e. cache line containing 32 bytes) is stored in the cache after the requested word is forwarded to the coreIf a page is non-cacheable, the requested word is simply forwarded to the core

cplbsThe -cplbs (CPLBs are active) switch instructs the compiler to assume that all memory accesses will be validated by the Blackfin processors memory protection hardware. More information in VisualDSP++ 4.5 C/C++ Compiler and Library Manual for Blackfin Processors under C/C++ Compiler Common Switch Description.

Veton Kpuska

*Veton Kpuska*Cache Hits & MissesA cache hit occurs when the address for an instruction fetch request from the core matches a valid entry in the cache.A cache hit is determined by comparing the upper 18 bits, and bits 11 and 10 of the instruction fetch address tags of valid lines currently stored in a cache set.Only valid cache lines (i.e. cache lines with their valid bits set) are included in the address tag compare operation.

When a cache hit occurs, the target 64-bit instruction word is sent to the instruction alignment unit where it is stored in one of two 64-bit instruction buffers.When a cache miss occurs, the instruction memory unit generates a cache line-fill access to retrieve the missing cache line from external memory to the core.

Veton Kpuska

*Veton Kpuska*L1 Instruction Memory: 16kB Configurable Memory BankInstructionDCB (Data Cache Bus)- DMA4KBsub-bankEAB (External Access Bus) Cache Line Fill 4KBsub-bank4KBsub-bank4KBsub-bank16 KB cache 4-way set associative with arbitrary locking of ways and linesLRU (Least Recently Used) replacementNo DMA access16 KB SRAMFour 4KB single-ported sub-banksAllows simultaneous core and DMA accesses to different banks

Veton Kpuska

*Veton Kpuska*L1 Data Memory: 16kB Configurable Memory BankBlock is Multi-ported when:Accessing different sub-bankORAccessing one odd and one even access (Addr bit 2 different) within the same sub-bank.Data 1Data 04KBsub-bank4KBsub-bank4KBsub-bank4KBsub-bankWhen Used as CacheEach bank is 2-way set-associativeNo DMA accessAllows simultaneous dual DAG accessWhen Used as SRAMAllows simultaneous dual DAG and DMA accessEAB (External Access Bus) Cache Line Fill DCB (Data Cache Bus)- DMA

Veton Kpuska

Memory Architecture

Veton Kpuska

*Veton Kpuska*Memory ArchitectureMemory is addressed as a unified 4G space using 32-bit addresses.Internal MemoryExternal MemoryI/O Control Registers

Veton Kpuska

*Veton Kpuska*Hierarchical MemoryL1 Memory SystemHighest Performance Memory Available to the Core ProcessorOff-Chip MemoryAccessible via External Bus Interface Unit (EBIU)SDRAMFlash MemorySRAMUp to 132M Bytes.

Veton Kpuska

*Veton Kpuska*Internal Memory3 Blocks of on-chip memory:L1 Instruction Memory:SRAM &4-way set-associative cache.Access at full processor speed.L1 Data MemorySRAM &/or2-way set-associative cache.Access at full processor speedL1 scratchpad RAMOperating as L1 MemoryAccessible as Data SRAMCannot be configured as Cache Memory

Veton Kpuska

*Veton Kpuska*External MemoryOff-Chip MemoryAccessed via External Bus Interface Unit (EBIU)16-bit InterfaceSynchronous DRAM (SDRAM) Bank4 Banks of Asynchronous Memory Devices:Flash MemoryEPROMROMSRAMMemory-Mapped I/O

Veton Kpuska

*Veton Kpuska*External MemorySDRAM Controller (PC133 compliant) can be programmed to interface up to 128M Bytes of SDRAM.

Asynchronous Memory Controller:4 banks of 1M Byte Segment

Veton Kpuska

*Veton Kpuska*I/O Memory SpaceBlacfin processors do not define separate I/O space.Control Registers for On-Chip I/O Devices are mapped into Memory-Mapped Registers (MMRs) separated into two smaller blocks of total 4G Byte address space.Control MMRs (accessible only in Supervisor mode) for all Core functions, &Registers needed for Setup and Control of the on-chip peripherals outside of the Core.

Veton Kpuska

Data Addressing Modes

Veton Kpuska

*Veton Kpuska*Address RegistersOne set of 32-bit general-purpose Pointer registers P0-P5 (Pointer/Address registers), SP (Stack Pointer Register) and FP (Frame Pointer Register)One set of 32-bit DSP buffer addressing registersI0-I3 (Index Registers), B0-B3 (Base Registers), L0-L3 (Length Registers), andM0-M3 (Modify Registers)All addresses are byte addresses into a 4 GB address space

Veton Kpuska

*Veton Kpuska*Address RegistersI0I1I2I3L0L1L2L3B0B1B2B3M0M1M2M331031031031P0P1P2P3P4P5310FPSPUSPAddress RegistersSP points to supervisor stack in Supervisor mode and user stack in User modeUSP is accessible in supervisor mode only Allows access to user stack location while in Supervisor mode

Veton Kpuska

*Veton Kpuska*Addressing ModesRegister Indirect AddressingIndex Registers I0-I3 (32-bit and 16-bit accesses)Pointer Registers P0 P5 (32-bit, 16-bit, and 8-bit accesses)Stack and Frame Pointer Registers SP, FP (32-bit accesses)

Types of address pointer modifyModify/Post-ModifyLinear addressingCircular buffering / modulo addressing Enables automatic maintenance of pointers to stay within bounds of a circular bufferBit-Reversal (Modify only)Pre-Modify with update (using Stack Pointer)Pre-Modify without update

Veton Kpuska

*Veton Kpuska*Linear vs. Circular BufferingLinear Buffer AccessIndex (I0:3) registers hold the address sent out on the address bus.Length (L0:3) register set to 0, thus disabling circular buffering.Default for C compilerProvisions in compiler to allow circular buffersModify (M0:3) registers contain the value (positive or negative) that is added to the I registers at the end of each memory access.

Circular Buffer AccessBase (B0:3) registers contain the circular buffers start address.Length (L0:3) register set to length of circular buffer.Modify (M0:3) value must be less than or equal to the length of the circular buffer.Indexing wraps back to Base address when Index modification exceeds Base + Length

Veton Kpuska

*Veton Kpuska*Circular Buffering ExampleBase Address and Starting Index Address (B0 = 0; I0 = 0;)Buffer Length is 44 (L0 = 44;)There are 11 data elements and each data element is 4 bytesModify Value is 16 (M0 = 16;)4 elements * 4 bytes/elementAddress048C1014181C2024281st Access2nd Access5th Access4th Access3rd Access

Veton Kpuska

*Veton Kpuska*SummaryBasic Features of BF533 Processor were introducedComprehensive discussion of each Processor feature related to audio processing will be discussed in depth in this class.

Veton Kpuska

Digital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*PLL - Phase Locked Loop and Clock ControlArchitecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit ProcessorDigital Systems: Hardware Organization and DesignDigital Systems: Hardware Organization and Design*Architecture of a Respresentative 32 Bit Processor*Architecture of a Respresentative 32 Bit Processor