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Microprocessor

This book is a part of the course by Jaipur National University, Jaipur.This book contains the course content for Microprocessor.

JNU, JaipurFirst Edition 2013

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JNU makes reasonable endeavours to ensure content is current and accurate. JNU reserves the right to alter the content whenever the need arises, and to vary it at any time without prior notice.

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Index

ContentI. ...................................................................... II

List of FiguresII. .........................................................VI

List of TablesIII. .......................................................VIII

AbbreviationsIV. ........................................................IX

ApplicationV. ............................................................. 105

BibliographyVI. ........................................................ 114

Self Assessment AnswersVII. ................................... 116

Book at a Glance

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Contents

Chapter I ....................................................................................................................................................... 1Digital Logic Fundamentals ........................................................................................................................ 1Aim ................................................................................................................................................................ 1Objectives ...................................................................................................................................................... 1Learning outcome .......................................................................................................................................... 11.1 Introduction .............................................................................................................................................. 21.2 Number System ........................................................................................................................................ 2 1.2.1 Decimal Number System ......................................................................................................... 2 1.2.2 Binary Number System ............................................................................................................ 2 1.2.3 Octal Number System .............................................................................................................. 3 1.2.4 Hexadecimal Number System ................................................................................................. 41.3 Conversion ............................................................................................................................................... 4 1.3.1 Decimal Number to Binary Number ........................................................................................ 4 1.3.2 Decimal Number to Octal Number .......................................................................................... 5 1.3.3 Decimal Number to Hexadecimal Number ............................................................................. 5 1.3.4 Binary Number to Decimal Number ........................................................................................ 5 1.3.5 Binary Number to Octal Number ............................................................................................. 6 1.3.6 Binary Number to Hexadecimal Number ................................................................................ 6 1.3.7 Octal Number to Decimal Number .......................................................................................... 6 1.3.8 Octal Number to Binary Number ............................................................................................. 6 1.3.9 Octal Number to Hexadecimal Number .................................................................................. 7 1.3.10 Hexadecimal Number to Binary Number .............................................................................. 7 1.3.11 Hexadecimal Number to Octal Number................................................................................. 7 1.3.12 Hexadecimal Number to Decimal Number ........................................................................... 81.4 Binary Arithmetic ..................................................................................................................................... 8 1.4.1 Binary Addition and Subtraction ............................................................................................. 8 1.4.2 Binary Multiplication and Division ......................................................................................... 8 1.4.3 Floating Point Representation .................................................................................................. 9 1.4.4 Complements ......................................................................................................................... 101.5 Binary Coded Decimal Number Representation (BCD) .........................................................................111.6 Excess-3 Code ........................................................................................................................................ 121.7 Gray Code ............................................................................................................................................. 121.8 Basic Gates ............................................................................................................................................. 13 1.8.1 OR Gate (Logical Addition) .................................................................................................. 13 1.8.2 AND Gate (Logical Multiplication) ....................................................................................... 14 1.8.3 NOT Gate (Logical Inversion: Compliment) ......................................................................... 14 1.8.4 NOR Gate .............................................................................................................................. 15 1.8.5 NAND Gate ........................................................................................................................... 15 1.8.6 XOR Gate .............................................................................................................................. 161.9 Arithmetic Circuits ................................................................................................................................. 16 1.9.1 Half Adder .............................................................................................................................. 16 1.9.2 Full Adder .............................................................................................................................. 17 1.9.3 Half Subtractor ....................................................................................................................... 181.10 Flip Flops ............................................................................................................................................. 19 1.10.1 RS Flip Flop ......................................................................................................................... 19 1.10.2 D Flip Flop ........................................................................................................................... 20 1.10.3 JK Flip Flop ......................................................................................................................... 21 1.10.4 T Flip Flop ........................................................................................................................... 211.11 Multiplexer ........................................................................................................................................... 221.12 Demultiplexer ...................................................................................................................................... 221.13 Decoder ............................................................................................................................................. 231.14 Encoder ............................................................................................................................................. 23Summary .................................................................................................................................................... 25

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References ................................................................................................................................................... 25Recommended Reading ............................................................................................................................. 25Self Assessment ........................................................................................................................................... 26

Chapter II ................................................................................................................................................... 28Microprocessors ......................................................................................................................................... 28Aim .............................................................................................................................................................. 28Objectives .................................................................................................................................................... 28Learning outcome ........................................................................................................................................ 282.1 Introduction to Microprocessors ............................................................................................................ 292.2 Organisation of a Microprocessor-based System ................................................................................... 29 2.2.1 Microprocessor ...................................................................................................................... 30 2.2.2 Memory .................................................................................................................................. 30 2.2.3 Input/Output ........................................................................................................................... 31 2.2.4 System Bus ............................................................................................................................ 312.3 Microprocessor Architecture .................................................................................................................. 312.4 Functional Diagram of 8085 .................................................................................................................. 32 2.4.1 Timing and Control Unit ........................................................................................................ 32 2.4.2 ALU ....................................................................................................................................... 32 2.4.3 The 8085 Programmable Registers ........................................................................................ 33 2.4.4 Microprocessor-initiated Operations and 8085 Bus Organisation ......................................... 34 2.4.5 Externally Initiated Operations .............................................................................................. 352.5 Pin Out Diagram of 8085 ....................................................................................................................... 36 2.5.1 Power Supply and Frequency Signals ................................................................................... 37 2.5.2 Higher Order Address Bus (A8-A15) ....................................................................................... 38 2.5.3 Multiplexed Address/Data Bus (AD0-AD7) ........................................................................... 38 2.5.4 Control And Status Signals .................................................................................................... 38 2.5.5 Serial IO Signal ...................................................................................................................... 38 2.5.6 Externally or Peripheral Initiated Signals .............................................................................. 382.6 8085 Addressing Modes ......................................................................................................................... 40 2.6.1 Immediate Addressing ........................................................................................................... 40 2.6.2 Register Addressing ............................................................................................................... 40 2.6.3 Direct Addressing .................................................................................................................. 40 2.6.4 Indirect Addressing ................................................................................................................ 40 2.6.5 Implied Addressing ................................................................................................................ 402.7 8085 Instruction Set ............................................................................................................................... 41 2.7.1 Instruction Classification ....................................................................................................... 41 2.7.2 Instruction Format .................................................................................................................. 42 2.7.3 Instruction Word Size............................................................................................................. 43 2.7.4 Overview of the 8085 Instruction Set .................................................................................... 44Summary ..................................................................................................................................................... 55References ................................................................................................................................................... 55Recommended Reading ............................................................................................................................. 55Self Assessment ........................................................................................................................................... 56

Chapter III .................................................................................................................................................. 58Memory and Interfacing .......................................................................................................................... 58Aim .............................................................................................................................................................. 58Objectives .................................................................................................................................................... 58Learning outcome ........................................................................................................................................ 583.1 Memory .................................................................................................................................................. 593.2 I/O Devices ............................................................................................................................................ 593.3 I/O Addressing ....................................................................................................................................... 603.4 Interfacing of Input Device .................................................................................................................... 603.5 Interfacing Output Data ......................................................................................................................... 62

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3.6 Tri-state Buffer ....................................................................................................................................... 64Summary ..................................................................................................................................................... 65References ................................................................................................................................................... 65Recommended Reading ............................................................................................................................. 65Self Assessment ........................................................................................................................................... 66

Chapter IV .................................................................................................................................................. 68Programming Techniques ......................................................................................................................... 68Aim .............................................................................................................................................................. 68Objectives .................................................................................................................................................... 68Learning outcome ........................................................................................................................................ 684.1 Timing Diagram ..................................................................................................................................... 694.2 Processor Cycle ...................................................................................................................................... 694.3 Op-code Fetch ........................................................................................................................................ 714.4 Timing Diagram of Op-code Fetch ........................................................................................................ 734.5 Stack ...................................................................................................................................................... 75 4.5.1 The PUSH Instruction ............................................................................................................ 76 4.5.2 The POP Instruction ............................................................................................................... 76 4.5.3 Operation on Stack ................................................................................................................. 764.6 Subroutines ............................................................................................................................................ 77 4.6.1 The CALL Instruction ............................................................................................................ 77 4.6.2 The RET Instruction .............................................................................................................. 77 4.6.3 Subroutine Operation ............................................................................................................. 77 4.6.4 Passing Data to Subroutine .................................................................................................... 784.7 Counters ................................................................................................................................................. 784.8 Delays .................................................................................................................................................... 78Summary ..................................................................................................................................................... 79References ................................................................................................................................................... 79Recommended Reading ............................................................................................................................. 79Self Assessment ........................................................................................................................................... 80

Chapter V .................................................................................................................................................... 82Interfacing with 8085 Microprocessor ..................................................................................................... 82Aim .............................................................................................................................................................. 82Objectives .................................................................................................................................................... 82Learning outcome ........................................................................................................................................ 825.1 Introduction ............................................................................................................................................ 835.2 Interfacing Types .................................................................................................................................... 835.3 Programmable Peripheral Devices ......................................................................................................... 835.4 Types of Communication Interface ........................................................................................................ 845.5 8085 Interrupt System ............................................................................................................................ 845.6 8257 or 8237A (DMA Controller) ......................................................................................................... 845.7 The 8255A Programmable Peripheral Interface..................................................................................... 85 5.7.1 Block Diagram of the 8255A ................................................................................................. 865.8 The 8259A-Programmable Interrupt Controller ................................................................................... 87 5.8.1 Functional Block Diagram of 8259 ....................................................................................... 87 5.8.2 Interfacing 8259 with 8085 Microprocessor .......................................................................... 895.9 8251A (USART) .................................................................................................................................... 90 5.9.1 Functional Block Diagram of 8251A ..................................................................................... 91 5.9.2 Interfacing 8251A with 8085 Microprocessor ....................................................................... 925.10 8085 SID and SOD Line ...................................................................................................................... 935.11 16 Bit Processor 8086 .......................................................................................................................... 94 5.11.1 Pin Configuration of 8086 ................................................................................................... 94 5.11.2 Functional Block Diagram of 8086 ...................................................................................... 99 5.11.3 Min/Max Mode of 8086 ..................................................................................................... 100

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5.11.4 Addressing Modes of 8086 ................................................................................................ 100Summary ................................................................................................................................................... 102References ................................................................................................................................................. 102Recommended Reading ........................................................................................................................... 102Self Assessment ......................................................................................................................................... 103

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List of Figures

Fig. 1.1 OR Gate (a) truth table, (b) graphical symbol ................................................................................ 13Fig. 1.2 AND gate (a) truth table, (b) graphical symbol .............................................................................. 14Fig. 1.3 NOT gate (a) truth table, (b) graphical symbol .............................................................................. 14Fig. 1.4 NOR gate (a) truth table, (b) graphical symbol .............................................................................. 15Fig. 1.5 NAND gate (a) truth table, (b) graphical symbol ........................................................................... 15Fig. 1.6 XOR gate (a) truth table, (b) graphical symbol .............................................................................. 16Fig. 1.7 Half adder-block diagram ............................................................................................................... 16Fig. 1.8 Logic diagram for half adder .......................................................................................................... 17Fig. 1.9 Full adder circuit-block diagram .................................................................................................... 17Fig. 1.10 Logic diagram for full adder ......................................................................................................... 18Fig. 1.11 Logic diagram for half subtractor ................................................................................................. 18Fig. 1.12 RS flip flop ................................................................................................................................... 19Fig. 1.13 D flip flop (a) logic diagram, (b) characteristics table ................................................................. 20Fig. 1.14 JK flip flop a) graphical symbol, (b) characteristics table ............................................................ 21Fig. 1.15 T flip flop a) graphical symbol, (b) characteristics table .............................................................. 22Fig. 1.16 Multiplexer ................................................................................................................................... 22Fig. 1.17 Demultiplexer ............................................................................................................................... 23Fig. 1.18 Decoder ......................................................................................................................................... 23Fig. 1.19 Encoder ........................................................................................................................................ 24Fig. 2.1 A typical programmable devices ..................................................................................................... 29Fig. 2.2 Microprocessor-based systems with bus architecture..................................................................... 30Fig. 2.3 The 8085A microprocessor: functional block diagram .................................................................. 32Fig. 2.4 The 8085 programmable registers .................................................................................................. 33Fig. 2.5 Flag register of 8085 ....................................................................................................................... 33Fig. 2.6 The 8085 bus structure.................................................................................................................... 34Fig. 2.7 The 8085 microprocessor pin out and signals ................................................................................ 37Fig. 2.8 Hold operation ................................................................................................................................ 39Fig. 2.9 8085 addressing structure ............................................................................................................... 41Fig. 3.1 I/O interfacing ................................................................................................................................. 59Fig. 3.2 DIP switches ................................................................................................................................... 61Fig. 3.3 Pin and logic diagram of 74244 ...................................................................................................... 61Fig. 3.4 Interfacing of input device .............................................................................................................. 62Fig. 3.5 LED display .................................................................................................................................... 63Fig. 3.6 Internal diagram of latch IC 74273 ................................................................................................. 63Fig. 3.7 Principal of interfacing an output device ........................................................................................ 64Fig. 3.8 Tri-state buffer ................................................................................................................................ 64Fig. 3.9 Tri-state buffer circuit ..................................................................................................................... 64Fig. 4.1 Machine cycle showing clock periods ............................................................................................ 69Fig. 4.2 Processor cycle ............................................................................................................................... 70Fig. 4.3 Ideal wave shape relationship for FC, EC, MC, and IC. ................................................................ 70Fig. 4.4 Machine cycle including wait states ............................................................................................... 71Fig. 4.5 Fetch cycle ...................................................................................................................................... 71Fig. 4.6 Instruction fetch: reads 1st byte (op-code) in instruction register (IR) .......................................... 72Fig. 4.7 Instruction execute: reads 2nd byte from memory and adds to accumulator ................................... 72Fig. 4.8 Op-code fetch ................................................................................................................................. 73Fig. 4.9 Memory read timing diagram ......................................................................................................... 74Fig. 4.10 I/O read timing diagram ............................................................................................................... 74Fig. 4.11 Memory write timing diagram ...................................................................................................... 75Fig. 4.12 I/O write timing diagram .............................................................................................................. 75Fig. 4.13 PUSH instruction .......................................................................................................................... 76Fig. 4.14 POP instruction ............................................................................................................................. 76Fig. 4.15 CALL Instruction .......................................................................................................................... 77Fig. 4.16 RET Instruction ............................................................................................................................ 77

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Fig. 4.17 Counters ........................................................................................................................................ 78Fig. 5.1 An 8085 – 8257 interface ................................................................................................................ 85Fig. 5.2 8255A I/O Ports .............................................................................................................................. 86Fig. 5.3 Block diagram of the 8255A ........................................................................................................... 87Fig. 5.4 Functional block diagram of 8259 .................................................................................................. 88Fig. 5.5 Interfacing 8259 with 8085 microprocessor ................................................................................... 89Fig. 5.6 Functional block diagram of 8251A ............................................................................................... 91Fig. 5.7 Interfacing 8251A with 8085 microprocessor ................................................................................ 93Fig. 5.8 Pin configuration of 8086 ............................................................................................................... 94Fig. 5.9 Functional block diagram of 8086 .................................................................................................. 99

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List of Tables

Table 1.1 First 20 binary numbers ................................................................................................................. 3Table 1.2 First 20 octal numbers .................................................................................................................... 3Table 1.3 First 16 hexadecimal numbers ....................................................................................................... 4Table 1.4 First 8 octal numbers ...................................................................................................................... 6Table 1.5 Binary coded decimal ....................................................................................................................11Table 1.6 Excess – 3 codes .......................................................................................................................... 12Table 1.7 Gray codes .................................................................................................................................... 13Table 1.8 Addition table ............................................................................................................................... 16Table 1.9 Truth table for half adder ............................................................................................................. 17Table 1.10 Truth table for full adder ............................................................................................................ 18Table 1.11 Truth table for half substractor ................................................................................................... 18Table 1.12 Truth table for full substractor ................................................................................................... 19Table 1.13 Truth table for RS flip flop ......................................................................................................... 20Table 2.1 Status of signals S1 and S2 ............................................................................................................ 38Table 2.2 Data transfer operations ............................................................................................................... 41Table 3.1 Difference between I/O mapped I/O and memory mapped I/O ................................................... 60Table 4.1 Machine cycle status and control signals ..................................................................................... 69Table 5.1 I/O addresses of 8259 ................................................................................................................... 90Table 5.2 I/O addresses of 8251A ................................................................................................................ 93Table 5.3 Status of S4 and S3 ........................................................................................................................ 95Table 5.4 status of S0, S1 and S2 ................................................................................................................... 97Table 5.5 Status of QS1 and QS0 ................................................................................................................... 98

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Abbreviations

AC - Auxiliary Carry FlagALE - Address Latch EnableALU - Arithmetic Logic UnitBCD - Binary Coded DecimalBIU - Bus Interface UnitBSR - Bit Set/ResetCLK - ClockCPU - Central Processing UnitCRT - Cathode Ray TubeCY - Carry FlagDMA - Direct Memory AccessEU - Execution UnitHLDA - Hold AcknowledgeI/O - Input–OutputICW - Initialisation Command WordIMR - Interrupt Mask RegisterINTA - Interrupt AcknowledgeINTR - Interrupt RequestIRR - Interrupt Request Register ISR - In-Service Register LCD - Liquid Crystal DisplayLED - Light Emitting DiodesLIFO - Last In First Out MPU - Micro Processing UnitOCW - Operational Command WordPC - Program Counter PR - Priority Resolver RAM - Random Access MemoryRD - ReadROM - Read Only MemorySID - Serial Input DataSOD - Serial Output DataSP - Stack Pointer USART - Universal Synchronous/Asynchronous Receiver/Transmitter)WR - Write

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Chapter I

Digital Logic Fundamentals

Aim

The aim of this chapter is to:

explain the number system and binary arithmetic •

analyse different logic gates•

explore• various sequential circuits

Objectives

The objectives of this chapter are to:

explain the process of code conversion•

elucidate different logic gates with truth table and symbols•

inform about multiplexer, demultiplexer, encoder and decoders•

Learning outcome

At the end of this chapter, the students will be able to:

recall binary arithmetic and code conversion•

recognisevariouslogicgatesandflipflops•

understand multiplexer, demultiplexer, encoder and decoders•

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1.1 IntroductionOur present number system provides modern mathematicians and scientists with a great advantage over those of previous civilisations and is an important factor in our rapid advancement. Since hands are the most convenient tools nature has provided, human beings have always tended to use them in counting. So the decimal number system followed naturally from this usage.Asevensimplersystem,thebinarynumbersystemhasprovedthemostnaturalandefficientsystemforcomputeruse,however, and this chapter develops the number system along with other systems used by computer technology.

1.2 Number SystemA number system of base or radix r is a system having 'r' distinct symbols for 'r' digits. A number is represented by a string of these symbolic digits. To determine the quantity that the number represents, we multiply the number by anintegerpowerofrdependingontheplaceitislocatedandthenfindthesumofweighteddigits.Numbersystemis subdivided into following categories.

1.2.1 Decimal Number SystemDecimal system is the most commonly used number system. Our present system of numbers has 10 separate symbols namely 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9, which are called Arabic numerals.

The digit of a number system is a symbol, which represents an integral quantity.•Thebaseorradixofanumbersystemisdefinedasthenumberofdifferentdigits,whichcanoccurineach•position in the number system. The decimal system has a base or radix of 10.

Earlieritwassodifficultforthemathematicianstocalculatetheromannumeralsandtoperformarithmeticoperations,but now it is enough to learn only the 10 basic numerals and the positional notational system in order to count any desiredfigure.Aftermemorizingtheadditionandmultiplicationtablesandlearningafewsimplerules,wecanperform all arithmetic operations.

The actual meaning of 168 can be seen more clearly if we notice that it is spoken as 'one hundred and sixty eight'. Basically, the number is a contraction of 1*100+6*10+8. The important point is that the value of each digit is determined by its position. Written numbers are always contracted, however, and only the basic 10 numerals are used, regardless of the size of the integer written. The general rule for representing numbers in the decimal system by using positional notation is as follows:

This is expressed as , ….a0

Where, n is the number of digits to the left to the decimal point.

1.2.2 Binary Number SystemDigital computers use the binary number system, which has only two symbols: 0 and 1. The numbers in binary system are represented as combinations of these two symbols. The decimal system uses power of 10 and binary system uses power of 2.

The binary digit is also referred to as Bit (the acronym for Binary Digit). Where, 4 bits = nibble8 bits- byteA byte is the basic unit of data in computers.

The number 125 actually means 1* 102 + 2* 101 +5*100. In binary system, the same number (125) is represented as 1111101, which means,

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1*26+1*25+1*24+1*23+1*22+0*21+1*20

Thefollowingtablelistsfirst20binarynumbers

Decimal Binary Decimal Binary1 1 11 10112 10 12 11003 11 13 11014 100 14 11105 101 15 11116 110 16 100007 111 17 100018 1000 18 100109 1001 19 1001110 1010 20 10100

Table 1.1 First 20 binary numbers

To express the value of a binary number, therefore, an-1 2n-1 + an-2 2

n-2 + ……. + a0 is expressed as an-1, an-2 ….. a0 where ai is either 1 or 0 and n is the number of digits to the left of the binary (radix) point.

1.2.3 Octal Number SystemThe octal number system has a base or radix as 8: eight different symbols are used to represent numbers. These are commonly0,1,2,3,4,5,6,7.Tablegivenbelowshowsfirst20octalnumbersandtheirdecimalequivalents.

Decimal Octal Decimal Octal0 0 11 131 1 12 142 2 13 153 3 14 164 4 15 175 5 16 206 6 17 217 7 18 228 10 19 239 11 20 2410 12 21 25

Table 1.2 First 20 octal numbers

Octal number does not include the decimal digits 8 and 9. If any number includes decimal digits 8 and 9, then the number can not be an octal number.

To convert an octal number to a decimal number, we use the same sort of polynomial as it was used in the binary case, except that we now have a radix of 8 instead of 2. Therefore, 1413 in octal is,

= 1*83+4*82+1*81+3*80

= 512 + 256 + 8 + 3 =779

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1.2.4 Hexadecimal Number SystemWhen the machine is handling numbers in binary, but in groups of four digits, it is convenient to have a code for representing each of these sets of four digits. Since 16 possible different numbers can be represented, the digits 0 through9willnotsuffice.SothelettersA,B,C,D,EandFarealsoused.Hexadecimalnumbersarestringsofthesedigits. The numbers in decimal, binary and hexadecimal are shown in the table below.

Binary Hexadecimal Decimal0000 0 00001 1 10010 2 20011 3 30100 4 40101 5 50110 6 60111 7 71000 8 81001 9 91010 A 101011 B 111100 C 121101 D 131110 E 141111 F 15

Table 1.3 First 16 hexadecimal numbers

Thebaseorradixofanumbersystemisdefinedasthenumberofdifferentdigits,whichcanoccurineachpositionin the number system. The decimal number system has a base, or radix of 10. Thus, the system has 10 different digits (0, 1, 2… 9), any one of which may be used in each position in a number. History records the use of several other number systems.

1.3 ConversionFollowing are different ways of number conversion:

1.3.1 Decimal Number to Binary NumberTo convert a decimal number into binary number it requires successive division by 2, writing down each quotient and its remainder. The remainders are taken in the reverse order, which is the binary equivalent of the decimal number. For example, following is the conversion of decimal number 25 to its binary equivalent:

The binary equivalent for 2510=110012

To convert decimal fractions into equivalent binary fractions, repeatedly double the decimal fraction. The number (0 or 1) that appears on the left is written separately. The bits that are written in this manner are read from top to

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bottom with a decimal point on the left. For example, if the given number is 0.0625, conversion is done in the following manner.

The multiplication cannot be continued further, as the fractional part in the previous step has already become zero. Therefore, 0.062510= .00012.

1.3.2 Decimal Number to Octal NumberConversion from decimal to octal can be performed by repeatedly dividing the decimal number by 8 and using each remainder as a digit in the octal number being formed. For instance, to convert decimal number 200 to an octal representation, we divide it as follows:

Therefore, (200)10 = (310)8

1.3.3 Decimal Number to Hexadecimal NumberOne way to convert decimal to hexadecimal is the hex dabbles. The idea is to divide successively by 16, writing down the remainders. Here is a sample to convert decimal 2429 to hexadecimal:

Therefore, (2429)10= (9AF)16

1.3.4 Binary Number to Decimal NumberForconvertingthevalueofbinarynumberstodecimalequivalent,wehavetofinditsquantity,whichisfoundby multiplying a digit by its place value. The following example illustrates the conversion of binary numbers to decimal system.

Example 1101 = 1*23-1+0*2 3-2+1*23-3

= 1*22+0*21+1*20

= 4+0+1 = 5

Example 21001 = 1*24-1 +0*24-2+0*24-3 +1*24-4

= 1*23 + 0*22 + 0*21 + 1*20

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= 8+1= 9

1.3.5 Binary Number to Octal NumberThere is a simple trick for converting a binary number to an octal number. Simply group the binary digits into groups of 3, starting at the octal point, and read each set of three binary digits according to the following table.

Binary Octal000 0001 1010 2011 3100 4101 5110 6111 7

Table 1.4 First 8 octal numbers

Let us convert the binary number 011101 into octal. First, we break binary number into 3 digits (011 101). Then converting each group of three binary digits, we get 35 in octal. Therefore,011101 binary = 35 in octal

011101 = 011 101 = 3 5 = (35)8

1.3.6 Binary Number to Hexadecimal NumberTo convert binary to hexadecimal, we simply break a binary number into groups of four digits and convert each group of four digits according to the preceding code.

Example 1(10111011)2 = 1011 1011 = B B = (B B)16

Example 2(10000100)2 = 1000 0100 = 8 4 = (8 4)16

1.3.7 Octal Number to Decimal NumberTo convert an octal number to a decimal number, we use the same sort of polynomial as was used in the binary case, except that we now have a radix of 8 instead of 2. Therefore, 1213 in octal is = 1*83+2*82+1*81+3*80

= 512 + 128 + 8 + 3 = 651 1.3.8 Octal Number to Binary NumberThe conversion from octal number to binary number is easily accomplished. Each octal bit is converted to its three digit binary equivalent.

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Example 1

1.3.9 Octal Number to Hexadecimal NumberThe method of converting octal to hexadecimal number is to convert the given octal number to binary number and then arrange the binary digits into groups of 4 starting at the binary point.

Example 1Convert octal number 714.06 to hexadecimal(714.06)8 = (111 001 100 000 110)2 = 0001 1100 1100⋅0001 1000 = 1CC.18The hexadecimal equivalent of (714.06)8 is (1CC.18)16

1.3.10 Hexadecimal Number to Binary NumberTo convert a hexadecimal number to a binary number, convert each hexadecimal digit to its 4-bit equivalent using the code. For instance, here’s how 9AF is converted to binary.

As another example, C5E2

1.3.11 Hexadecimal Number to Octal NumberThe conversion of hexadecimal number to octal number involves two steps. First, convert the number from hexadecimal to binary numbers, and second, from binary to octal numbers, converting the hexadecimal into binary by writing 4 bits binary value for each bit in hexadecimal number and then arranging the binary digits into groups of three starting at the binary point.

Example 1Convert hexadecimal (1E.C) to octal (1E.C)16 = (0001 1110.1100)2 = (011 110 110) = 36.6The octal equivalent of (1E.C)16 is (36.6)8

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1.3.12 Hexadecimal Number to Decimal NumberThe conversion of hexadecimal to decimal is straightforward but time consuming. In Hexadecimal number system each digit position corresponds to a power of 16. The weights of the digit positions in a hexadecimal number are as follows: For instance, BB represents

BB = B*161 +B*160

= 11*16+11*1 = 176+11 = 187

1.4 Binary ArithmeticBinary arithmetic is as described below.

1.4.1 Binary Addition and SubtractionBinary addition is performed in the same manner as decimal addition. The complete table for binary addition is as follows:0+0=00+1=11+0=11+1=0 plus a carry over of 1

‘Carry over’ are performed in the same manner as in decimal arithmetic. Since 1 is the largest digit in the binary system, any sum greater than 1 requires that a digit be carried.

Examples

Subtraction is the inverse operation of addition. To subtract, it is necessary to establish a procedure for subtracting a larger digit from a smaller digit. The only case in which this occurs with binary numbers is when 1 is subtracted from 0. It is necessary to borrow 1 from the next column to the left. Following is the binary subtraction table:

0-0=01-0=10-1=1 with a borrow of 11-1=0

Examples

1.4.2 Binary Multiplication and DivisionThe table for binary multiplication is very short, with only four entries instead of the many for normal decimal multiplication.

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0*0=00*1=01*0=01*1=1

The following examples of binary multiplication illustrate the simplicity of each operation. It is only necessary to copy the multiplicand if the digit in the multiplier is 1 and to copy all 0’s if the digit in the multiplier is a 0.

The complete table for binary division is as follows:

0/1 = 01/1 = 1

Examples:

1.4.3 Floating Point RepresentationFloatingpointnumbersconsistsoftwoparts.Thefirstpartofthenumberisasignedfixed-pointnumber,whichistermedasmantissa,andthesecondpartspecifiesthedecimalorbinarypointpositionandistermedasanExponent.The mantissa can be an integer or a fraction.

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Example

Adecimal+12.34inatypicalfloating-pointnotations12.34=0.1234*102

12.34 = 1234 * 10-2

This number in any of the above form (if represented in BCD) requires 17 bits for mantissa (1 for sign and 4 each decimal digit as BCD) and 9 bits for exponent (1 for sign and 4 for each decimal digit as BCD). Exponent indicates thecorrectdecimallocation.Inthefirstcasewhereexponentis+2,indicatesthatactualpositionofthedecimalpoint is 2 places to the right of the assumed position, while exponent –2 indicates that the assumed position of the point is 2 places towards the left of assumed position. The assumption of the position of the point is normally the same in a computer resulting in a consistent computational environment.

Floating-pointnumbersareoftenrepresentedinnormalisedform.Afloating-pointnumberwhosemantissadoesnotcontainzeroasthemostsignificantdigitofthenumberisconsideredtobeinanormalisedform.Forexample,a BCD mantissa +370 which is 0 0011 0111 000 is in normalised form because these leading zero’s are not part of a 0 digit. On the other hand, a binary number 0 01100 is not in a normalised form. The normalised form of this number will be 0 1100.

Arithmeticoperations involvedwithfloatingpointnumbersaremorecomplex innature, takes longer time forexecutionandrequirecomplexhardware.Yetthefloatingpointrepresentationisamustasitisusefulinscientificcalculations.Realnumbersarenormallyrepresentedasfloatingpointnumbers.

1.4.4 Complements

1-complement•The 1-complement of a binary number is obtained just changing each 0 to 1 and each 1 to 0.

2-complement•The 2-complement of a binary number is obtained adding 1 to the 1-complement of this number:

2-complement= 1-complement+1

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There is a simple way to obtain the 2-complement:BeginningwiththeLSB,justwritedownbitsastheyaremovingtolefttillthefirst1,includingit.•Substitute the rest of bits by their 1-complement.•

1.5 Binary Coded Decimal Number Representation (BCD)In BCD number system, a group of binary bit is used to represent each of 10 decimal digits. For instances, an obvious and natural code is a simple weighted binary code as shown here.

Binary code Decimal Digit

0000 0

0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 8

1001 9

Table 1.5 Binary coded decimal

This is known as a binary coded decimal 8421 code or simply BCD. Notice that 4 binary bits are required for each decimal digit and each bit is assigned a weight; for instance the right most bit has a weight of 1, and the left most bit in each code group has a weight of 8. By adding the weights of the positions in which 1’s appear, the decimal digit represented by a code group may be derived. This is somewhat uneconomical since 24=16, and thus the 4 bits could actually represent 15 different values. For the decimal number 1246 to be represented, 16 bits are required: 0001 0010 0100 0110.

Example 1Convert decimal 4019 to BCD

The BCD equivalent of (4019)10 is 0100 0000 0001 1001

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Convert BCD number 0001 1001 0000 0111 to decimal

The decimal equivalent of BCD Number 0001 1001 0000 0111 is 1907. BCD numbers are useful wherever decimal information is transferred into a computer. The pocket calculator is one of the best examples for the application of BCD numbers. Other examples of BCD system are electronic counters, digital voltmeter and digital clocks.

1.6 Excess-3 CodeThe excess-3 code is a decimal code that has been used in older computers. This is an un-weighted code. Its binary code assignment is obtained from the corresponding BCD equivalent binary number after the addition of binary 3 (0011).

Decimal BCD Excess 3 code0 0000 00111 0001 01002 0010 01013 0011 01104 0100 01115 0101 10006 0110 10017 0111 10108 1000 10119 1001 110010 0001 0000 0100 001111 0001 0001 0100 0100

Table 1.6 Excess – 3 codes

1.7 Gray CodeDigital systems can process data only in discrete form. Many physical systems supply continuous output data. The data must be converted into digital form before they can be used by a digital computer. Continuous or analog informationisconvertedintodigitalformbymeansofananalogtodigitalconverter.ThereflectedbinaryorGraycode shown in the table below is sometimes used for the converted digital data.

The advantage of the Gray code over straight binary numbers is that the Gray code changes by only one bit as it sequences from one number to the next. In other words, the change from any number to the next in sequence is recognised by a change of only one bit from 0 to 1 and data is represented by the continuous change of a shaft position. The shaft is partitioned into segments with each segment assigned a number. If adjacent segments are made to correspond to adjacent Gray code numbers, ambiguity is reduced when the shaft position is in the line that separates any two segments.

Gray code counters are sometimes used to provide the timing sequences that control the operations in a digital system.AGraycodecounterisacounterwhoseflipflopgoesthroughasequenceofstates.Graycodecountersremove the ambiguity during the change from one state of the counter to the next because only one bit can change

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during the state transition.

Gray code Decimal Equivalent0000 00001 10011 20010 30110 40111 50101 60100 71100 81101 91111 101110 111010 121011 131001 141000 15

Table 1.7 Gray codes

1.8 Basic GatesDifferent types of gates are as described below.

1.8.1 OR Gate (Logical Addition)If A and B are the input logic variable and Y is the output variable, the truth table for a two input OR gate is given below.

A B Y0 0 00 1 11 0 11 1 1

(a)Truth table

(b) Graphical symbol

Fig. 1.1 OR Gate (a) truth table, (b) graphical symbol

The OR gate produces the inclusive – OR function, i.e., the output is 1, if A or B or both inputs are 1, otherwise

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the output is 0. In other words, in an 'n' input OR gate, if any input is a 1, the output is also 1. For an OR gate, the logical relationship of inputs and output can be written as,

Y=A+B+C+D+E+……

1.8.2 AND Gate (Logical Multiplication)The AND gate has one or more inputs and a single output. The output of an AND gate is equal to the multiplication of its inputs. The truth table for a two input AND gate is shown below. The output is 1 if both A and B are 1, otherwise the output is 0. In general, in an 'n' input AND gate, only if all the inputs are at logic 1, the output will be 1.

A B Y0 0 00 1 01 0 01 1 1

(a) Truth table


Fig. 1.2 AND gate (a) truth table, (b) graphical symbol

The input-output relationship can be written as:

Y=A.B.C.D.E.F…… OR Y=ABCDEF……

1.8.3 NOT Gate (Logical Inversion: Compliment)The complement function is nothing but inversion, 0 is changed to 1 and 1 to 0. The inverter circuit is also referred to as a NOT gate and it has a single input and single output.

A Y0 11 0

(a) Truth table


Fig. 1.3 NOT gate (a) truth table, (b) graphical symbol

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The NOT logic can be written as, Y=A’ or Y=A. The small circle in the output of the graphic symbol of an inverter designates a logic complement.

1.8.4 NOR GateFigure below shows the NOR gate block diagram symbol with inputs A, B, C and the output ABC. This shows the NOR gate’s output will be 1 only when all three inputs are 0. If any input represents 1, then the output of a NOR gate will be 0. The operation of the gate can be analysed using the equivalent block diagram circuit, which has an equivalent circuit showing an OR gate and an inverter. The inputs A, B, C are ORed by the OR gate, giving A+B+C, which is complemented by the inverter, yielding (A+B+C) =ABC.

A B Y0 0 10 1 01 0 01 1 0

(a) Truth table


Fig. 1.4 NOR gate (a) truth table, (b) graphical symbol

1.8.5 NAND GateThe inputs A, B and C and the output from the gate are written A+B+C. The output will be a 1 if A is a 0 or B is a 0 or C is a 0, and the output will be a 0 only if A, B and C are all 1’s. The operation of the gate can be analysed usingtheequivalentblockdiagramcircuitshowninthefigure,whichhasanANDgatefollowedbyaninverter.Ifthe inputs are A, B, and C then the output of the AND gate will be A.B.C and the complement of this is (A.B.C) =A+B+C.

A B Y0 0 00 1 11 0 11 1 0

(a) Truth table


Fig. 1.5 NAND gate (a) truth table, (b) graphical symbol

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1.8.6 XOR GateThe exclusive – OR (XOR), denoted by, is a logical operation that performs the following Boolean operation.

x⊕y = xy’+ x’y

It is equal to 1 if only x is equal to 1, or if only y is equal to 1, but not when both are equal to 1.

A B Y0 0 10 1 11 0 11 1 0

a) Truth table


Fig. 1.6 XOR gate (a) truth table, (b) graphical symbol

1.9 Arithmetic Circuits1.9.1 Half AdderA basic module used in binary arithmetic elements is the half-adder. The function of the half-adder is to add two binary digits, producing a sum according to the binary addition rules shown in the table 1.8

Input Sum of Bits0+0 00+1 11+0 11+1 0 With a carry of 1

Table 1.8 Addition table

The following shows a design for a half-adder, two inputs are designated as X and Y and two outputs, designated as S and C. The half-adder perform binary addition operation for two binary inputs as shown in the table. This is arithmetic addition, not logical or Boolean algebra addition.

Fig. 1.7 Half adder-block diagram

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Fig. 1.8 Logic diagram for half adder

Input Output

X Y S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Table 1.9 Truth table for half adder

In the half-adder diagram there are two inputs to the half-adder and two outputs. If either of the inputs is a 1 but not both, then the output on the S line will be a 1. If both inputs are 1, the output on the C line will be a 1. For all other states, there will be a 0 output on the carry line. These relationships may be written in Boolean form as follows.

S = XY’ + X’YC = XY

1.9.2 Full AdderThe adder circuit is capable of adding the content of two registers. It must include provision for handling carries as well as an addend and augends bits. So there must be three inputs to each stage of a multi digit adder, except the stagefortheleastsignificantbits.Oneforeachinputfromthenumbersbeingadded,oneforanycarrythatmighthave been generated or propagated by the previous stage.

There are three inputs to the full-adder, X and Y inputs from the respective digits of the registers to be added, the Ci input, which is for any carry generated by the previous stage. The two outputs are S, which is the output value for that stage of the addition, and C0, which produces the carry to be added into the next stage. The Boolean expressions for the input output relationships for each of the two outputs are as follows.

Fig. 1.9 Full adder circuit-block diagram

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Fig. 1.10 Logic diagram for full adder

Input OutputX Y Ci S C0

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 1 0 0 11 1 1 1 1

Table 1.10 Truth table for full adder

1.9.3 Half SubtractorA half subtractor subtracts a bit from another. The subtraction table (or truth table) of a half subtractor is shown below. The half subtractor has two input bits A and B, two output bits, a difference DIFF = (A-B) and a Borrow.

Input

Borrow DIFFA B

0 0 0 00 1 1 11 0 0 11 1 0 0

Table 1.11 Truth table for half substractorDifference =

Borrow =

Fig. 1.11 Logic diagram for half subtractor

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From the truth table shown in the table 1.10, it can be seen that DIFF = A-B and borrow which has been implemented on the logic circuit for half subtractor.

Full Subtractor1.9.4 A full subtractor subtracts with three bits (A-B-C). The third bit C is the borrow from previous stage. The truth table of a full subtractor is given below.

From the truth table of the full subtractor it can be seen that DIFF = (A B C) and borrow = A’B + BC + CA’. This logic has been implemented below.

Input

Borrow DIFFA B C

0 0 0 0 00 0 1 1 10 1 0 1 11 0 0 0 10 1 1 1 01 0 1 0 01 1 0 0 01 1 1 1 1

Table 1.12 Truth table for full substractor

1.10 Flip FlopsAflipflopisabistabledevice,thatis,itcanremaininoneofthetwostablestateswhicharedesignatedas'0'and'1' states. It is the fundamental logic circuit used for storing information in digital systems.

Differenttypesofshiftregistersandcountersaredesignedonlyusingflipflops,thatarebuildusingNORgatesorNANDgates.Aflipflophastwooutputs,oneofwhichisthecomplementoftheother.Theyarecallednormalandcomplementoutputs.Flipflopscanbecategorisedasfollows.

1.10.1 RS Flip FlopTheRSflipflopcanbeimplementedinmanyways.Onesuchimplementationisshowninfigurebelow.TherearetwoinputstotheRSflipflop.Theselinesareusedtocontroltheoutputoftheflipflop.Theworkingoftheflipflopcan be divided into different cases depending on both the inputs.

Case 1(S=0, R=0)When both inputs are 0, the NAND gates outputs A and B are logic. Hence, the outputs of C and D depend only on the feedback inputs (secondary inputs). The primary inputs, that is outputs of gates A and B are 'don’t care' now. In other words, the entire circuit behaves as a latch. Thus, the circuit will 'hold on' to its previous output. This state is called 'HOLD' state.

Fig.1.12RSflipflop

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FiguregivenaboveshowsanRSflipflopconstructedwithfourNANDgatesA,B,CandD.IthastwoinputsSand R and two outputs Q and Q’.

Case 2 (S=0, R=1)With S=0 and R=1, gate A will output logic 1 and gate B will output logic 0. The output of D, i.e., Q’ will be 1, making bothinputstogateCas0.Hence,Qwillbeina1state.Thisstateoftheflipflopisknownas'RESET'state.

Case 3 (S=1, R=1)This condition with S=1 and R=1 is prohibited. This is because when both S and R are equal to 1, gates A and B will output0’,whichwillforcebothQandQ’to1.Thisisagainsttheprincipleofoperationofaflipflop.Moreover,iftheinputsarenowchanged,thenextstateoftheflipflopisunpredictable.Thenextstateactuallydependsonwhichgate is faster to change its present state. This prohibited state is also called 'RACE' condition.

The table below presents the input output relations when S=1 and R=1.

Input OutputMode

S R Q(N+1)

0 0 Q(N) HOLD0 1 0 RESET1 0 1 SET1 1 * PROHIBITED

Table1.13TruthtableforRSflipflop

Case 4 (S=1, R=0)This is the just the reverse of case 2. On similar arguments, we can see that now Q=1 and Q’=0. This state of the flipflopisknownas'SET'state.

1.10.2 D Flip FlopIntheRSflipflop,theconditionR=1andS=1isforbidden.ThisstatecanbeavoidedbyconnectinganinverterbetweenSandRinputs.TheflipflopwiththismodifiedconnectioniscalledaDflipflop

(a) Logic diagram

CLK D Q DO X Q Q1 0 0 11 1 1 1

(b) Characteristics table

Fig.1.13Dflipflop(a)logicdiagram,(b)characteristicstable

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When the CLK input is 0, the D input does not affect the output. So when the clock is 0, D is treated as 'don’t care.' The value of D is prevented from reading the output until a clock pulse occurs. When the clock is high, both the AND gates are enabled and the value of D appears at Q. When the clock goes low, last value is retained by Q. This flipflopisalsocalledasa'delayflipflop'or'dataflipflop.'

1.10.3 JK Flip FlopJKflipflopisamodificationoftheSRflipflop,inthattheindeterminateconditionoftheSRtypeisdefinedintheJKtype.InputsJandKbehavelikeinputsSandRtosetandcleartheflipflop,respectively.WheninputsJandKarebothequalto1,aclocktransitionswitchestheoutputsoftheflipfloptotheircomplementstate.

TheJinputissimilartotheS(set)inputoftheSRflipflop,andtheKinputisequivalenttotheR(clear)input.Insteadoftheindeterminatecondition,theJKflipflophasacomplementconditionQ(t+1)=Q’(t),whenbothJandK are equal to 1.

(a) Graphical symbol

J K Q(t+1)0 0 Q(r) No change0 1 0 Clear to 01 0 1 Set to 11 1 Q’(t) Complement


Fig.1.14JKflipflopa)graphicalsymbol,(b)characteristicstable

1.10.4 T Flip FlopAnothertypeofflipflopisthetoggleflipflop.ThisflipflopisobtainedfromaJKflipflopwheninputsJandKareconnectedtoprovideasingleinputdesignatedbyT.TheTflipflopthereforehasonlytwoconditions.WhenT=0(J=K=0),aclocktransitiondoesnotchangethestateoftheflipflop.WhenT=1(J=K=1),aclocktransitioncomplementsthestateoftheflipflop.Theseconditionscanbeexpressedbyacharacteristicsequation.

(a) Graphical symbol

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T Q(t+1)

0 Q(t) No change

1 Q’(t) complement


Fig.1.15Tflipflopa)graphicalsymbol,(b)characteristicstable

1.11 MultiplexerA multiplexer is a combinational logic circuit, which has many inputs and only one output. Multiplexer means 'Many to one'. By applying a suitable control input, any data input can be sent to the output. Figure below shows a four data input multiplexer. D3, D2, D1 and D0 are data inputs. A and B are control inputs. Y is the output of the multiplexer. (Note that the multiplexer can be obtained by modifying a decoder circuit).

Fig. 1.16 Multiplexer

When control input AB = 00, Gate = 0 is enabled and hence Y = D0. Similarly if AB = 10, Gate 2 is enabled and hence Y= D2 and so on.

1.12 DemultiplexerA demultiplexer performs a function exactly opposite to that of a multiplexer. It has one data input and several output lines. Based on the value of the control input, one of the output lines will become active and will output the data input across it. Figure shows a 1 to 4 demultiplexer. D is the data input Y3, Y2, Y1 and Y0. i.e., Y0=D. Similarly when the control input AB=10, Y2=D.

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Fig. 1.17 Demultiplexer

1.13 DecoderA decoder has several output lines and control input lines. Based on the value of the control input (or select input), one of the output lines will become active. If there are four control input lines, then the decoder can have up to a maximum of sixteen (2 power 4) output lines. The decoder is generally used to select one among the many devices.It is widely used as address decoder in a computer system. (The outputs of a decoder can become the select inputs to the memory locations. In such case, the control inputs become the address of the memory location).Figure shows a simple decoder with two control inputs and four outputs.

Fig. 1.18 Decoder

When the control input AB = 00, the AND gate G0 is enabled and its output Y0 is high.Suppose AB = 10, then G2 is enabled and hence Y2 will be high.

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1.14 EncoderAn encoder is a digital circuit that generates the binary code corresponding to the input number. An octal-to-Binary encoder takes an octal input (in some symbolic form) and generates its binary equivalent as output. Similarly, a decimal-to-binary encoder takes a decimal input and generates an equivalent binary output. Figure shows an octal-to-binary encoder using OR gates. (A decimal-to-binary encoder has ten input lines and uses four OR gates at the output).

Fig. 1.19 Encoder

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Summary A number system of base or radix r is a system, which have r distinct symbols for r digits. A number is represented •by a string of these symbolic digits.Digital computers use the binary number system, which has only two symbols: 0 and 1,it uses power of 10 and •binary system uses powers of 2.The octal number system has a base or radix as 8: eight different symbols are used to represent numbers.•Binary addition is performed in the same manner as decimal addition.•Afloating-pointnumberwhosemantissadoesnotcontainzeroasthemostsignificantdigitofthenumberis•considered to be in a normalised form.Arithmeticoperationsinvolvedwithfloatingpointnumbersaremorecomplexinnature,takeslongertimefor•execution and require complex hardware.The 1-complement of a binary number is obtained just changing each 0 to 1 and each 1 to 0.•The 2-complement of a binary number is obtained adding 1 to the 1-complement of this number.•In BCD number system a group of binary bit is used to represent each of 10 decimal digits.•The advantage of the Gray code over straight binary numbers is that the Gray code changes by only one bit as •it sequences from one number to the next.The adder circuit is capable of adding the content of two registers.•Aflipflopisabistabledevice,thatis,itcanremaininoneofthetwostablestateswhicharedesignatedas'0'•and '1' states.A multiplexer is a combinational logic circuit, which has many inputs and only one output.•A demultiplexer performs a function exactly opposite to that of a multiplexer. It has one data input and several •output lines.A decoder has several output lines and control input lines.•An encoder is a digital circuit that generates the binary code corresponding to the input number.•

ReferencesE. Cortina. • Digital Electronics. Available at: <http://dpnc.unige.ch/tp/elect/doc/07-Digital.pdf> [Accessed on 23rd February, 2011].Unit 1: Number Systems and Binary Codes. Available at: <http://www.b-u.ac.in/sde_book/bca_fund.pdf>. •[Accessed on 23rd, February, 2011].

Recommended ReadingJr. Charles H. Roth, Larry L Kinney, 2009. • Fundamentals of Logic Design. CL-Engineering; 6th edition. p.758.Roger Tokheim. 1994. • Schaum’s Outline of Digital Principles. McGraw-Hill, 3rd edition. p.384.Seymour Lipschutz. 1982. • Schaum’s Outline of Essential Computer Mathematics. McGraw-Hill, 1st edition. p.256.

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Self Assessment

A_______________is a combinational logic circuit, which has many inputs and only one output.1. multiplexera. de multiplexerb. flipflopc. logic gated.

An __________ is a digital circuit that generates the binary code corresponding to the input number.2. decodera. encoderb. logic gatec. registerd.

The output of a/an ___________ gate is equal to the multiplication of its inputs.3. ORa. NANDb. ANDc. NORd.

_____________ counters are sometimes used to provide the timing sequences that control the operations in a 4. digital system.

Binary codea. BCD codeb. ASCII codec. Gray coded.

Digital systems can process data only in______________form.5. discretea. isolateb. continuousc. analogd.

State which of the following statement is true.6. Continuous or analog information is converted into digital form by means of an inverter.a. Continuous or analog information is converted into digital form by means of an analog to digital b. converter.Continuous or analog information is converted into digital form by means of an analog converter.c. Continuous or analog information is converted into digital form by means of a digital converter.d.

State which of the following statement is true.7. Realnumbersarenormallyrepresentedasnonfloatingpointnumbers.a. Real numbers are normally represented as decimal numbers.b. Realnumbersarenormallyrepresentedasfloatingpointnumbers.c. Real numbers are normally represented in indexed form.d.

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State which of the following statement is true.8. Flipflopisthefundamentallogiccircuitusedforstoringinformationinanalogsystems.a. Flipflopisthefundamentallogiccircuitusedforstoringinformationincontinuousform.b. Insulators is the fundamental logic circuit used for storing information in digital systems.c. Flipflopisthefundamentallogiccircuitusedforstoringinformationindigitalsystems.d.

Which of the following will be the 1-complement of 00101?9. 11010a. 01010b. 10101c. 00001d.

Which of the following is BCD equivalent of (3015)10. 10?1100 0000 0010 1010a. 0011 0000 0001 0101b. 1100 1111 1110 0110c. 0101 1110 0000 1111d.

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Chapter II

Microprocessors

Aim


explain the organisation of a microprocessor-based system•

illustrate the architecture of 8085 microprocessor•

elucidate• the instruction set of 8085 microprocessor

Objectives


examine different addressing modes of 8085 microprocessor•

classify • instructionssetintofivefunctionalcategories

illustrate the pin out diagram of 8085 • microprocessor

Learning outcome


understand the architecture of 8085 microprocessor•

explain different addressing modes of 8085 microprocessor•

recall the instruction set of 8085 microprocessor•

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2.1 Introduction to MicroprocessorsA microprocessor is a multipurpose, programmable logic device that reads binary instructions from a storage device called memory. It accepts binary data as input and processes data according to those instructions and provides results as output. A typical programmable machine can be represented with three components: microprocessor, memory and I/O as shown below.

Fig. 2.1 A typical programmable devices

Microprocessor, memory and I/O devices work together or interact with each other to perform a given task; thus they compromise a system. The physical components of this system are called hardware. A set of instructions written for the microprocessor to perform a task is called a program. A group of programs is called software.

A microprocessor as a programmable device•The microprocessor is programmable device that can be instructed to perform given tasks within its capacity. The engineers designing a microprocessor determine a set of tasks the microprocessor should perform and design the necessary logic circuits and provide the user with a list of instructions the processor will understand.

For example, an instruction for adding two numbers may look like a group of eight binary digits such as 1000 0000.These instructions are simply a pattern of 0s and 1s.The user (programmer) selects instructions from the list and determines the sequence of execution for a given task. These instructions are entered or stored in storage, called memory, which can be read by the microprocessor.

Memory•Memoryislikethepagesofanotebook,withspaceforafixednumberofbinarynumbersoneachline.However,these pages are generally made of semiconductor material. Typically, each line is an 8-bit register that can store 8 binary bits, and several of these registers are arranged in a sequence called memory. These registers are always grouped together in powers of two.

I/O devices•The user can enter instructions and data into memory through devices such as keyboard or simple switches, these devices are called input devices. The microprocessor reads the instruction from the memory and processes the data according to those instructions. The results can be displayed by a device such as seven segment LEDS or printed by a printer. These devices are called output devices.

2.2 Organisation of a Microprocessor-based SystemFigurebelowshowsasimplifiedbutformalstructureofamicroprocessor-basedsystem.Sinceamicrocomputer•isoneamongmanymicroprocessor-basedsystems,itwillhavethesamestructureasshowninthefigure.It includes three components: microprocessor, I/O (input/output) and memory (read/write memory and read-only •memory). These components are organised around a common communication path called a bus.The entire group of components is also referred to as a system or a microcomputer system, and the components •

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themselves are referred to as sub-systems. The microprocessor is one component of the microcomputer. On the other hand, the microcomputer is a complete •computer similar to any other computer, except that CPU function of the microcomputer is performed by the microprocessor.Similarly, the term peripheral is used for input/output devices. •

Fig. 2.2 Microprocessor-based systems with bus architecture(Source: http://www.b-u.ac.in/sde_book/bca_fund.pdf)

2.2.1 MicroprocessorThe microprocessor is a semiconductor device consisting of electronic logic circuits manufactured by using either a large-scale integration (LSI) or very-large-scale integration (VLSI) technique. It is capable of performing various computing functions and making decisions to change the sequence of program execution, in large computers, a CPU implemented on one or more circuit boards performs these computing functions. The microprocessor is in many ways similar to the CPU. The microprocessor can be divided into three segments for the sake clarity, as shown in fig2.2.

Arithmetic/logic unit (ALU):• This is the area of the microprocessor where various computing functions are performed on data. The ALU unit performs arithmetic operations as addition and subtraction, and logic operations such as AND, OR and exclusive OR. Results are stored either in register or in memory.Register array: • This area of the microprocessor consists of various registers. These registers are primarily used to store data temporarily during his execution of a program. Some of the registers are accessible to the user through instructions.Control unit:• The control unit provides the necessary timing and control signals to all the operations in the microcomputers.Itcontrolstheflowofdatabetweenthemicroprocessorandmemoryandperipherals.

2.2.2 MemoryMemory stores such binary information as instructions and data, and provides that information to the microprocessor whenever necessary. To execute programs the microprocessor reads instructions and data from memory and performs the computing operations in its ALU section. Results are either transferred to the output section for displayer stored inmemoryforlateruse.Thememoryblockshowninfigurehastwosections:

The ROM• is used to store programs that do not need alterations. The monitor program of a single board

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microcomputer is generally stored in the ROM. This program interprets the information entered through a keyboard and provides equivalent binary digits of the microprocessor. Programs stored in the ROM can only be read; they cannot be altered.Read/Write Memory (R/WM)• , popularly known as Random-Access memory (RAM) or user memory. It is used to store user programs and data. In signal board microcomputers, the monitor program monitors the Hex keys and stores those instructions and data in the R/W memory. The information stored in this memory can be easily read and altered.

2.2.3 Input/OutputThe third component of a microprocessor-based system is I/O (input/output); it communicates with the outside world. I/O includes two types of devices; input and output; these I/O devices are also known as peripherals.

The input devices• like keyboard, switches and an analog- t o – digital (A/ D) converters transfer binary information (data instructions) from the outside world to the microprocessor. The output devices• transfer data from the microprocessor to the outside world. They include devices such as Light Emitting Diodes (LED’s), a Cathode Ray Tube (CRT) or video screen, a printer, X-Y plotter, a magnetic tape, and digital – to analog (D/A) converter. Typically, single board microcomputers and microprocessor – based products include LED’s, seven – segment LED’s, and alphanumeric LED displays as output devices. Microcomputers (PCs) are generally equipped with the output devices such as video screen and a printer.

2.2.4 System BusThe system bus is a communication path between the microprocessor and peripherals; it is nothing but a group of wires to carry bits. In fact, there are several buses in the system. All peripherals share the same bus; however, the microprocessor communicates with only one peripheral at a time. The timing is provided by the control unit of the microprocessor.

2.3 Microprocessor ArchitectureThemicroprocessorisaprogrammablelogicdevice,designedwithregisters,flipflopsandtimingelements.It has a set of instructions, designed internally to manipulate data and communicate with peripherals. This process of data manipulation and communication is determined by the logic design of the microprocessor.

The microprocessor can be programmed to perform functions on given data by selecting necessary instructions from its set. These instructions are given to the micro-processor by writing them into its memory. Writing instructions and data is done through an input device such as a keyboard. The microprocessor reads or transfers one instruction at a time, matches it with its instruction set, and performs the data manipulation indicated by the instruction. The result can be stored in memory or sent to such output devices as LEDs or a CRT terminal.

In addition, the microprocessor can respond to external signals. It can be interrupted, reset, or asked to wait to synchronisewithlowerperipherals.Allthevariousfunctionsperformedbythemicroprocessorcanbeclassifiedinthree general categories:

microprocessor-initiated operations•internal data operations•peripherals (or external initiated) operations•

To perform these functions, the microprocessor requires a group of logic circuits and a set of signals called control signals. However, early processors did not have the necessary circuitry on one chip; the complete units were made upofmorethanonechip.Therefore,thetermMicroProcessingUnit(MPU)isdefinedhereasagroupofdevicesthat can perform these functions with the necessary set of control signals. This term is similar to Central Processing Unit (CPU). However, later microprocessors include most of the necessary circuitry to perform these operations on a single chip. Therefore, the terms MPU and microprocessor are often used synonymously.

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2.4 Functional Diagram of 8085

Fig. 2.3 The 8085A microprocessor: functional block diagram(Source: http://www.b-u.ac.in/sde_book/bca_fund.pdf)

The internal architecture of the 8085 includes the ALU (Arithmetic Logic Unit), timing and control unit, instruction register and decoder, register array, interrupt control and serial I/O control. Let us have a look on each of the blocks.

2.4.1 Timing and Control UnitThis unit synchronises all the microprocessor operations with the clock and generates the control signals necessary for communication between the microprocessor and the peripherals. The control signals are similar to a sync pulse in an oscilloscope. The RD and WR signals are sync pulses indicating the availability of data on the data bus.

2.4.2 ALUThe ALU performs the actual numerical and logic operation such as ‘add’, ‘subtract’, ‘AND’, ‘OR’, etc. It uses data from the memory and the accumulator to perform various arithmetic functions. The results are stored in the accumulator.

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2.4.3 The 8085 Programmable Registers

Fig. 2.4 The 8085 programmable registers(Source: http://www.b-u.ac.in/sde_book/bca_fund.pdf)

Registers: • The8085have6general-purposeregisterstoperformthefirstoperations:store8-bitdata.TheseregistersareidentifiedbyB,C,D,E,HandLasshowninfigure.Theycanbecombinedasregisterpairs-BC,DE, and HL- to perform 16 bit operations. These registers are programmable, meaning that a programmer can use them to load and transfer data from the registers by using instructions. For example, MOVE B, C – copies the data from C to B.

Accumulator: • Accumulator is an 8 –bit register. This register is used to store 8-bit data and in performing Arithmetic and Logical Operations. The result of operations is stored in accumulator (A).

Flags: • TheALUincludesfiveflipflops,whicharesetorresetafteranoperationaccordingtodataconditionsoftheresultintheaccumulatorandotherregisters.Theseflipflopsarecalledflags.Letusseeeachflagindetail

S-signflag: � AfterexecutionofanarithmeticorlogicoperationifbitD7oftheresultis1,thesignflagisset.Thisflagisusedwithsignednumbers.InagivenbyteifD7is1,thenumberwillbeviewedasanegative number; if it is zero the number will be considered positive. In arithmetic operations with signed numbers, the bit D7 is reserved for indicating the sign and the remaining seven bits are used to represent the magnitude of a number.Z-Zeroflag: � ThezeroflagissetiftheALUoperationsresultsin0,andtheflagisresetiftheresultisnot0.Thisflagismodifiedbytheresultsintheaccumulatoraswellasintheotherregisters.AC-AuxiliaryCarryflag: � In an arithmetic operation, when a carry is generated by digit D3 and passed on todigitD4,theACflagisset.ItisusedonlyinternallyforBCDoperations.P-Parityflag: � Afteranarithmeticorlogicoperation,iftheresultasanevennumberof1stheflagisset.Ifitasanoddnumberof1stheflagisreset.CY-Carryflag: � Ifanarithmeticoperationresultsinacarrythecarryflagissetotherwiseitisreset.Thecarryflagalsoservesasaborrowflagforsubtraction.

Thebitpositionsreservedfortheseflagsintheflagintheflagregisterareasfollows.

Fig. 2.5 Flag register of 8085

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Program Counter (PC): • This 16 – bit register deals with fourth operations, sequence in the execution of instructions. This register is the memory pointer. Memory location has 16 bit addresses.Stack Pointer (SP): • The stack pointer is also a 16-bit register used as a memory pointer. It points to the memory locationinR/Wmemorycalledthestack.Thebeginningofthestackisdefinedbyloadingthe16bitaddressin the stack pointer (register).Register Array: • Two additional registers, called temporary registers W and Z, are included in the register array. These registers are used to hold 8-bit data during the execution of some instructions. However, because they are used internally, they are not available to the programmer.Instruction Register and Decoder: • The instruction register and the decoder are part of the ALU. When an instruction is fetched from memory, it is loaded in the instruction register. The decoder decodes the instruction and establishes the sequence of events to follow. The instruction register is not programmable and cannot be accessed through any instruction.

2.4.4 Microprocessor-initiated Operations and 8085 Bus OrganisationThe MPU performs primarily four operations:

Memory READ: reads data (or instructions) from memory•Memory WRITE: reads data (or instructions) into memory•I/O READ: accepts data from input devices•I/O WRITE: send data to output devices•

Fig. 2.6 The 8085 bus structure(Source: http://www.b-u.ac.in/sde_book/bca_fund.pdf)

To communicate with a peripheral (or memory location), the MPU needs to perform the following stepsStep 1: identify the peripheral or the memory location (with its address)Step 2: transfer dataStep 3: Provide timing or synchronisation signals

The 8085 MPU performs these functions using three sets of communication lines called buses: the address bus, the data bus and the control bus. These buses together form one group called the system bus.

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Address Bus:• Theaddressbus isagroupof16 linesgenerally identifiedasA0 to A15. The address bus is unidirectional;bitsflowinonedirectionfromtheMPUtoperipheraldevices.TheMPUusestoperformthefirstfunction:identifyingtheperipheraloramemorylocation.Data Bus:• Databusisgroupofeightlinesusedfordataflow.Theselinesarebidirectional.TheMPUusesthedata bus to perform the second function: Transferring data.Control Bus:• It comprised of various single lines that carries synchronisation signals. It performs the third function: providing time signals.

2.4.5 Externally Initiated OperationsExternal devices can initiate the following operations, for which individual pins on the microprocessor chip are assigned:

Reset• : When the reset is activated, all internal operations are suspended and the program counter is cleared (it holds 0000H). The program execution can again begin at the zero memory address.Interrupt• : The microprocessor can be interrupted from the normal execution of instructions and asked to execute some other instructions called service e routine. The microprocessor resumes its operation after completing the service routine.Ready• : The 8085 has a pin called READY. If the signal at this READY pin low, the microprocessor enters into a wait state.Hold• : When the HOLD pin is activated by an external signal, the microprocessor relinquishes control of the buses and allows the external peripheral to use them.

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2.5 Pin Out Diagram of 8085

(a) The 8085 microprocessor pin out diagram

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(b) The 8085 microprocessor signalsFig. 2.7 The 8085 microprocessor pin out and signals(Source: http://www.b-u.ac.in/sde_book/bca_fund.pdf)

Let us see the explanations for the pins.

2.5.1 Power Supply and Frequency SignalsVcc+5V volt supply

VssGround reference

X1, X2 (Input)A crystal (or RC, LC network) is connected at these two pins. The frequency is internally divided by two; therefore, to operate a system at 3 MHz, the crystal should have a frequency of 6 MHz.CLK (OUT) – Clock OutputThis signal can be used as the system clock for other devices.

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2.5.2 Higher Order Address Bus (A8-A15)These8pinsareusedtocarrythehigherorderaddress.Themostsignificant8bitsofthememoryaddressorthe8bits of I/O address is carried by theses lines. These lines are tri-stated during Hold and Halt modes.

2.5.3 Multiplexed Address/Data Bus (AD0-AD7)Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 addresses) appear on the bus during the firstclockcycleofamachinestate.Itthenbecomesthedatabusduringthesecondandthirdclockcycles.Theselines are tri-stated during Hold and Halt modes.

2.5.4 Control And Status SignalsThis group of signals includes two control signals (RD and WR), three status signals, (IO/M, s1 and s0) to identify the nature of the operation, and one special signal (ALE) to indicate the beginning of the operation. These signals are as follows.

ALE• – Address Latch Enable: This is a positive going pulse generated every time the 8085 begins an operation (machine cycle); it indicates that the bits on AD7 – AD0 are address bits. This signal is used primarily to latch the low-order address from the multiplexed bus and generate a separate set of eight address lines, AD7 – A0.RD – Read:• This is a Read Control Signal (active low). This signal indicates that the selected I/O or memory device is to be read and data are available on the data bus.WR• – Write: This is a Write control signal (active low). This signal indicates that the data on the data bus are to be written into a selected memory or I/O location.IO/M:• This is a status signal used to differentiate between I/O and memory operations. When it is high, it indicates an I/O operation; when it is low, it indicates a memory operation. This signal is combined with RD (Read) and WR Write) to generate I/O and memory control signals.S1 and S0:• These are the two data bus status signals. The four combinations of these signals give the information of what the microprocessor is doing or the encoded status of the bus cycle.

S1 S0 Operation0 0 Halt0 1 Write1 0 Read1 1 Fetch

Table 2.1 Status of signals S1 and S2

2.5.5 Serial IO Signal

SID (input): • It is serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.SOD (output): • Itisserialoutputdataline.TheoutputSODissetorresetasspecifiedbytheSIMinstruction.

2.5.6 Externally or Peripheral Initiated Signals

Trap (Input)This is a non-mask able interrupt and has the highest priority

RST 5.5, RST 6.5, RST 7.5: RESTART interrupt (inputs)These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically

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inserted.RST 7.5 − Highest PriorityRST 6.5 − Is level triggered RST 5.5 − Lowest Priority and is edge triggered

The priority of these interrupts is ordered as shown above. These interrupts have a higher priority than the INTR.

INTR (interrupt request) (input)It is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted.

INTA (interrupt acknowledge) (output)It is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port.

READY (input)If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle.

HOLD (Hold request) (input)HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue. The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.

HLDA (Hold acknowledge) (output)Hold acknowledge indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low.

Fig. 2.8 Hold operation(Source: http://webphysics.davidson.edu/faculty/dmb/py310/8085.pdf)

RESET IN (input)ResetsetstheProgramCountertozeroandresetstheInterruptEnableandHLDAflipflops.Noneoftheotherflagsor registers (except the instruction register) are affected. The CPU is held in the reset condition as long as Reset is applied.

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RESET OUT (output)Indicates CPU is being reset. It can be used as a system RESET. The signal is synchronised to the processor clock.

2.6 8085 Addressing ModesThe8085hasfiveaddressingmodes:

Immediate addressing•Register addressing•Direct addressing•Indirect addressing•Implied addressing •

2.6.1 Immediate AddressingInanimmediateaddressingmode,8or16bitdatacanbespecifiedasapartofinstruction.

ExampleMVI A, 30H − Moves 8 bit immediate data (30H) into accumulatorLXI SP, 2700H − Moves 16 bit immediate data (2700H) into SP

2.6.2 Register AddressingTheregisteraddressingmodespecifiesthesourceoperand,destinationoperand,orbothtobecontainedin8085registers. This results in faster execution, since it is not necessary to access memory locations for operands.

ExampleMOV A, B − Moves the content of register B into accumulatorADD C − Adds the content of register C into the contents of accumulator and stores result in the accumulator

2.6.3 Direct AddressingThedirectaddressingmodespecifiesthe16bitaddressoftheoperandwithintheinstructionitself.Thesecondandthe bytes of instruction contain this 16 bit address.

ExampleLDA 2000H − Loads the 8 bit content of memory location 2000H into the accumulatorSHLD 2000H − Stores the HL register pair into two consecutive memory locations. Lower byte i.e., the contents of L register into memory location 3000H and the higher byte i.e., the contents of H register into memory location 3001H.

2.6.4 Indirect AddressingThis mode contains a register pair which stores the address of data.

ExampleLDAX B− Loads the accumulator with the contents of a memory location addressed by B, C register pair.

2.6.5 Implied AddressingInimpliedaddressingmode,theoperandisnotspecifiedexplicitlyintheinstruction.ExampleCMA − Complements the contents of accumulatorRAL − Rotates the contents of accumulator left through carry

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2.7 8085 Instruction SetThe 8085 use a 16-bit address. Since 8085 is a byte- addressable machine, it follows that it can directly address 65,536(216)distinctmemorylocations.Theaddressingstructureofthe8085processorisshowninthefigure.

Fig. 2.9 8085 addressing structure(Source: http://www.b-u.ac.in/sde_book/bca_fund.pdf)

2.7.1InstructionClassificationAninstructionisabinarypatterndesignedinsideamicroprocessortoperformaspecificfunction.Theentiregroupof instructions, called the instruction set, determines what functions the microprocessor can perform.

Theinstructionscanbeclassifiedintofivefunctionalcategories,whichareasdecribedbelow:

Data transfer operationsThis group of instructions copies data from a location called a source to another location, called destination, without modifying the contents of the source. The term data transfer is used for this copying function. The various types of data transfer are listed below

Types Examples

Between registers Copy the contents of the register B intoregister D

Specificdatabytetoaregisteroramemorylocation Load register B with the data byte 23H

Between a memory location and a register From a memory location 3000H to register B

Between an I/O device and the accumulator From an input keyboard to the accumulator

Table 2.2 Data transfer operations

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Arithmetic operationsThese instructions perform arithmetic operations such as addition, subtraction, increment and decrement.

Addition: • Any 8-bit number, or the contents of a register, or the contents of a memory location can be added to the contents of the accumulator and sum is stored in the accumulator.Subtraction: • Any 8-bit number, or the contents of a register, or the contents of a memory location can be added to the contents of the accumulator and sum is stored in the accumulator.Increment/decrement:• The 8-bit contents of a register or a memory location can be incremented or decremented.

Logical operationsThese instructions perform various logical operations with the contents of the accumulator.

AND, OR, EXCLUSIVE –OR:• Any 8-bit number, or the contents of a register, or the contents of a memory location can be logically AND ed, Or ed, or Exclusive – OR ed with the contents of the accumulator and sum is stored in the accumulator.Rotate:• Each bit in the accumulator can be shifted either left or right to the next position.Compare: • Any 8-bit number, or the contents of a register, or the contents of a memory location can be compared for equality, greater than, or less than, with the contents of the accumulator.Complement: • The contents of the accumulator can be complemented; all 0s are replaced by 1s and all 1s are replaced by 0s.

Branching operationsThis group of instructions alters the sequence of program execution either conditionally or unconditionally.

JUMP:• Conditional jumps are an important aspect of the decision making process in programming. These instructions test foracertaincondition(e.g.,ZeroorCarryflag)andalter theprogramsequencewhen thecondition is met. In addition, the instruction set includes an instruction called unconditional jump.CALL, RETURN AND RESTART: • These instructions change the sequence of a program either by calling a subroutine or returning from a subroutine or returning from a subroutine. The conditional Call and Return instructionsalsocantestconditionalflags.Machine control operations:• These instructions control machine functions such as Halt, Interrupt or do nothing.

Machine control operationsThese instructions control machine functions such as Halt, Interrupt, or do nothing. The microprocessor operations related to data manipulation can be summarised in four functions:

copying data•performing arithmetic operations•performing logical operations•testing for a given condition and alerting the program sequence•

Some important aspects of the instruction set are as noted below:In data transfer, the contents of the source are not destroyed; only the contents of the destination are changed. •Thedatacopyinstructionsdonotaffecttheflags.Arithmetic and Logical operations are performed with the contents of the accumulator, and the results are stored •intheaccumulator(withsomeexpectations).Theflagsareaffectedaccordingtotheresults.Any register including the memory can be used for increment and decrement.•A program sequence can be changed either conditionally or by testing for a given data condition.•

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2.7.2 Instruction FormatAninstructionisacommandtothemicroprocessortoperformagiventaskonaspecifieddata.Eachinstructionhastwo parts: one is task to be performed, called the operation code (opcode), and the second is the data to be operated on,calledtheoperand.Theoperand(ordata)canbespecifiedinvariousways.Itmayinclude8-bit(or16-bit)data,an internal register, a memory location, or 8-bit (or 16-bit) address. In some instructions, the operand is implicit.

2.7.3 Instruction Word SizeThe8085instructionsetisclassifiedintothefollowingthreegroupsaccordingtowordsize:

One-byte instructions•A 1-byte instruction includes the opcode and operand in the same byte. Operand(s) are internal register and are coded into the instruction.For example

Instruction Task Op-code Operand Code Hex code

MOV C,A Copy the contents of the accumulator inthe register C MOV C,A 01001111 4FH

ADD B Add the contents of register B to thecontents of the accumulator ADD B 1000 0000 80H

CMA Compliment each bit in the accumulator CMA 0010 1111 2FH

These instructions are 1-byte instructions performing three different tasks. Inthefirstinstruction,bothoperandregistersarespecified.•Inthesecondinstruction,theoperandBisspecifiedandtheaccumulatorisassumed.•Similarly, in the third instruction, the accumulator is assumed to be the implicit operand. These instructions are •stored in 8-bit binary format in memory; each requires one memory location.

Two-byte instructions•Inatwo-byteinstruction,thefirstbytespecifiestheoperationcodeandthesecondbytespecifiestheoperand.Sourceoperand is a data byte immediately following the opcode.

For example

Instruction Task Op-code Operand Binarycode Hex code

MVI A, Data Load an 8-bit data byte in the accumulator. MVI A, Data

0011 11003EData

First Byte

Second Byte

DATA

Assume that the data byte is 32H. The assembly language instruction is written as:

Mnemonics Hex codeMVI A, 32 H 3E 32H

The instruction would require two memory locations to store in the memory.

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Three-Byte Instructions•Inathree-byteinstruction,thefirstbytespecifiestheopcode,andthefollowingtwobytesspecifythe16-bitaddress.Note that the second byte is the low-order address and the third byte is the high-order address.Opcode + data byte + data byte

Task Opcode Operand Binary code Hex code

Transfer theProgram sequence to the memory location 2085H.

JMP 2085 H1100 00111000 01010010 0000

C38520

First ByteSecond ByteThird Byte

This instruction would require three memory locations to store in memory.

2.7.4 Overview of the 8085 Instruction SetThe following notations are used in the description of the instructions:

R = 8085 8-bit register (A, B, C, D, E, H, L)•M = Memory register (location)•Rs = Register source (A, B, C, D, E, H, L)•Rd = Register destination•Rp = Register pair (BC, DE, HL, SP)•

Data transfer instructions

Sr.no. Instruction Opcode Operand Description

1 MOV

Rd, RsM, RsRd, M

Move or copy from source to destinationThis instruction copies the contents of the source register into the destination register; the contents of the source register are not altered. If one of the operands is a memory location, its locationisspecifiedbythecontentsoftheHLregisters.

Example: MOV B, C or MOV B, M2 MVI

Rd, dataM, data

Move immediate 8-bit dataThe 8-bit data is stored in the destination register or data memory. If the operand is a memory location, its location is specifiedbythecontentsoftheHLregisters.

Example: MVI B, 57H or MVI M, 57H

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3 LDA

16-bit address

Load accumulatorThecontentsofamemorylocation,specifiedbya16-bitaddress in the operand, are copied to the accumulator.The contents of the source are not altered.

Example: LDA 2034H4 LDAX.

B/D Reg pair

Load accumulator indirectThe contents of the designated register pair point to a memory location. This instruction copies the contents of that memory location into the accumulator. The contents of either the register pair or the memory location are not altered.

Example: LDAX B5 LXI

Reg. pair, 16-bit data

Load register pair immediateThe instruction loads 16-bit data in the register pair designated in the operand.

Example: LXI H, 2034H or LXI H, XYZ6 LHLD

16-bit address

Load H and L registers directThe instruction copies the contents of the memory location pointed out by the 16-bit address into register L and copies the contents of the next memory location into register H. The contents of source memory locations are not altered.

Example: LHLD 2040H7 STA

16-bit address

Store accumulator direct The contents of the accumulator are copiedintothememorylocationspecifiedbytheoperand.Thisisa3-byteinstruction,thesecondbytespecifiesthelow-orderaddressandthethirdbytespecifiesthehigh-orderaddress.

Example: STA 4350H8 STAX

Reg. pair

Store accumulator indirectThe contents of the accumulator are copied into the memory locationspecifiedbythecontentsoftheoperand(registerpair). The contents of the accumulator are not altered.

Example: STAX B9 SHLD

16-bit ad-dress

Store H and L registers directThe contents of register L are stored into the memory location specifiedbythe16-bitaddressintheoperandandthecontentsof H register are stored into the next memory location by in-crementing the operand. The contents of registers HL are not altered.Thisisa3-byteinstruction,thesecondbytespecifiesthelow-orderaddressandthethirdbytespecifiesthehigh-order address.

Example: SHLD 2470H

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10 XCHG

None

Exchange H and L with D and EThe contents of register H are exchanged with the contents of register D, and the contents of register L are exchanged with the contents of register E.

Example: XCHG11 SPHL

None

Copy H and L registers to the stack pointerThe instruction loads the contents of the H and L registers into the stack pointer register, the contents of the H register pro-vide the high-order address and the contents of the L register provide the low-order address. The contents of the H and L registers are not altered.

Example: SPHL12 XTHL

None

Exchange H and L with top of stackThe contents of the L register are exchanged with the stack location pointed out by the contents of the stack pointer register. The contents of the H register are exchanged with the next stack location (SP+1); however, the contents of the stack pointer register are not altered.

Example: XTHL13 PUSH

Reg. pair

Push register pair onto stackThe contents of the register pair designated in the operand are copied onto the stack in the following sequence. The stack pointer register is decremented and the contents of the high order register (B, D, H, A) are copied into that location. The stack pointer register is decremented again and the contents of thelow-orderregister(C,E,L,flags)arecopiedtothatloca-tion.

Example: PUSH B or PUSH A14 POP

Reg. pair

Pop off stack to register pairThe contents of the memory location pointed out by the stack pointer register are copied to the low-order register (C, E, L, statusflags)oftheoperand.Thestackpointerisincrementedby 1 and the contents of that memory location are copied to the high-order register (B, D, H, A) of the operand. The stack pointer register is again incremented by 1.Example: POP H or POP A

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15 OUT 8-bit port address

Output data from accumulator to a port with 8-bit addressThe contents of the accumulator are copied into the I/O port specifiedbytheoperand.Example: OUT F8H

16 IN 8-bit port address

Input data to accumulator from a port with 8-bit addressThe contents of the input port designated in the operand are read and loaded into the accumulator.Example: IN 8CH

Arithmetic instructions


17 ADD

RM

Add register or memory to accumulatorThe contents of the operand (register or memory) areM added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory loca-tion,itslocationisspecifiedbythecontentsoftheHLregis-ters.Allflagsaremodifiedtoreflecttheresultoftheaddition.Example: ADD B or ADD M

18 ADC

RM

Add register to accumulator with carryThe contents of the operand (register or memory) and the Carryflagareaddedtothecontentsoftheaccumulatorandthe result is stored in the accumulator. If the operand is a memorylocation,itslocationisspecifiedbythecontentsoftheHLregisters.Allflagsaremodifiedtoreflecttheresultofthe addition.Example: ADC B or ADC M

19 ADI

8-bit data

Add immediate to accumulatorThe 8-bit data (operand) is added to the contents of the ac-cumulatorandtheresultisstoredintheaccumulator.Allflagsaremodifiedtoreflecttheresultoftheaddition.Example: ADI 45H

20 ACI

8-bit data

Add immediate to accumulator with carryThe8-bitdata(operand)andtheCarryflagareaddedtothecontents of the accumulator and the result is stored in the accumulator.Allflagsaremodifiedtoreflecttheresultoftheaddition.Example: ACI 45H

21 DAD

Reg. pair

Add register pair to H and L registersThe16-bitcontentsofthespecifiedregisterpairareaddedtothe contents of the HL register and the sum is stored in the HL register. The contents of the source register pair are not altered.Iftheresultislargerthan16bits,theCYflagisset.Nootherflagsareaffected.Example: DAD H

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22 SUB

RM

Subtract register or memory from accumulatorThe contents of the operand (register or memory) are sub-tracted from the contents of the accumulator, and the result is stored in the accumulator. If the operand is a memory loca-tion,itslocationisspecifiedbythecontentsoftheHLregis-ters.Allflagsaremodifiedtoreflecttheresultofthesubtrac-tion.Example: SUB B or SUB M

23 SBB

RM

Subtract source and borrow from accumulatorThe contents of the operand (register or memory) and the Bor-rowflagaresubtractedfromthecontentsoftheaccumulatorand the result is placed in the accumulator. If the operand is a memorylocation,itslocationisspecifiedbythecontentsoftheHLregisters.Allflagsaremodifiedtoreflecttheresultofthe subtraction.Example: SBB B or SBB M

24 SUI

8-bit data

Subtract immediate from accumulatorThe 8-bit data (operand) is subtracted from the contents of the accumulator and the result is stored in the accumulator. All flagsaremodifiedtoreflecttheresultofthesubtraction.Example: SUI 45H

25 SBI

8-bit data

Subtract immediate from accumulator with borrowThe8-bitdata(operand)andtheBorrowflagaresubtractedfrom the contents of the accumulator and the result is stored in theaccumulator.Allflagsaremodifiedtoreflecttheresultofthe subtraction.Example: SBI 45H

26 INR

RM

Increment register or memory by 1The contents of the designated (register or memory) are incre-mented by 1 and the result is stored in the same place. If the operandisamemorylocation,itslocationisspecifiedbythecontents of the HL registers.Example: INR B or INR M

27 INX

R

Increment register pair by 1The contents of the designated register pair are incremented by 1 and the result is stored in the same place.Example: INX H

28 DCR

RM

Decrement register or memory by 1The contents of the designated register or memory are decre-mented by 1 and the result is stored in the same place. If the operandisamemorylocation,itslocationisspecifiedbythecontents of the HL registers.Example: DCR B or DCR M

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29 DCX

R

Decrement register pair by 1The contents of the designated register pair are decremented by 1 and the result is stored in the same place.Example: DCX H

30 DAA

None

Decimal adjust accumulatorThe contents of the accumulator are changed from a binary value to two 4-bit binary coded decimal (BCD) digits. This is theonlyinstructionthatusestheauxiliaryflagtoperformthebinary to BCD conversion. S,Z,AC,P,CYflagsarealteredtoreflecttheresultsoftheoperation. If the value of the low-order 4-bits in the accumula-torisgreaterthan9orifACflagisset,theinstructionadds6to the low-order four bits.If the value of the high-order 4-bits in the accumulator is greaterthan9oriftheCarryflagisset,theinstructionadds6to the high-order four bits.Example: DAA

Branching instructions


31 JMP

16-bit address

Jump unconditionallyThe program sequence is transferred to the memory location specifiedbythe16-bitaddressgivenintheoperand.Example: JMP 2034H or JMP XYZ

32 JCJNCJPJMJZJNZJPEJPO 16-bit address

Jump conditionallyThe program sequence is transferred to the memory location specifiedbythe16-bitaddressgivenintheoperandbasedonthespecifiedflagofthePSWasdescribedbelow.

Jump on Carry, CY = 1Jump on no Carry, CY = 0Jump on positive, S = 0Jump on minus, S = 1Jump on zero, Z = 1Jump on no zero, Z = 0Jump on parity even, P = 1Jump on parity, odd P = 0Example: JZ 2034H or JZ XYZ

33 CALL

16-bit address

Unconditional subroutine callThe program sequence is transferred to the memory location specifiedby the 16-bit address given in the operand.Beforethe transfer, the address of the next instruction after CALL (the contents of the program counter) is pushed onto the stack.Example: CALL 2034H or CALL XYZ

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34 CCCNCCPCMCZCNZCPECPO

16-bit address Call conditionallyThe program sequence is transferred to the memory location specifiedbythe16-bitaddressgivenintheoperandbasedonthespecifiedflagofthePSWasdescribedbelow.Beforethetransfer,the address of the next instruction after the call (the contents of the program counter) is pushed onto the stack.

Call on Carry, CY = 1Call on no Carry, CY = 0Call on positive, S = 0Call on minus, S = 1Call on zero, Z = 1Call on no zero, Z = 0Call on parity even, P = 1Call on parity odd P = 0Example: CZ 2034H or CZ XYZ

35 RET None Return from subroutine unconditionallyThe program sequence is transferred from the subroutine to the calling program. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address.Example: RET

36 RCRNCRPRMRZRNZRPERPO

None Return from subroutine conditionallyThe program sequence is transferred from the subroutine to thecallingprogrambasedonthespecifiedflagofthePSWasdescribed below. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address.

Return on Carry, CY = 1Return on no Carry, CY = 0Return on positive, S = 0Return on minus, S = 1Return on zero, Z = 1Return on no zero, Z = 0Return on parity even ,P = 1Return on parity odd, P = 0.Example: RZ

37 PCHL None Load program counter with HL contentsThe contents of registers H and L are copied into the program counter. The contents of H are placed as the high-order byte and the contents of L as the low-order byte.Example: PCHL

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38 RST 0-7 RestartThe RST instruction is equivalent to a 1-byte call instruction to one of eight memory locations depending upon the number.The instructions are generally used in conjunction with interrupts and inserted using external hardware. However these can be used as software instructions in a program to transfer program execution to one of the eight locations. The addresses are

The 8085 has four additional interrupts and these interrupts generate RST instructions internally and thus do not require any external hardware. These instructions and their Restart addresses are

Instruction Restart AddressRST 0 0000HRST 1 0008HRST 2 0010HRST 3 0018HRST 4 0020HRST 5 0028HRST 6 0030HRST 7 0038H

Instruction Restart AddressTRAP 0024HRST 5.5 002CHRST 6.5 0034HRST 7.5 003CH

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Logical instructions


39 CMP

RM

Compare register or memory with accumulatorThe contents of the operand (register or memory) are compared with the contents of the accumulator. Both contents are preserved. TheresultofthecomparisonisshownbysettingtheflagsofthePSW as follows:

if(A)<(reg/mem):carryflagissetif(A)=(reg/mem):zeroflagissetif(A)>(reg/mem):carryandzeroflagsareresetExample: CMP B or CMP M

40 CPI

8-bit data

Compare immediate with accumulatorThe second byte (8-bit data) is compared with the contents of the accumulator. The values being compared remain unchanged. TheresultofthecomparisonisshownbysettingtheflagsofthePSW as follows:if(A)<data:carryflagissetif(A)=data:zeroflagissetif(A)>data:carryandzeroflagsareresetExample: CPI 89H

41 ANA

RM

Logical AND register or memory with accumulatorThe contents of the accumulator are logically ANDed with the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, itsaddressisspecifiedbythecontentsofHLregisters.S,Z,Paremodifiedtoreflecttheresultoftheoperation.CYisreset.AC is set.Example: ANA B or ANA M

42 ANI

8-bit data

Logical AND immediate with accumulatorThe contents of the accumulator are logically ANDed with the8-bit data (operand) and the result is placed in the accumulator. S,Z,Paremodifiedtoreflecttheresultoftheoperation.CYisreset. AC is set.Example: ANI 86H

43 XRA

RM

Exclusive OR register or memory with accumulatorThe contents of the accumulator are Exclusive ORed with the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, itsaddressisspecifiedbythecontentsofHLregisters.S,Z,Paremodifiedtoreflecttheresultoftheoperation.CYandACare reset.Example: XRA B or XRA M

44 XRI

8-bit data

Exclusive OR immediate with accumulatorThe contents of the accumulator are Exclusive ORed with the 8-bit data (operand) and the result is placed in the accumulator. S,Z,Paremodifiedtoreflecttheresultoftheoperation.CYand AC are reset.Example: XRI 86H

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45 ORA

RM

Logical OR register or memory with accumulatorThe contents of the accumulator are logically ORed with the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, itsaddressisspecifiedbythecontentsofHLregisters.S,Z,Paremodifiedtoreflecttheresultoftheoperation.CYandACare reset.Example: ORA B or ORA M

46 ORI

8-bit data

Logical OR immediate with accumulatorThe contents of the accumulator are logically ORed with the 8-bit data (operand) and the result is placed in the accumulator. S,Z,Paremodifiedtoreflecttheresultoftheoperation.CYand AC are reset.Example: ORI 86H

47 RLC

None

Rotate accumulator leftEach binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position of D0 as well as in the Carry flag.CYismodifiedaccordingtobitD7.S,Z,P,ACarenotaffected.Example: RLC

48 RRC

None

Rotate accumulator rightEach binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of D7 as well as in the Carryflag.CYismodifiedaccordingtobitD0.S,Z,P,ACarenot affected.Example: RRC.

49 RAL

None

Rotate accumulator left through carryEach binary bit of the accumulator is rotated left by one position throughtheCarryflag.BitD7isplacedintheCarryflag,andtheCarryflagisplacedintheleastsignificantpositionD0.CYismodifiedaccordingtobitD7.S,Z,P,ACarenotaffected.Example: RAL

50 RAR

None

Rotate accumulator right through carryEach binary bit of the accumulator is rotated right by one position throughtheCarryflag.BitD0isplacedintheCarryflag,andtheCarryflagisplacedinthemostsignificantpositionD7.CYismodifiedaccordingtobitD0.S,Z,P,ACarenotaffected.Example: RAR

51 CMA

None

Complement accumulatorThecontentsoftheaccumulatorarecomplemented.Noflagsare affected.Example: CMA

52 CMC None

Complement carryTheCarryflagiscomplemented.Nootherflagsareaffected.Example: CMC

43 STC None

Set CarryTheCarryflagissetto1.Nootherflagsareaffected.Example: STC

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Control instructions


44 NOP None No operationNo operation is performed. The instruction is fetched and decoded. However no operation is executed.Example: NOP

45 HLT None Halt and enter wait stateTheCPUfinishes executing the current instructionandhaltsany further execution. An interrupt or reset is necessary to exit from the halt state.Example: HLT

46 DI None Disable interruptsTheinterruptenableflipflopisresetandalltheinterruptsexcepttheTRAParedisabled.Noflagsareaffected.Example: DI

47 EI None Enable interruptsThe interrupt enable flip flop is set and all interrupts are enabled.No flags are affected.After a system reset or theacknowledgementofaninterrupt,theinterruptenableflipflopisreset, thus disabling the interrupts. This instruction is necessary to re-enable the interrupts (except TRAP).Example: EI

48 RIM None This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations.Example: RIM

49 SIM None Set interrupt maskThis is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator contents as follows.Example: SIM

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SummaryA microprocessor is a multipurpose, programmable logic device that reads binary instructions from a storage •device called memory. It accepts binary data as input and processes data according to those instructions and provides results as output.The microprocessor is programmable device that can be instructed to perform given tasks within its capacity.•The user can enter instructions and data into memory through devices such as keyboard or simple switches, •these devices are called input devices.The output devices transfer data from the microprocessor to the outside world. They include devices such as •Light Emitting Diodes (LED’s), a Cathode Ray Tube (CRT) or video screen, a printer, X-Y plotter, a magnetic tape, and digital – to analog (D/A) converter. The microprocessor is a semiconductor device consisting of electronic logic circuits manufactured by using •either a large-scale integration (LSI) or very-large-scale integration (VLSI) technique.The control unit provides the necessary timing and control signals to all the operations in the •microcomputers.Memory stores such binary information as instructions and data, and provides that information to the •microprocessor whenever necessary.The system bus is a communication path between the microprocessor and peripherals; it is nothing but a group •of wires to carry bits.The8085have6general-purposeregisterstoperformthefirstoperations:store8-bitdata,theseregistersare•identifiedasB,C,D,E,HandL.TheALUincludesfiveflipflops,whicharesetorresetafteranoperationaccordingtodataconditionsofthe•resultintheaccumulatorandotherregisters.Theseflipflopsarecalledflags.Aninstructionisabinarypatterndesignedinsideamicroprocessortoperformaspecificfunction.•

References8085 Instruction Set. Available at: <http://ce.sharif.ir/courses/86-87/1/ce126/resources/root/instructionset8085.•pdf> [Accessed on 24th February, 2011].D.A.Godse, A.P.Godse, 2007. • Elements of Microprocessors. Technical Publications. pp 51–52.Mathur. • Microprocessor 8085 and Its Interfacing. PHI Learning Pvt. Ltd. pp.40–45.Number System and Binary Codes. Available at: <http://www.b-u.ac.in/sde_book/bca_fund.pdf> [Accessed on •24th February, 2011].Tutorial on Introduction to 8085 Architecture and Programming. Available at: <http://webphysics.davidson.•edu/faculty/dmb/py310/8085.pdf> [Accessed on 24th February, 2011].

Recommended ReadingA.P.Godse, D.A.Godse, 2006. • Microprocessors and Applications. Technical Publications, 1st edition. p.738.John Uffenbeck, (1999). • Microcomputers and Microprocessors: The 8080, 8085, and Z-80 Programming, Interfacing, and Troubleshooting. Prentice Hall, 3rd edition. p.729.Ramesh S. Gaonkar, 2004. • Microprocessor Architecture, Programming, and Applications with the 8085. Prentice Hall, 5th edition. p.820.

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Self Assessment

A set of instructions written for the microprocessor to perform a task is called a __________.1. programa. datab. softwarec. informationd.

The __________________ is programmable device that can be instructed to perform given tasks within its 2. capacity.

microchipa. microprocessorb. ICc. microcomputerd.

The ________________ unit performs arithmetic operations as addition and subtraction, and logic operations 3. such as AND, OR and exclusive OR.

CPUa. controlb. ALUc. logicd.

The ___________ unit provides the necessary timing and control signals to all the operations in the 4. microcomputers.

logica. internalb. externalc. controld.

The ____________ is used to store programs that do not need alterations.5. ROMa. RAMb. cachec. virtual d.

Inwhichofthefollowingaddressingmode,theoperandisnotspecifiedexplicitlyintheinstruction?6. Indirecta. Implied b. Immediatec. Registerd.

Inwhichofthefollowingaddressingmode,8or16bitdatacanbespecifiedasapartofinstruction?7. Indirecta. Implied b. Immediatec. Registerd.

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Which of the following pin indicates CPU is being reset? 8. RESET INa. BUSYb. INTRc. RESET OUTd.

State which of the following statements is true.9. The system bus is a communication path between the microprocessor and peripherals.a. The address bus is a communication path between the microprocessor and peripherals.b. The data bus is a communication path between the microprocessor and peripherals.c. The central bus is a communication path between the microprocessor and peripherals.d.

State which of the following statements is true.10. If Busy signal is high during a read or write cycle, it indicates that the memory or peripheral is ready to a. send or receive data.If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or b. receive data.If INTR is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or c. receive data.If INTA is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or d. receive data.

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Chapter III

Memory and Interfacing

Aim


explore memory and I/O devices•

analyse I/O addressing devices•

elucidate various• tri-state devices

Objectives


examine memory mapped I/O and I/O mapped I/O devices•

study interfacing of input and output devices•

determine tri-state buffer•

Learning outcome


understand memory and I/O devices•

explain I/O addressing devices•

identify the difference between memory mapped I/O and I/O mapped I/O devices•

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3.1 MemoryMemory is basically a data storage device. For any microprocessor system, we require memories to store monitor program, to store user program and to store data. So memory is an essential component in microprocessor system which will allow the user to store program and data. Memory consists of thousands of memory cells. Each memory cell is capable of storing 1-bit. Memory in a microprocessor system is where information (data and instructions) is kept.Itcanbeclassifiedintotwomaintypes:

Main memory (RAM and ROM)•Storage memory (Disks, CD ROMs, etc.)•

ThesimpleviewofRAMisthatitismadeupofregistersthataremadeupofflipflops(ormemoryelements).Thenumberofflipflopsina'memoryregister'determinesthesizeofthememoryword.ROMontheotherhandusesdiodesinsteadoftheflipflopstopermanentlyholdtheinformation.For the microprocessor to access (Read or Write) information in memory (RAM or ROM), it needs follow the following steps:

Select the right memory chip (using part of the address bus).•Identify the memory location (using the rest of the address bus).•Access the data (using the data bus).•

3.2 I/O DevicesInput and output (IO) devices are used to enter data to the microprocessor and to take out data from •the microprocessor from external world. The input and output devices are used to get output from the microprocessor. Input/output, or I/O, refers to the communication between an information processing system and the outside •world-possibly a human or another information processing system. Inputs are the signals or data received by the system and outputs are the signals or data sent from it. The term can also be used as part of an action; 'perform I/O' means to perform an input or output operation. I/O •devices are used by a person to communicate with a computer. For instance, keyboard and mouse are considered input devices of a computer, while monitors and printers are •considered output devices of a computer. Devices for communication between computers, such as modems and network cards, typically serve for both •input and output. Input and output devices are connected to the microprocessor through some interfacing devices as shown here.

Fig. 3.1 I/O interfacing

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3.3 I/O AddressingThe I/O devices in 8085 may be interface with 8085 in two different ways, i.e., I/O mapped I/O and memory mapped I/O. These two methods of I/O interfacing give rise to two different I/O address spaces.Let us the difference between I/O mapped I/O and memory mapped I/O.

Memory mapped I/O I/O mapped I/O

16-bit addresses are provided for I/O devices. 8-bit addresses are provided for I/O devices

The devices are accessed by memory read or memory write cycles.

The devices are accessed by I/O read or I/O write cycles. During these cycles the 8-bit address is available on both low order address lines and high order address lines.

The I/O ports or peripherals can be treated like memory locations and so all instructions related to memory can be used for data transfer between I/O device and the processor.

Only IN and OUT instructions can be used for data transfer between I/O device and the processor.

In memory mapped ports the data can be moved from any register to ports and vice-versa.

In I/O mapped ports the data transfer can take place only between the accumulator and ports.

When memory mapping is used for I/O devices, the full memory address space cannot be used for addressing memory. Hence memory mapping is useful only for small systems, where the memory requirement is less.

When I/O mapping is used for I/O devices, the full memory address space can be used for addressing memory. Hence it is suitable for systems which require large memory capacity.

In memory mapped I/O devices, a large number if I/O ports can be interfaced.

In I/O mapping only256 ports (28 = 256) can be interfaced.

For accessing the memory mapped devices, the processor executes memory read or write cycle. During this cycle is asserted low ( =0).

For accessing the I/O mapped devices, the processor executes I/O read or write cycle. During this cycle is asserted low ( ).

Table 3.1 Difference between I/O mapped I/O and memory mapped I/O

3.4 Interfacing of Input DeviceInput devices are used to input data to the microprocessor. A common example of an input device is the keyboard •asshowninfigure.SuchanI/Odeviceisnotdirectlyconnectedtothemicroprocessorbutconnectedthroughan interface, i.e., a buffer gate IC.The DIP switches cannot be directly connected to the data lines of the microprocessor. These are connected to •themicroprocessorthroughthebuffergateIC.Onesuchchipisthe74LS244chipshowninfigurealongwithits internal logic diagram.Thisbufferchipperformstwoimportantfunctions:firstly,itincreasesthedrivingcapabilitiesofthebusesand•secondly, it is used to select the input device through its OE signal.

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Fig. 3.2 DIP switches

Fig. 3.3 Pin and logic diagram of 74244

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Fig. 3.4 Interfacing of input device

Asshowninfigure,theaddresslinesaredecoded,eitherusingaNAND(orAND)gateorusingadecoder,to•generate an address select signal. The address lines may be A0-A15 in case of memory mapped IO scheme.Then the address select signal is NANDed with the control signal IOR (in case of IO mapped IO).•The output of the NAND gate will generate the chip select signal, which is applied to the OE signal of the •74244 buffer chip.When the OE signal goes low it will enable the buffer and microprocessor will start reading the switch position •and load it into the accumulator.

3.5 Interfacing Output DataOutput devices are used to take data from the microprocessor. A common example of an output device is the •display devices such as LED or LCD or seven segment displays. Fig. 3.6 shows a simple seven segment display. Such an IO device is not directly connected to the microprocessor, but connected through a latch IC.Figure below shows the pin and internal diagram of latch 74273. The eight latches of the DM74ALS373 are •transparent D-type latches. While the enable is taken low, the output will be latched at the level of the data that was set up.A buffered output control input can be used to place the eight outputs in either a normal logic state (high or low •logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus linessignificantly.Theoutputcontroldoesnotaffecttheinternaloperationofthelatches.Thatis,theolddatacan be retained or new data can be entered even while the outputs are off.

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Fig. 3.5 LED display

Fig. 3.6 Internal diagram of latch IC 74273

Figure below gives the basic principal of interfacing an output device. To generate an address, a signal is selected. •The address lines are decoded, either using NAND (or AND) gate or using a decoder. The address lines may be A0-A7, in case of IO mapped IO or may be A0-A15 in case of memory mapped IO scheme.Then the address select signal is NANDed with control signal IOW (in case of IO mapped IO) or with MEMW •(in case of memory mapped IO).The output of NAND gate will generate the chip select signal, which is applied to the output control signal OE •of the 74273 latch chip. The OE signal enabled the tri-stated buffer gates. The control input G is connected to theclocksoastotriggertheDflipflops.

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Fig. 3.7 Principal of interfacing an output device

Whenmicroprocessorwantstosendsomedatafordisplay,theOEsignalgoeslow,itwilltriggertheflipflopsand•the microprocessor data will be latched into the latches, which will then be available at the display section.

3.6 Tri-state BufferTri-state buffer is an important circuit element that is used extensively in memory.•This buffer is a logic circuit that has three states: Logic 0, logic1, and high impedance.•When this circuit is in high impedance mode it looks as if it is disconnected from the output completely.•

Fig. 3.8 Tri-state buffer

Thiscircuithastwoinputsandoneoutput:Thefirstinputbehaveslikethenormalinputforthecircuit.The•second input is an 'enable'.If it is set high, the output follows the proper circuit behaviour.•If it is set low, the output looks like a wire connected to nothing.•

Fig. 3.9 Tri-state buffer circuit

The Output is Low The Output is High High Impedance

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SummaryMemory is basically a data storage device. It consists of thousands of memory cells.•Input and output devices are connected to the microprocessor through some interfacing device.•Memory in a microprocessor system is where information (data and instructions) is kept.•ThesimpleviewofRAMisthatitismadeupofregistersthataremadeupofflipflops•Thenumberofflipflopsina'memoryregister'determinesthesizeofthememoryword.•ROMontheotherhandusesdiodesinsteadoftheflipflopstopermanentlyholdtheinformation.•Input/output, or I/O, refers to the communication between an information processing system and the outside •world-possibly a human or another information processing system. Inputs are the signals or data received by the system and outputs are the signals or data sent from it. The I/O devices in 8085 may be interface with 8085 in two different ways, i.e., I/O mapped I/O and memory mapped I/O.Input devices are used to input data to the microprocessor. A common example of an input device is the •keyboard.Output devices are used to take data from the microprocessor. A common example of an output device is the •display devices such as LED or LCD or seven segment displays.

ReferencesDr. Bassel Soudan. Microprocessors & Interfacing. Available at: <http://www.scribd.com/doc/7305870/•Microprocessor-Architecture> [Accessed 19th February, 2011].I/O Interfacing with 8085. Available at: <http://www.8085projects.info/IO-Interfacing-Methods.html> [Accessed •19th February, 2011].Shankar. How to Interface the 8085 Microprocessor? Available at <http://www.brighthub.com/engineering/•electrical/articles/53885.aspx> [Accessed 19th February, 2011].

Recommended ReadingJohn Uffenbeck, 1999. • Microcomputers and Microprocessors: The 8080, 8085, and Z-80 Programming, Interfacing, and Troubleshooting. Prentice Hall, 3rd edition. p.729.MohamedRafiquzzaman,1995.• Microprocessors and Microcomputer Based System Design, CRC-Press, 2nd edition. p.800.William Routt, 2006. • Microprocessor Architecture, Programming, and Systems Featuring the 8085. Delmar Cengage Learning, 1st edition. p.288.

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Self Assessment

___________ is basically a data storage device.1. Memorya. CPUb. ALUc. Accumulatord.

Memory consists of thousands of memory 2. __________.chipsa. cellsb. gridsc. rowsd.

Input and output devices are connected to the 3. ___________ through some interfacing device.CPUa. ALUb. microprocessorc. computerd.

Memory in a microprocessor system is where4. ___________ is kept.cella. interruptb. subroutinec. informationd.

The simple view of 5. ___________ isthatitismadeupofregistersthataremadeupofflipflopsRAMa. ROMb. cachec. virtual memoryd.

State which of the following statements is true.6. Thenumberofflipflopsina'memoryregister'determinesthesizeofthememorybyte.a. Thenumberofflipflopsina'memoryregister'determinesthesizeofthememoryword.b. The number of cells in a 'memory register' determines the size of the memory word.c. The number of gates in a 'memory register' determines the size of the memory word.d.

State which of the following statement is true.7. RAMusesdiodesinsteadoftheflipflopstopermanentlyholdtheinformation.a. ROMusesgatesinsteadoftheflipflopstopermanentlyholdtheinformation.b. ROMusesdiodesinsteadoftheflipflopstopermanentlyholdtheinformation.c. ROMusesdiodesinsteadoftheflipflopstotemporarilyholdtheinformation.d.

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In I/O mapping how many ports can be interfaced?8. Twoa. Fiveb. 255c. 256d.

In which of the following does the data transfer can take place only between the accumulator and ports?9. I/O mapped I/O portsa. Memory mapped I/Ob. Memory mapped memoryc. Accumulator mapped portsd.

In which of these16-bit addresses are provided for I/O devices?10. I/O mapped I/O portsa. Memory mapped I/Ob. Memory mapped memoryc. Accumulator mapped portsd.

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Chapter IV

Programming Techniques

Aim


illustrate the timing diagram for 8085 •

analyse stack and subroutines •

explore• counter and time delays

Objectives


examine machine and instruction cycle•

study operation on stack and subroutines•

explain counter and time delays•

Learning outcome


recall timing diagram of op-code fetch•

explain POP, PUSH, CALL and RET instructions•

recall types of passing data to subroutine•

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4.1 Timing DiagramTiming diagram is the display of initiation of read/write and transfer of data operations under the control of 3-status signals IO/M, S1, and S0. As the heartbeat is required for the survival of the human being, the CLK is required for the proper operation of different sections of the microprocessors. All actions in the microprocessor are controlled by either leading or trailing edge of the clock. Each machine cycle is composed of many clock cycles. Since, the data andinstructions,botharestoredinthememory,theμPperformsfetchoperationtoreadtheinstructionordataandthenexecutetheinstruction.TheμP,indoingso,maytakeseveralcyclestoperformfetchandexecuteoperation.

The 3-status signals - IO/M, S1, and S0 are generated at the beginning of each machine cycle. The unique combination of these 3-status signals identify read or write operation and remain valid for the duration of the cycle. Table 4.1 shows details of the unique combination of these status signals to identify different machine cycles. Thus, time taken byanyμPtoexecuteoneinstructioniscalculatedintermsoftheclockperiod.TheexecutionofinstructionalwaysrequiresreadandwritesoperationstotransferdatatoorfromtheμPandmemoryorI/Odevices.Eachread/writeoperationconstitutesonemachinecycle(MC1)asindicatedinfig.4.1.Eachmachinecycleconsistsofmanyclockperiods/ cycles, called T-states. The heartbeat of the microprocessor is the clock period. Each and every operation inside the microprocessor is under the control of the clock cycle. The clock signal determines the time taken by the microprocessor to execute any instruction. The clock cycle has two edges (leading and trailing or lagging). State is definedasthetimeintervalbetween2-trailingandleadingedgesoftheclock.Machinecycleisthetimerequiredto transfer data to or from memory or I/O devices.

Table 4.1 Machine cycle status and control signals

Fig. 4.1 Machine cycle showing clock periods

4.2 Processor CycleThe functions of the microprocessor are divided into fetch and execute cycles of any instruction of a program. •The program is nothing but number of instructions stored in the memory in sequence. In the normal process of operation, the microprocessor fetches (receives or reads) and executes one instruction •at a time in the sequence until it executes the halt (HLT) instruction. Thus,aninstructioncycleisdefinedasthetimerequiredtofetchandexecuteaninstruction.Forexecutingany•

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program, basically 2-steps are followed sequentially with the help of clocks:Fetch �Execute �

ThetimetakenbytheμPinperformingthefetchandexecuteoperationsarecalledfetchandexecutecycle.Thus,sumofthefetchandexecutecycleiscalledtheinstructioncycle,asindicatedinfig.4.2

Fig. 4.2 Processor cycle

These cycles have been illustrated in Fig. 4.2 and 4.3. Each read or writes operation constitutes a machine cycle. The instructions of 8085 require 1–5 machine cycles containing 3–6 states (clocks). The 1st machine cycle of any instruction is always an Op-code fetch cycle in which the processor decides the nature of instruction. It is of at least 4-states and may go up to 6-states.

Fig. 4.3 Ideal wave shape relationship for FC, EC, MC, and IC.

It is well known that an instruction cycle consists of many machine cycles. Each machine cycle consists of many •clock periods or cycles, called T-states. The 1st machine cycle (M1) of every instruction cycle is the op-code fetch cycle. In the op-code fetch cycle, the processor comes to know the nature of the instruction to be executed. The processor during (M1 cycle) puts the program counter contents on the address bus and reads the op-code •of the instruction through read process. The T1, T2, and T3 clock cycles are used for the basic memory read operation and the T4 clock and beyond are used for its interpretation of the op-code. Basedontheseinterpretations,theμPcomestoknowthetypeofadditionalinformation/dataneededforthe•execution of the instruction and accordingly proceeds further for 1 or 2-machine cycle of memory read and writes.Theop-codefetchcycle isoffixedduration(normally4-states),whereas the instructioncycle isofvariable duration depending on the length of the instruction.As an example, STA instruction, requires op-code fetch cycle, lower-order address fetch cycle and higher order •fetch cycle and then the execute cycle. Thus, op-code fetch cycle is of one machine cycle in this example. A particularmicroprocessorrequiresadefinitetimetoperformingaspecifictask.Thistimeiscalledmachinecycle. Thus,onemachinecycleisrequiredeachtimetheμPaccessI/Oportormemory.Afetchop-codecycleisalways•1-machine cycle, whereas, execute cycle may be of one or more machine cycle depending upon the length of the instruction.

Instruction Fetch (FC) � ⇒ An instruction of 1 or 2 or 3-bytes is extracted from the memory locations during thefetchandstoredintheμP’sinstructionregister.

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Instruction Execute (EC) � ⇒ Theinstructionisdecodedandtranslatedintospecificactivitiesduringtheexecution phase. Thus, in an instruction cycle, instruction fetch, and instruction execute cycles are related as depicted in Fig. 4.2. Every instruction cycle consists of 1, 2, 3, 4 or 5-machine cycles as indicated in fig.4.4.OnemachinecycleisrequiredeachtimetheμPaccessmemoryorI/Oport.Thefetchcycle,ingeneralcouldbe4to6-stateswhereastheexecutecyclecouldof3to6-states.Thefirstmachinecycleofanyinstructionisalwaysthefetchcyclethatprovidesidentificationoftheinstructiontobeexecuted.

The fetch portion of an instruction cycle requires one machine cycle for each byte of instruction to be fetched. •Sinceinstructionisof1to3byteslong,theinstructionfetchisoneto3-machinecyclesinduration.Thefirstmachine cycle in an instruction cycle is always an op-code fetch. The 8-bits obtained during an op-code fetch are always interpreted as the op-code of an instruction. The machine •cycle including wait states is shown below.

Fig. 4.4 Machine cycle including wait states

A typical fetch cycle is shown below. Here, only two clock cycles have been shown as the requirement to read •the instruction. Since the access time of the memory may vary and it may require more than 2-clock cycles, the microprocessor has to wait for more than 2-clocks duration before it receives the op-code instruction. Hence, most of the microprocessors have the provisions of introducing wait cycle within the fetch cycle to cope •up with the slow memories or I/O devices.

Fig. 4.5 Fetch cycle

4.3 Op-code FetchA microprocessor either reads or writes to the memory or I/O devices. The time taken to read or write for any •instructionmustbeknownintermsoftheμPclock.The1ststepincommunicatingbetweenthemicroprocessorand memory is reading from the memory. This reading process is called op-code fetch. The process of op-code fetch operation requires minimum 4-clock cycles T1, T2, T3, and T4 and is the 1st •machine cycle (M1) of every instruction. In order to differentiate between the data byte pertaining to an op-code or an address, the machine cycle takes help of the status signal IO/M, S1, and S0. The IO/M = 0 indicates memory operation and S1 = S0 = 1 indicates op-code fetch operation.The op-code fetch machine cycle M1 consists of 4-states (T1, T2, T3, and T4). The 1st 3-states are used for •fetching (transferring) the byte from the memory and the 4th-state is used to decode it. Thus, thorough understanding about the communication between memory and microprocessor can be achieved •only after knowing the processes involved in reading or writing into the memory by the microprocessor and time taken w.r.t. its clock period. This can be explained by examples.

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Theprocessofimplementationofeachinstructionfollowsthefetchandexecutescycles.Inotherwords,first•the instruction is fetched from memory and then executed. Fig. 4.6 and 4.7 depict these 2-steps for implementation of the instruction ADI 05H. Let us assume that the •accumulator contains the result of previous operation i.e., 03H and instruction is held at memory locations 2030H and 2031H.

Fig. 4.6 Instruction fetch: reads 1st byte (op-code) in instruction register (IR)

The fetch part of the instruction is the same for every instruction. The control unit puts the contents of the •program counter (PC) 2030H on the address bus. The 1st byte (op-code C6H in this example) is passed to the instruction register. In the execute cycle of the instruction, the control unit examines the op-code and as per interpretation further •memory read or write operations are performed depending upon whether additional information/ data are required or not. In this case, the data 05H from the memory is transferred through the data bus to the ALU. At the same time the •control unit sends the contents of the accumulator (03H) to the ALU and performs the addition operation. The result of the addition operation 08H is passed to the accumulator overriding the previous contents 03H. •On the completion of one instruction, the program counter is automatically incremented to point to the next memory location to execute the subsequent instruction.

Fig. 4.7 Instruction execute: reads 2nd byte from memory and adds to accumulator

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4.4 Timing Diagram of Op-code FetchThe process of op-code fetch operation requires minimum 4-clock cycles T1, T2, T3, and T4 and is the 1st machine cycle (M1) of every instruction.

ExampleFetch a byte 41H stored at memory location 2105H.

Forfetchingabyte,themicroprocessormustfindoutthememorylocationwhereitisstored.Thenprovidecondition(control)fordataflowfrommemorytothemicroprocessor.Theprocessofdataflowandtimingdiagramoffetchoperationareshowninfigs.4.8.TheμPfetchesop-codeoftheinstructionfromthememoryas per the sequence below.

A low IO/M means microprocessor wants to communicate with memory.•TheμPsendsahighonstatussignalS1andS0indicatingfetchoperation.•TheμPsends16-bitaddress.ADbushasaddressin1stclockofthe1stmachinecycle,T1.•AD7 to AD0 address is latched in the external latch when ALE = 1.•AD bus now can carry data.•In T2, the RD control signal becomes low to enable the memory for read operation.•The memory places op-code on the AD bus.•The data is placed in the data register (DR) and then it is transferred to IR.•

Fig. 4.8 Op-code fetch

During T3, the RD signal becomes high and memory is disabled.•During T4, the op-code is sent for decoding and decoded in T4.•The execution is also completed in T4 if the instruction is single byte.•More machine cycles are essential for 2- or 3-byte instructions.•M1 is meant for fetching the op-code. The machine cycles M2 and M3 are required to read/ write data or address •from the memory or I/O devices.

Read cycleThe high order address (A15 • ⇔ A8) and low order address (AD7 ⇔ AD0) are asserted on 1st low going transition of the clock pulse.

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The timing diagram for IO/M read is shown in Fig. 4.9 and 4.10. The A15 • ⇔ A8 remains valid in T1, T2, and T3 i.e., duration of the bus cycle, but AD7 ⇔ AD0 remains valid only in T1. Since it has to remain valid for the whole bus cycle, it must be saved for its use in the T2 and T3.

Fig. 4.9 Memory read timing diagram

ALE is asserted at the beginning of T1 of each bus cycle and is negated towards the end of T1. ALE is active •during T1 only and is used as the clock pulse to latch the address (AD7 ⇔AD0) during T1. The RD is asserted near the beginning of T2. It ends at the end of T3. As soon as the RD becomes active, it forces the memory or I/O port to assert data. RD •becomes inactive towards the end of T3, causing the port or memory to terminate the data.

Fig. 4.10 I/O read timing diagram

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Write cycleImmediately after the termination of the low order address, at the beginning of the T2, data is asserted on the •address/data bus by the processor. WR control is activated near the start of T2 and becomes inactive at the end of T3. The processor maintains valid data until after WR is terminated. This ensures that the memory or port has valid •datawhileWRisactive.Itisclearfromfig.4.11and4.12thatforREADbuscycle,thedataappearsonthebusas a result of activating RD and for the WR bus cycle, the time the valid data is on the bus overlaps the time that the WR is active.

Fig. 4.11 Memory write timing diagram

Fig. 4.12 I/O write timing diagram

4.5 Stack Thestackisanareaofmemoryidentifiedbytheprogrammerfortemporarystorageofinformation.•The stack is a LIFO structure – Last In First Out. The stack normally grows backwards into memory.•Inotherwords,theprogrammerdefinesthebottomofthestackandthestackgrowsupintoreducingaddress•range.Given that the stack grows backwards into memory, it is customary to place the bottom of the stack at the end •of memory to keep it as far away from user programs as possible. Inthe8085,thestackisdefinedbysettingtheSP(StackPointer)register.•

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LXI SP, FFFFHThis sets the stack pointer to location FFFFH (end of memory for the 8085). The size of the stack is limited •only by the available memory.Information is saved on the stack by PUSHing it on.•It is retrieved from the stack by POPing it off.•The 8085 provides two instructions: PUSH and POP for storing information on the stack and retrieving it •back.Both PUSH and POP work with register pairs only.•

4.5.1 The PUSH Instruction

PUSH B (1 Byte Instruction)•Decrement SP•Copy the contents of register B to the memory location pointed to by SP•Decrement SP•Copy the contents of register C to the memory location pointed to by SP•

Fig. 4.13 PUSH instruction

4.5.2 The POP Instruction

POP D (1 Byte Instruction)•Copy the contents of the memory location pointed to by the SP to register E•Increment SP•Copy the contents of the memory location pointed to by the SP to register D•Increment SP•

Fig. 4.14 POP instruction

4.5.3 Operation on Stack

During pushing, the stack operates in a 'decrement then store' style.•Thestackpointerisdecrementedfirst,andthentheinformationisplacedonthestack.•During POPing, the stack operates in a 'use then increment' style.•The information is retrieved from the top of the stack and then the pointer is incremented.•The SP pointer always points to 'the top of the stack'.•

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4.6 SubroutinesA subroutine is a group of instructions that will be used repeatedly in different locations of the program.•Rather than repeating the same instructions several times, they can be grouped into a subroutine that is called •from the different locations.In assembly language, a subroutine can exist anywhere in the code.•However, it is customary to place subroutines separately from the main program.•The 8085 has two instructions for dealing with subroutines.•The CALL instruction is used to redirect program execution to the subroutine.•The RET instruction is used to return the execution to the calling routine.•

4.6.1 The CALL Instruction

CALL 4000H (3 byte instruction)•When CALL instruction is fetched, the MP knows that the next two memory locations contain 16bit subroutine •address in the memory.

Fig. 4.15 CALL Instruction

MP reads the subroutine address from the next two memory location and stores the higher order 8bit of the •address in the W register and stores the lower order 8bit of the address in the Z register.Pushes the address of the instruction immediately following the CALL onto the stack [Return address].•Loads the program counter with the 16-bit address supplied with the CALL instruction from WZ register.•

4.6.2 The RET Instruction

RET (1 byte instruction)•Retrieve the return address from the top of the stack.•Load the program counter with the return address.•

Fig. 4.16 RET Instruction

4.6.3 Subroutine Operation

The CALL instruction places the return address at the two memory locations immediately before where the •stack pointer is pointing.You must set the SP correctly BEFORE using the CALL instruction.•

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The RET instruction takes the contents of the two memory locations at the top of the stack and uses these as •the return address.Do not modify the stack pointer in a subroutine. You will lose the return address•Number of PUSH and POP instruction used in the subroutine must be same, otherwise, RET instruction will •pick wrong value of the return address from the stack and program will fail.

4.6.4 Passing Data to SubroutineData is passed to a subroutine through registers.

Call by reference:• The data is stored in one of the registers by the calling program and the subroutine uses the valuefromtheregister.Theregistervaluesgetmodifiedwithinthesubroutine.Thenthesemodificationswillbe transferred back to the calling program upon returning from a subroutine.Call by value:• Thedataisstoredinoneoftheregisters,butthesubroutinefirstPUSHESregistervaluesinthestack and after using the registers, it POPS the previous values of the registers from the stack while exiting the subroutine. The original values are restored before execution returns to the calling program.

4.7 CountersA loop counter is set up by loading a register with a certain value.•Then using the DCR (to decrement) and INR (to increment) the contents of the register are updated.•A loop is set up with a conditional jump instruction that loops back or not depending on whether the count has •reached the termination count.Theoperationofaloopcountercanbedescribedusingthefollowingflowchart.•

Fig. 4.17 Counters

4.8 DelaysWe have seen that each instruction passes through different combinations of Fetch, Memory Read, and Memory •Write cycles.Knowing the combinations of cycles, one can calculate how long such an instruction would require to •complete.Knowing how many T-States an instruction requires, and keeping in mind that a T-State is one clock cycle long, •we can calculate the time using the following formula:

Delay = No. of T-States / FrequencyFor example a 'MVI' instruction uses 7 T-States. •Therefore, if the Microprocessor is running at 2 MHz, the instruction would require 3.5µ seconds to •complete.

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Summary Timing diagram is the display of initiation of read/write and transfer of data operations under the control of •3-status signals IO/M, S1, and S0.Theexecutionofinstructionalwaysrequiresreadandwritesoperationstotransferdatatoorfromtheμpand•memory or I/O devices.The 3-status signals: IO/M, S1, and S0 are generated at the beginning of each machine cycle.•The functions of the microprocessor are divided into fetch and execute cycles of any instruction of a •program.Each machine cycle consists of many clock periods or cycles, called T-states.•Forfetchingabyte,themicroprocessormustfindoutthememorylocationwhereitisstored.•The 1• st machine cycle (M1) of every instruction cycle is the op-code fetch cycle.Theop-codefetchcycleisoffixedduration(normally4-states),whereastheinstructioncycleisofvariable•duration depending on the length of the instruction.ThetimetakentoreadorwriteforanyinstructionmustbeknownintermsoftheμPclock.•Thestackisanareaofmemoryidentifiedbytheprogrammerfortemporarystorageofinformation.•A subroutine is a group of instructions that will be used repeatedly in different locations of the program.•Rather than repeating the same instructions several times, they can be grouped into a subroutine that is called •from the different locations.

ReferencesMohd. Moinul Hoque. Stack and Subroutines. Available at: <http://www.aust.edu/cse/moinul/Stack_and_•Subroutine.pdf > [Accessed on 10th February, 2011].Timing Diagram 8085. Available at: <http://www.newagepublishers.com/samplechapter/000495.pdf> [Accessed •on 10th February, 2011].

Recommended ReadingG.T. Swamy, 2006. • Microprocessor [8085] Lab Manual. Laxmi Publications. p.70.Mrs. Deepali A. Godse, Mr. Atul P. Godse, 2008. • Microprocessor & Microcontroller. Technical Publications. p.684.S. K. Sen, 2006. • Understanding 8085 Microprocessor and Peripheral ICs through Problems and Solutions. New Age Publications. p.175.

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Self Assessment

Each machine cycle consists of many clock periods or cycles called___________.1. T-statesa. M-statesb. P-statesc. Z-statesd.

The ___________isanareaofmemoryidentifiedbytheprogrammerfortemporarystorageofinformation.2. flipflopa. stackb. subroutinec. interruptd.

A ___________ is a group of instructions that will be used repeatedly in different locations of the program.3. flipflopa. stackb. subroutinec. interruptd.

The 14. st machine cycle (M1) of every instruction cycle is the ___________ fetch cycleoperanda. tri-stateb. interruptc. op-coded.

The ___________ instruction is used to redirect program execution to the subroutine.5. CALLa. RETb. PUSHc. POPd.

Which of the following instruction is used to return the execution to the calling routine?6. CALLa. RETb. PUSHc. POPd.

State which of the following statements is true.7. Each instruction cycle is composed of many clock cyclesa. Each machine cycle is composed of many instruction cyclesb. Each machine cycle is composed of many clock cyclesc. Each machine cycle is composed of many fetch cycles.d.

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State which of the following statements is false.8. The 1st step in communicating between the microprocessor and memory is reading from the memorya. Forfetchingabyte,themicroprocessormustfindoutthememorylocationwhereitisstoredb. ThetimetakentoreadorwriteforanyinstructionmustbeknownintermsoftheμPclockc. The 1st machine cycle (M1) of every instruction cycle is the read cycle.d.

Timing diagram is the display of initiation of read/write and transfer of data operations under the control of 9. which of the following 3-status signals?

IO/M, S1, and S0a. AD0-AD7, S1, and S0b. IO, S1, and S0c. INTR, S1, and S0d.

The 8085 provides which two instructions for storing information on the stack and retrieving it back?10. SET and RESETa. PUSH and POPb. CALL and RETc. INTA and INTRd.

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Chapter V

Interfacing with 8085 Microprocessor

Aim


explain different interfacing types•

elucidate various peripheral devices•

explore• the architecture of 8086 microprocessor

Objectives


classify types of communication interface•

explain the 8085 interrupt system•

elucidate the addressing modes of 8086 microprocessor•

Learning outcome


understand 8255 – parallel communication interface •

explain 8257 – DMA controller•

recall 8259 – programmable interrupt controller•

identify the architecture and pin diagram of 8086 microprocessor•

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5.1 IntroductionA microprocessor is the CPU of a computer. A microprocessor can perform some operation on a data and give the output. But in order to perform the operation, we need an input to enter the data and an output to display the results of the operation. So we are using a keyboard and monitor as Input and output along with the processor. Microprocessors engineering involves a lot of other concepts and we also interface memory elements like ROM, EPROM to access the memory.

5.2 Interfacing TypesThere are two types of interfacing in context of the 8085 processor.

Memory interfacingWhile executing an instruction, there is a necessity for the microprocessor to access memory frequently for •reading various instruction codes and data stored in the memory. The interfacing circuit aids in accessing the memory.Memory requires some signals to read from and write to registers. Similarly the microprocessor transmits some •signals for reading or writing a data.The interfacing process involves matching the memory requirements with the microprocessor signals. The •interfacing circuit therefore should be designed in such a way that it matches the memory signal requirements with the signals of the microprocessor. For example, for carrying out a READ process, the microprocessor should initiate a read signal which the memory requires to read a data. In simple words, the primary function of a memory interfacing circuit is to aid the microprocessor in reading •and writing a data to the given register of a memory chip.

I/O interfacingKeyboard and displays are used as communication channel with outside world. So it is necessary that we interface •keyboard and displays with the microprocessor. This is called I/O interfacing. In this type of interfacing we use latches and buffers for interfacing the keyboards and displays with the •microprocessor.But the main disadvantage with this interfacing is that the microprocessor can perform only one function. It •functions as an input device if it is connected to buffer and as an output device if it is connected to latch. Thus , the capability is very limited in this type of interfacing.

5.3 Programmable Peripheral DevicesProgrammable peripheral devices were introduced by Intel to increase the overall performance of the system. These devices, along with I/O functions, perform various other functions such as time delays, counters and interrupt handling. These are nothing but a combination of many devices on a single chip. A programmable device can be set uptoperformspecificfunctionbywritingacodeintheinternalregister.Asthiscodecontrolsthefunctionofthedevice, it’s called control word and internal register in which it is stored is called control register.

INTEL developed some peripheral devices for processors like 8085/8086/8088. The peripheral devices includes:8255 – Parallel Communication Interface (PPI)•8251 – Serial Communication Interface (USART- Universal Synchronous/Asynchronous Receiver/•Transmitter)8257 – DMA Controller•8259 – Programmable Interrupt Controller•

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5.4 Types of Communication InterfaceThere are two ways in which a microprocessor can connect with outside world or other memory systems:

Serial communication interface• : In this, the interface gets a single byte of data from the microprocessor and sends it bit by bit to other system serially (or) the interface receives data bit by bit serially from the external systems and converts the data into a single byte and transfers it to the microprocessor.Parallel communication interface: • This interface gets a byte of data from microprocessor and sends it bit by bit to the other systems in simultaneous (or) parallel fashion. The interface also receives data bit by bit simultaneously from the external system and converts the data into a single byte and transfers it to microprocessor.

5.5 8085 Interrupt SystemThe8085chiphasfiveinterruptpins,namely,TRAP,RST7.5,RST6.5,RST5.5,andINTR.IfthesignalsontheseinterruptpinsgotoHIGHsimultaneously,thenTRAPwillbeservicedfirstfollowedbyRST7.5,RST6.5,RST5.5 and INTR. Note that once an interrupt is serviced, all the interrupts except TRAP are disabled. They can also be enabled or disabled simultaneously by executing the EI or DI instruction respectively. The 8085 interrupts are as follows:

TRAP:• TRAP is a non-maskable interrupt. That is, it cannot be enabled or disabled by an instruction. In order for the 8085 to service this interrupt, the signal on the TRAP pin must have a sustained HIGH level with a low to high transition. If this condition occurs, then the 8085 complete execution of the current instruction pushes the program counter onto the stack, and branches to location 0024 (interrupt address vector for the TRAP). Note that the TRAP interrupt is cleared by the falling edge of the signal on the pin.RST7.5: • RST7.5 is a maskable interrupt. This means that it can be enabled or disabled using the SIM or EI/DI instruction. The 8085 responds to the RST 7.5 interrupt when the signal on the RST 7.5 pin has a low to high transition. In order to service RST 7.5, the 8085 completes execution of the current instruction, pushes the program counter onto the stack, and branches to 003C16. The 8085 remember the RST 7.5 interrupt by setting aninternalDflipflopbytheleadingedge.RST 6.5:• RST 6.5 is a maskable interrupt. It can be enabled or disabled using the SIM or EI/DI instruction. RST 6.5 is HIGH level sensitive. In order to service this interrupt the 8085 completes execution of the current instruction, saves the program counter onto the stack, and branches to location 003416.

RST 5.5: • RST 5.5 is a maskable interrupt. It can be enabled or disabled using the SIM or EI/DI instruction. RST 6.5 is HIGH level sensitive. In order to service this interrupt the 8085 completes execution of the current instruction, saves the program counter onto the stack, and branches to location 002C16.INTR: • INTR is a maskable interrupt. It can be enabled or disabled using the SIM or EI/DI instruction. This is also called the handshake interrupt. INTR is HIGH level sensitive. When no other interrupts are active and the signal on the INTR pin is HIGH, the 8085 completes execution of the current instruction, and generates an interrupt acknowledge, INTA, LOW pulse on the control bus. The 8085 then expect either a 1 byte CALL or a 3 – byte CALL on the data line. This instruction must be provided by external hardware. In other words, the INTA can be used to enable tri-state buffer. The output of this buffer can be connected to the 8085 data lines. The buffer can be designed to provide the appropriate op code on the data lines. Note that the occurrence of INTA turns off the 8085 interrupt system in order to avoid multiple interrupts from a single device. Also note that there are eight RST instructions. Each of these RST instructions has a vector address.

5.6 8257 or 8237A (DMA Controller)The Intel 8257 DMA controller chip is a 40 pin DIP and is programmable.•It is compatible with the 8085 microprocessor.•The 8257 is a four channel DMA controller with priority logic built into the chip. This means that the 8257 •provide for DMA transfers for a maximum of up to devices via the DMA request lines DRQ0 to DRQ3.Associated with each DRQ is a DMA acknowledge. Note that the DACK signals are active LOW.•The 8257 uses the 8085 HOLD pin in order to take over the system bus. After initialising the 8257 by the 8085, •

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the8257 perform the DMA operation in order to transfer a block of data of up to 16,384 bytes between the memory and a peripheral without involving the microprocessor.Atypical8085–8257isshowninthefig5.1AnI/Odevicewhenenabledbythe8085,canrequestaDMA•transfer by raising the DMA request (DRQ) line of one of the channels of the 8257.In response, the 8257 will send a HOLD request (HOLD) to the 8085. The 8257 waits for the HOLD Acknowledge •(HLDA) from the 8085.On receipt of HLDA from the 8085, the 8257 generates a LOW on the DACK lines for the I/O devices.•Note that DACK is used as a chip select bit for the I/O device. The 8257 sends the READ or WRITE control •signals and data are transferred between the I/O and memory. On completion of the data transfer, the DACK0 is set to HIGH, and the HRQ line is reset to LOW in order to transfer control of the bus to the 8085.The 8257 utilizes four clock cycles in order to transfer 8 bits of data.•

Fig. 5.1 An 8085 – 8257 interface

The 8257 has three main registers. These are a 16 bit DMA address register, a terminal count register and a •status register.Both address and terminal count registers must be initialised before DMA operation. The DMA address register •is initialised with the starting address of the memory to be written into or read from.The low order 14 bits of the terminal count register are initialised with the value (n-1), where n is the desired •number of DMA cycles.A terminal count (TC) pin on the 8257 is set to HIGH in order to indicate to the peripheral device that the present •DMA cycle is the last cycle.An 8-bit status register in the 8257is used to indicate which channels have attained a terminal count.•

5.7 The 8255A Programmable Peripheral InterfaceThe 8255A is a widely used, programmable, parallel I/O device.•It can be programmed to transfer data under various conditions, from simple I/O interrupt I/O.•

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Itisflexible,versatile,andeconomical(whenmultipleI/Oportsarerequired),butsomewhatcomplex.•It is an important general-purpose I/O device that can be used with almost any microprocessor.•

Fig. 5.2 8255A I/O Ports

The 8255A has 24 I/O pins that can be grouped primarily in two 8-bit parallel ports: A and B, with the remaining •eight bits as port C.The eight bits of port C can be used as individual bits or be grouped in two 4-bit ports: CUPPER (CU) and •CLOWER(CL),asintofig.5.2.Thefunctionoftheseportsisdefinedbywritingacontrolwordinthecontrolregister.•Allthefunctionsofthe8255A,classifiedaccordingtotwomodes:theBitSet/Reset(BSR)modeandtheI/O•mode.The BSR mode is used to set or reset the bits in port C. The I/O mode is further divided into three modes 0.Mode •1, and mode 2. In Mode 0, all port function as simple I/O ports.Mode 1 is a handshake mode whereby ports A and/or B use bits from port C as handshake signals.•In the handshake mode, two type of I/O data transfer can be implemented: status check and interrupt.•In Mode 2,port A can be set up for bi-directional data transfer using handshake signal from port C, and port B •can be set up either in mode 0 or mode 1.

5.7.1 Block Diagram of the 8255ATheblockdiagraminfig5.3showstwo8-bitport(AandB),two4-bitports(CUandCL),andthedatabusbuffer,and control logic. This block diagram includes all the elements of a programmable device: port C performs function similar to that of the status register in addition to providing handshake signal.

Control logic: • The control logic has six lines. Their functions to providing handshake signal RD (Read): This control signal enables the read operation. When the signal is low the MPU reads data from a selected I/O port of 8255A.WR (Write):• This control signal enables the write operation. When the signal is low the MPU writes in to a selected I/O port of control register.RESET (Reset):• This is an active high signal; it clears the controls register and sets all port in the input modes.CS, A0, and A1• : These are device select signals. CS is connected to a decoded address and A0 and A1 are generally connected to MPU address lines A0 and A1, respectively.BSR (Bit Set/Reset) Mode: • The BSR modes is concerned only with the eight bits of port C, which can be set

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or rest by writing an appropriate control word in the control register. A control word with bit D7=0 is recognised as a BSR control word, and it does not alter any previously transmitted control word with bit D7=1: thus the I/O operation of ports A and B are not affected by a BSR control word. In the BSR mode, individual bits of port c can be used for application such as an on/off switch.

Fig. 5.3 Block diagram of the 8255A

5.8 The 8259A-Programmable Interrupt Controller It is programmed to work with either 8085 or 8086 processor.•It manages 8-interrupts according to the instructions written into its control registers.•In 8086 processor, it supplies the type number of the interrupt and the type number is programmable. In 8085 •processor, the interrupt vector address is programmable. The priorities of the interrupts are programmable.The interrupts can be masked or unmasked individually.•The 8259s can be cascaded to accept a maximum of 64 interrupts.•

5.8.1 Functional Block Diagram of 8259It has eight functional blocks:

Control logic1. Read write logic2. Data bus buffer3. Interrupt Request Register (IRR)4. In-Service Register (ISR)5. Interrupt Mask Register (IMR)6.

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Priority Resolver (PR)7. Cascade buffer8.

The data bus and its buffer are used for the following activities:The processor sends control word to data bus buffer through D0-D7.•The processor read status word from data bus buffer through D0-D7•From the data bus buffer, the 8259 send type number (in case of 8086) or the call opcode and address (in case •of 8085) through D0-D7 to the processor.

Fig. 5.4 Functional block diagram of 8259

The processor uses the RD (low), WR (low) and A0 to read or write 8259.•The 8259 is selected by CS (low).•The IRR has eight input lines (IR0-IR7) for interrupts. When these lines go high, the request is stored in IRR. •It registers a request only if the interrupt is unmasked.Normally IR0 has highest priority and IR7 has the lowest priority. The priorities of the interrupt request input •are also programmable.First the 8259 should be programmed by sending Initialisation Command Word (ICW) and Operational Command •Word (OCW). These command words will inform 8259 about the following,

Type of interrupt signal (Level triggered / Edge triggered) �Type of processor (8085/8086) �Call address and its interval (4 or 8) �Masking of interrupts �Priority of interrupts �Type of end of interrupts �

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The Interrupt Mask Register (IMR) stores the masking bits of the interrupt lines to be masked. The relevant •information is send by the processor through OCW.The in-service register keeps track of which interrupt is currently being serviced.•The priority resolver examines the interrupt request, mask and in-service registers and determines whether INT •signal should be sent to the processor or not.The cascade buffer/comparator is used to expand the interrupts of 8259.•In cascade connection, one 8259 will be directly interrupting 8086 and it is called master 8259.•To each interrupt request input of master 8259 (IR0-IR7), one slave 8259 can be connected. The 8259s interrupting •the master 8259 are called slave 8259s.Each 8259 has its own addresses so that each 8259 can be programmed independently by sending command •words and independently the status bytes can be read from it.

5.8.2 Interfacing 8259 with 8085 Microprocessor

Fig. 5.5 Interfacing 8259 with 8085 microprocessor(Source: http://www.8085projects.info/Interfacing-of-PIC-8259-with-8085.html)

It requires two internal address and they are A =0 or A = 1.•ItcanbeeithermemorymappedorI/Omappedinthesystem.Theinterfacingof8259to8085isshowninfig•5.5 is I/O mapped in the system.The low order data bus lines D• 0-D7 are connected to D0-D7 of 8259.The address line A• 0 of the 8085 processor is connected to A0 of 8259 to provide the internal address.The 8259 require one chip select signal. Using 3-to-8 decoder generates the chip select signal for 8259.•The address lines A• 4, A5 and A6 are used as input to decoder.The control signal IO/M (low) is used as logic high enables for decoder and the address line A• 7 is used as logic low enable for decoder.The I/O addresses of 8259 are shown in table.•

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Binary Address

Hex addressDecoder Input/ Enable

Input to addressPin of 8259

A7 A6 A5 A4 A3 A2 A1 A0

For A0 of 8259 to be zero 0 0 0 0 X X X 0 00

For A0 of 8259 to be one 0 0 0 0 X X X 1 01

Table 5.1 I/O addresses of 8259

Working of 8259 with 8085 processorFirst the 8259 should be programmed by sending Initialisation Command Word (ICW) and Operational Command •Word (OCW). These command words will inform 8259 about the following,

Type of interrupt signal (Level triggered / Edge triggered) �Type of processor (8085/8086) �Call address and its interval (4 or 8) �Masking of interrupts �Priority of interrupts �Type of end of interrupts �

Once 8259 is programmed it is ready for accepting interrupt signal. When it receives an interrupt through any •one of the interrupt lines IR0-IR7 it checks for its priority and also checks whether it is masked or not.If the previous interrupt is completed and if the current request has highest priority and unmasked, then it is •serviced.For servicing this interrupt, the 8259 will send INT signal to INTR pin of 8085.•In response, it expects an acknowledge INTA (low) from the processor.•When the processor accepts the interrupt, it sends three INTA (low) one by one.•Inresponsetofirst,secondandthirdINTA(low)signals,the8259willsupplyCALLopcode,lowbyteofcall•address and high byte of call address respectively. Once the processor receives the call opcode and its address, it saves the content of program counter (PC) in stack and loads the CALL address in PC and start executing the interrupt service routine stored in this call address.

5.9 8251A (USART)The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous •serial data communication.It is packed in a 28 pin DIP.•It supports the serial transmission of data.•

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5.9.1 Functional Block Diagram of 8251A

Fig. 5.6 Functional block diagram of 8251A(Source: http://www.8085projects.info/INTEL-8251A-%28USART%29.html)

Thefunctionalblockdiagramof8251Aconsistsfivesectionsasfollows:1. Read/Write control logic

The Read/Write Control logic interfaces the 8251A with CPU; it determines the functions of the 8251A according •tothecontrolwordwrittenintoitscontrolregister.Itmonitorsthedataflow.This section has three registers and they are control register, status register and data buffer.•The active low signals RD, WR, CS and C/D (Low) are used for read/write operations with these three •registers.When C/D (low) is high, the control register is selected for writing control word or reading status word.•When C/D (low) is low, the data buffer is selected for read/write operation.•When the reset is high, it forces 8251A into the idle mode.•The clock input is necessary for 8251A for communication with CPU and this clock does not control either the •serial transmission or the reception rate.

2. Transmitter sectionThe transmitter section accepts parallel data from CPU and converts them into serial data.•The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another •register called output register to convert the parallel data into serial bits.When output register is empty, the data is transferred from buffer to output register. Now the processor can •again load another data in buffer register.If buffer register is empty, then TxRDY is goes to high.•If output register is empty then TxEMPTY goes to high.•The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART.•The clock frequency can be 1, 16 or 64 times the baud rate.•

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3. Receiver sectionThe receiver section accepts serial data and convert them into parallel data•The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, •and a buffer register to hold the parallel data.When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples •the line again.If the line is still low, then the input register accepts the following bits, forms a character and loads it into the •buffer register.The CPU reads the parallel data from the buffer register.•When the input register loads a parallel data to buffer register, the RxRDY line goes high.•The clock signal RxC (low) controls the rate at which bits are received by the USART.•During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.•During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous •character.

4. Data bus bufferThis 3-state bidirectional, 8-bit buffer is used to interface the 8251A to the system data bus. Data is transmitted •and received by the buffer upon the execution of IN and OUT instructions of the CPU. Control words, command words and status information are also transferred through the data bus buffer.•

5. MODEM controlThe MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through •MODEM over telephone lines.This unit takes care of handshake signals for MODEM interface.•

5.9.2 Interfacing 8251A with 8085 Microprocessor

The 8251A can be either memory mapped or I/O mapped in the system.•8251AinI/Omappedinthesystemisshowninthefig.5.7.•Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.•The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0 to IOCS-7) and in •this, the chip select signal IOCS-2 is used to select 8251A.The address line A7 and the control signal IO / M (low) are used as enable for decoder.•The address line A0 of 8085 is connected to C/D (low) of 8251A to provide the internal addresses. The data •lines D0 - D7 are connected to D0 - D7 of the processor to achieve parallel data transfer.The RESET and clock signals are supplied by the processor. Here the processor clock is directly connected to •8251A. This clock controls the parallel data transfer between the processor and 8251A.The output clock signal of 8085 is divided by suitable clock dividers like programmable timer 8254 and then •used as clock for serial transmission and reception.The TTL logic levels of the serial data lines and the control signals necessary for serial transmission and •reception are converted to RS232 logic levels using MAX232 and then terminated on a standard 9-pin D-.type connector.In 8251A the transmission and reception baud rates can be different or same•

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Fig. 5.7 Interfacing 8251A with 8085 microprocessor(Source: http://www.8085projects.info/Interfacing-of-INTEL-8251A-%28USART%29.html)

The device which requires serial communication with processor can be connected to this 9-pin D-type connector •using 9-core cable.The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to initiate interrupt driven data •transfer scheme between processor and 8251 A.I/O addresses of 8251A interfaced to 8085 is as given below.•

Internal Device of 8251A

Binary Address

Hex addressDecoder Input/ Enable Input to addressPin of 8251

A7 A6 A5 A4 A3 A2 A1 A0

Data Buffer 0 0 1 0 X X X 0 20

Control register 0 0 1 0 X X X 1 21

Table 5.2 I/O addresses of 8251A

5.10 8085 SID and SOD LineSerial I/O is extensively used for data transfer between a peripheral device and the microprocessor. Since microprocessors perform internal operations in parallel, conversion of data from parallel to serial and vice versa is required to provide communication between the microprocessor and the serial I/O. The 8085 provide serial I/O capabilities via SID (Serial Input Data) and SOD (Serial Output Data) lines.

One can transfer data to or from the SID or SOD lines using the instruction RIM and SIM. After executing the RIM instruction, the bits in the accumulator are interpreted as follows:

Serial input bit is bit 7 of the accumulator.•Bits 0 to 6 are interrupt masks, the interrupt enable bit, and pending interrupts.•

The SIM instruction sends the contents of the accumulator to the interrupt mask register and serial output line. Therefore, before executing the SIM, the accumulator must be loaded with proper data. The contents of the

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accumulator are interpreted as follows:Bit 7 of the accumulator is the serial output bit.•The SOD enable bit is bit 6 of the accumulator. This bit must be 1 in order to output bit 7 of the accumulator •to the SOD lines.Bits 0 to 5 are interrupt masks, enables and resets.•

5.11 16 Bit Processor 8086Itisa16-bitmicroprocessor(μp).It’sALU,internalregistersworkswith16bitbinaryword.•8086 has a 20 bit address bus that can access up to 220 = 1 MB memory locations.•8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits or 8 bit at a time.•It can support up to 64K I/O ports.•It provides 14, 16 -bit registers.•Frequency range of 8086 is 6-10 MHz•It has multiplexed address and data bus AD• 0- AD15 and A16 – A19.It requires single phase clock with 33% duty cycle to provide internal timing.•It can prefetch upto 6 instruction bytes from memory and queues them in order to speed up instruction •execution.It has a 40 pin dual in line package.•It requires +5V power supply•8086 is designed to operate in two modes, minimum mode and maximum mode.•

The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single microprocessor �configuration.The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi micro �processorsconfiguration.

5.11.1PinConfigurationof8086

Fig.5.8Pinconfigurationof8086(Source: http://www.8085projects.info/page/8085-interfacing-techniques.aspx)

The microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP •or plastic package.

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The8086operatesinsingleprocessorormultiprocessorconfigurationtoachievehighperformance.Thepins•serve a particular function in minimum mode (single processor mode) and other function in maximum mode configuration(multiprocessormode).The 8086 signals can be categorised in three groups.•

Thefirstarethesignalhavingcommonfunctionsinminimumaswellasmaximummode. �The second are the signals which have special functions for minimum mode �The third are the signals having special functions for maximum mode. �

The following signal descriptions are common for both modes.•

AD15-AD0 These are the time multiplexed memory I/O address and data lines. Address remains on the lines during T1 state, whilethedataisavailableonthedatabusduringT2,T3,TwandT4.TheselinesareactiveHIGHandfloattoatristate during interrupt acknowledge and local bus hold acknowledge cycles.

A19/S6, A18/S5, A17/S4, A16/S3 These are the time multiplexed address and status lines. During T1,thesearethemostsignificantaddresslinesformemory operations. During I/O operations, these lines are low. During memory or I/O operations, status information is available on those lines for T2, T3, Tw and T4.

Thestatusoftheinterruptenableflagbitisupdatedatthebeginningofeachclockcycle.TheS4 and S3 together indicate which segment registers is presently being used for memory accesses as stated in the table below. These linesfloattotri-stateoffduringthelocalbusholdacknowledge.ThestatuslineS6 is always low. The address bits are separated from the status bit using latches controlled by the ALE signal.

S4 S3 Indication0 0 Alternate Data0 1 Stack1 0 Code or Name1 1 Data0 0 Whole word0 1 Upper byte from or to even address1 0 Lower byte from or to even address

Table 5.3 Status of S4 and S3

BHE/S7The bus high enable is used to indicate the transfer of data over the higher order (D15-D8) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristated during hold. It is low during T1forthefirstpulseoftheinterruptacknowledgescycle.

RD – ReadThis signal on low indicates the peripheral that the processor is performing memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge.

READYThis is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronised by the 8284A clock generator to provide ready input to the 8086. The signal is active high.

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INTR-Interrupt RequestThis is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This signal is active high and internally synchronised.

TESTThis input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronised internally during each clock cycle on leading edge of clock.

CLK- Clock InputThe clock input provides the basic timing for processor operation and bus control activity. It’s an asymmetric square wave with 33% duty cycle.

The following pin functions are for the minimum mode operation of 8086:

M/IO – Memory/IOThis is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes activehighinthepreviousT4andremainsactivetillfinalT4ofthecurrentcycle.Itistristatedduringlocalbus'hold acknowledge '.

INTA – Interrupt AcknowledgeThis signal is used as a read strobe for interrupt acknowledge cycles. i.e., when it goes low, the processor has accepted the interrupt.

ALE – Address Latch EnableThis output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated.

DT/R – Data Transmit/ReceiveThisoutputisusedtodecidethedirectionofdataflowthroughthetransreceivers(bidirectionalbuffers).Whentheprocessor sends out data, this signal is high and when the processor is receiving data, this signal is low.

DEN – Data EnableThis signal indicates the availability of valid data over the address/data lines. It is used to enable the transreceivers (bidirectional buffers) to separate the data from the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is tristated during ‘hold acknowledge’ cycle.

HOLD, HLDA – AcknowledgeWhen the HOLD line goes high, it indicates to the processor that another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle.

Atthesametime,theprocessorfloatsthelocalbusandcontrollines.WhentheprocessordetectstheHOLDlinelow, it lowers the HLDA signal. HOLD is an asynchronous input, and is should be externally synchronised. If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release the local bus during T4 provided

The request occurs on or before T2 state of the current cycle.•The current cycle is not operating over the lower byte of a word.•Thecurrentcycleisnotthefirstacknowledgeofaninterruptacknowledgesequence.•

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A Lock instruction is not being executed.•

The following pin functions are applicable for maximum mode operation of 8086.

S2, S1, S0 – Status LinesThesearethestatuslineswhichreflectthetypeofoperation,beingcarriedoutbytheprocessor.Thesebecomeactivity during T4 of the previous cycle and active during T1 and T2 of the current bus cycles.

LOCKThis output pin indicates that other system bus master will be prevented from gaining the system bus, while the LOCK signalislow.TheLOCKsignalisactivatedbytheLOCKprefixinstructionandremainsactiveuntilthecompletionof the next instruction. When the CPU is executing a critical instruction, which requires the system bus, the LOCK prefixinstructionensuresthatotherprocessorsconnectedinthesystemwillnotgainthecontrolofthebus.

The8086,whileexecutingtheprefixedinstruction,assertsthebuslocksignaloutput,whichmaybeconnectedtoanexternal bus controller. By pre-fetching the instruction, there is a considerable speeding up in instruction execution in 8086. This is known as instruction pipe lining.

S2 S1 S0 Indication0 0 0 Interrupt Acknowledge0 0 1 read I/O port0 1 0 Write I/O port0 1 1 Halt1 0 0 Code Access1 0 1 Read Memory1 1 0 Write Memory

1 1 1 Passive

Table 5.4 status of S0, S1 and S2

At the starting the CS:IP is loaded with the required address from which the execution is to be started. Initially, the queuewillbeemptyanthemicroprocessorstartsafetchoperationtobringonebyte(thefirstbyte)ofinstructioncode, if the CS:IP address is odd or two bytes at a time, if the CS:IP address is even.

Thefirstbyteisacompleteopcodeincaseoffewinstruction(onebyteopcodeinstruction)andisapartofopcode,in case of few instructions (two byte opcode instructions), the remaining part of code lie in second byte.

Thesecondbyteisthendecodedincontinuationwiththefirstbytetodecidetheinstructionlengthandthenumberofsubsequent bytes to be treated as instruction data. The queue is updated after every byte is read from the queue but the fetch cycle is initiated by BIU only if at least two bytes of the queue are empty and the EU may be concurrently executing the fetched instructions.

Thenextbyteafter theinstructioniscompletedisagainthefirstopcodebyteof thenext instruction.Asimilarprocedure is repeated till the complete execution of the program. The fetch operation of the next instruction is overlapped with the execution of the current instruction. As in the architecture, there are two separate units, namely Execution unit and Bus interface unit.

While the execution unit is busy in executing an instruction, after it is completely decoded, the bus interface unit may be fetching the bytes of the next instruction from memory, depending upon the queue status.

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QS1 QS0 Status

0 0 No operation

0 1 First byte of the opcode from the queue

1 0 Empty queue

1 1 Subsequent byte from the queue

Table 5.5 Status of QS1 and QS0

RQ/GT0, RQ/GT1 – Request/GrantThese pins are used by the other local bus master in maximum mode, to force the processor to release the local bus at the end of the processor current bus cycle.Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT pins have internal pull-up resistors and may be left unconnected. Request/Grant sequence is as follows:

A pulse of one clock wide from another bus master requests the bus access to 8086.•During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the requesting master, indicates •thatthe8086hasallowedthelocalbustofloatandthatitwillenterthe‘holdacknowledge’stateatnextcycle.The CPU bus interface unit is likely to be disconnected from the local bus of the system.A one clock wide pulse from the master indicates to the 8086 that the hold request is about to end and the 8086 •may regain control of the local bus at the next clock cycle. Thus, each master to master exchange of the local bus is a sequence of 3 pulses. There must be at least one dead clock cycle after each bus exchange. The request and grant pulses are active •low. For the bus request those are received while 8086 is performing memory or I/O cycle, the granting of the bus is governed by the rules as in case of HOLD and HLDA in minimum mode.

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5.11.2 Functional Block Diagram of 8086

Fig. 5.9 Functional block diagram of 8086(Source: http://www.8085projects.info/page/8085-interfacing-techniques.aspx)

8086 has two blocks Bus Interfacing Unit (BIU) and Execution Unit (EU).•The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory �and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue.EU executes instructions from the instruction system byte queue. �

Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism •whichiscalledasPipelining.Thisresultsinefficientuseofthesystembusandsystemperformance.BIU contains Instruction queue, Segment registers, Instruction pointer, and Address adder.•EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.•

Bus interface unitIt provides a full 16 bit bidirectional data bus and 20 bit address bus.•The bus interface unit is responsible for performing all external bus operations.•Specificallyitperformsfollowingfunctions:Instructionfetch,Instructionqueuing,Operandfetchandstorage,•Address relocation and Bus control.The BIU uses a mechanism known as an instruction stream queue to implement pipeline architecture.•This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it •has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction.These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction •bytes in a single memory cycle.After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty •location nearest the output.The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of •the queue. If the queue is full and the EU is not requesting access to operand in memory.These intervals of no bus activity, which may occur between bus cycles, are known as idle state.•

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If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands •frommemoryorI/O,theBIUfirstcompletestheinstructionfetchbuscyclebeforeinitiatingtheoperandread/write cycle.The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the •address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address. For example: The physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O •read or write.

Execution unitThe execution unit is responsible for decoding and executing all instructions.•The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, •passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform theoperationspecifiedbytheinstructionontheoperands.Duringtheexecutionoftheinstruction,theEUteststhestatusandcontrolflagsandupdatesthembasedonthe•results of executing the instruction.If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue.•When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another •set of sequential instructions.Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this •newlocationtorefillthequeue.

5.11.3 Min/Max Mode of 8086MN/MX

Minimum mode:• In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1. All control signals for memory and I/O are generated by the microprocessor itself.Maximum mode:• It is designed to be used when a coprocessor exists in the system. 8086 works in a multiprocessor environment. Control signals for memory and I/O are generated by an external BUS Controller.

5.11.4 Addressing Modes of 8086

An instruction acts on any number of operands. The way an instruction accesses its operands is called its •Addressing modes.Operands may be of three types:•

Implicit �Explicit �Both Implicit and Explicit �

Implicitoperandsmeanthattheinstructionbydefinitionhassomespecificoperands.TheprogrammersdoNOT•select these operandsExplicitoperandsmeantheinstructionoperatesontheoperandsspecifiedbytheprogrammer.•Theaddressingmodesof8086canbeclassifiedintofourgroups:•

Immediate addressing �Register addressing �Memory addressing �I/O port addressing �

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Immediate addressingIn this addressing mode, the operand is stored as part of the instruction. The immediate operand, which is stored along with the instruction, resides in the code segment -- not in the data segment. This addressing mode is also faster to execute an instruction because the operand is read with the instruction from memory.

ExampleMOV AL, 30; move the constant 30 into register ALADD AX, 5; add constant 5 to register EAXMOV DX, offset msg; move the address of message to register DX

Register addressingIn this addressing mode, the operands may be:

reg16: 16-bit general registers: AX, BX, CX, DX, SI, DI, SP or BP.•reg8: 8-bit general registers: AH, BH, CH, DH, AL, BL, CL, or DL.•Sreg: segment registers: CS, DS, ES, or SS. There is an exception: CS cannot be a destination.•

For register addressing modes, there is no need to compute the effective address. The operand is in a register and to get the operand there is no memory access involved.

Some rules in register addressing modes:You may not specify CS as the destination operand.•

Example: mov CS, 02h –> wrong

Only one of the operands can be a segment register. You cannot move data from one segment register to another •with a single mov instruction. To copy the value of cs to ds, you would have to use some sequence like:

Examplemov ds,cs -> wrongmov ax, csmov ds, ax -> the way we do it

You should never use the segment registers as data registers to hold arbitrary values. They should only contain segment addresses.

Memory addressingMemory (RAM) is the main component of a computer to store temporary data and machine instructions. In a program, programmers many times need to read from and write into memory locations.

There are different forms of memory addressing modesDirect Addressing•Register indirect addressing•Based addressing•Indexed addressing•Based indexed with displacement•

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SummaryThe interfacing process involves matching the memory requirements with the microprocessor signals.•The interfacing circuit therefore should be designed in such a way that it matches the memory signal requirements •with the signals of the microprocessor.Programmable peripheral devices were introduced by Intel to increase the overall performance of the system.•In serial communication interface, the interface gets a single byte of data from the microprocessor and sends it •bit by bit to other system serially.In parallel communication interface gets a byte of data from microprocessor and sends it bit by bit to the other •systems in simultaneous (or) parallel fashion.The8085chiphasfiveinterruptpins,namely,TRAP,RST7.5,RST6.5,RST5.5,andINTR.•The Intel 8257 DMA controller chip is a 40 pin DIP and is programmable.•The 8255A is a widely used, programmable, parallel I/O device.•The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous •serial data communication.Serial I/O is extensively used for data transfer between a peripheral device and the microprocessor.•8086isa16-bitMicroprocessor(μp).It’sALU,internalregistersworkswith16bitbinaryword.•8086 has two blocks Bus Interfacing Unit (BIU) and Execution Unit (EU).•The BIU uses a mechanism known as an instruction stream queue to implement pipeline architecture.•The Execution unit is responsible for decoding and executing all instructions.•An instruction acts on any number of operands. The way an instruction accesses its operands is called its •Addressing modes.

References8085 Interfacing Techniques. Available at: <http://www.8085projects.info/page/8085-interfacing-techniques.•aspx> [Accessed on 24th February, 2011].N. K. Srinath.8085 Microprocessor: Programming and Interfacing. PHI Learning Pvt. Ltd., 2005.327 pages.•http://www.brighthub.com/engineering/electrical/articles/53885.aspx•

Recommended ReadingKenneth Ayala, 1995. • 8086 Microprocessor: Programming and Interfacing the PC. Delmar Cengage Learning, 1st edition. p.698.MohamedRafiquzzaman,1995.• Microprocessors and Microcomputer Based System Design. CRC-Press, 2nd edition. p.800.Mrs. Deepali A. Godse, Mr. Atul P. Godse, 2008. • Microprocessor-II. Technical Publications. p.522.

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Self Assessment

The _______________process involves matching the memory requirements with the microprocessor signals.1. interfacinga. acknowledgeb. interruptionc. pipeliningd.

Programmable peripheral devices were introduced by _______________to increase the overall performance 2. of the system.

HPa. Intelb. HCLc. Delld.

The 8257 is a _______________channel DMA controller with priority logic built into the chip.3. twoa. threeb. fourc. fived.

Serial I/O is extensively used for data transfer between a peripheral device and the ___________.4. CPUa. ALUb. I/Oc. microprocessord.

The _______________instruction sends the contents of the accumulator to the interrupt mask register and serial 5. output line.

SIMa. RIMb. OUTc. INd.

State which of the following is true.6. In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its a. MN/MX pin to logic 0.In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its b. MN/MX pin to logic 1.In a maximum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its c. MN/MX pin to logic 1.In a minimum mode 8086 system, the microprocessor 8086 is operated in maximum mode by strapping its d. MN/MX pin to logic 1.

Microprocessor

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State which of the following is true.7. The BSR mode is used to set or reset the bits in port A.a. The BSR mode is used to set or reset the bits in port B.b. The BSR mode is used to set or reset the bits in port C.c. The PSW mode is used to set or reset the bits in port C.d.

Which of the following is also called the handshake interrupt?8. RST 6.5a. INTAb. RESETc. INTR.d.

Which of the following section accepts serial data and convert them into parallel data?9. Receiver a. Transmitterb. Controlc. Arithmetic.d.

Which of the following interface gets a byte of data from microprocessor and sends it bit by bit to the other 10. systems in simultaneous (or) parallel fashion?

Serial Communication Interfacea. Parallel Communication Interfaceb. Peripheral Communication Interfacec. Input/output Interfaced.

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Application I

Digital Gates Emulator using 8085 Microprocessor

This project 'Digital gates Emulator' is used to emulate the basic gates such us NOT, OR, AND. The system has the selector switch by which we can select any gate. The system has two inputs and one output. We use two SPDT switches for the inputs and for the output we use an LED. The gate selection can be done by the selector switch and it is also indicated on separate LED’s. There are three LED’s provided on the board for the gates NOT, OR, AND. The corresponding LED will glow for the corresponding gate. The main operation is done by the Microprocessor through its ports using the PPI (Programmable Peripheral Interface) IC8255. The microprocessor gets the input through the ports and it will produce the output according to the gate selected.

Circuit Diagram

Microprocessor

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Flow chart

Block diagram

QuestionsWhere are digital gates emulator used?1. AnswerDigital gates Emulator' are used to emulate the basic gates such us NOT, OR, AND.

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How are different gates selected in the system?2. AnswerThe system has the selector switch by which one can select any gate. The gate selection can be done by the selector switch and it is also indicated on separate LED’s.

Explain the operation of digital gates emulator3. AnswerThe system has the selector switch by which any gate can be selected. The system has two inputs and one output. Two SPDT switches are used for the inputs and for the output LEDs are used. The corresponding LED will glow for the corresponding gate. The main operation is done by the Microprocessor through its ports using the PPI (Programmable Peripheral Interface) IC8255. The microprocessor gets the input through the ports and it will produce the output according to the gate selected.

Microprocessor

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Application II

Automatic Plant Irrigator

The project presented here waters plants regularly when you are out for vocation. The circuit comprises of sensor partsbuiltusingop-ampICLM324.Op-amp’sareconfiguredhereasacomparator.Twostiffcopperwires(foronesensor) are inserted in the soil to sense the whether the soil is wet or dry. The microprocessor was used to control the whole system. It monitors the sensors through the programmable peripheral interface (PPI) IC 8255. When more than two sensors sense the dry condition, then the microprocessor will switch on the motor and it will switch off the motor when all the sensors goes wet. The microprocessor does the above job by receiving the signals from the sensors through the PPI, and this signals operated under the control of software which is stored in ROM. We are using the 8 bit Microprocessor 8085 and the programmable peripheral interface IC 8255.

Circuit diagram

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Flow chart

Microprocessor

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Block diagram

QuestionsWhat is the use of automatic plant irrigator?1. What is the use of op-amps in the circuit?2. What is the function of microprocessor in this circuit?3.

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Application III

Access Control System

This project of Access Control System is used in the places where we need more security. It can also used to secure lockers and other protective doors. The system comprises a number keypad and the keypads are connected to the 8 bit microprocessor 8085 through the programmable peripheral IC 8255. This is one of the popular microprocessor.The microprocessor continuously monitor the keypad and if somebody enters the password it will check the entered password with the password which was stored in the memory and if it they are same then the microprocessor will switch on the device.

In this project an electrical device is being controlled. The password can be an four digit number. If we enter the correct password then the microprocessor will switch on the load. If we want to switch off the load simply press the digit 0 in the keypad.

Circuit diagram

Microprocessor

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Flow chart

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Block diagram

QuestionsWhere is access control system used?1. What are the different components used in the above system?2. What is the function of microprocessor in the above system?3.

Microprocessor

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Bibliography

References8085 Instruction Set. Available at: <http://ce.sharif.ir/courses/86-87/1/ce126/resources/root/instructionset8085.•pdf> [Accessed on 24th February, 2011].8085 Interfacing Techniques. Available at: <http://www.8085projects.info/page/8085-interfacing-techniques.•aspx> [Accessed on 24th February, 2011].D.A.Godse, A.P.Godse, 2007. • Elements of Microprocessors. Technical Publications. pp 51–52.Dr. Bassel Soudan. Microprocessors & Interfacing. Available at: <http://www.scribd.com/doc/7305870/•Microprocessor-Architecture> [Accessed 19th February, 2011].E. Cortina. • Digital Electronics. Available at: <http://dpnc.unige.ch/tp/elect/doc/07-Digital.pdf> [Accessed on 23rd February, 2011].http://www.brighthub.com/engineering/electrical/articles/53885.aspx•I/O Interfacing with 8085. Available at: <http://www.8085projects.info/IO-Interfacing-Methods.html> [Accessed •19th February, 2011].Mathur. • Microprocessor 8085 and Its Interfacing. PHI Learning Pvt. Ltd. pp40–45.Mohd. Moinul Hoque. Stack and Subroutines. Available at: <http://www.aust.edu/cse/moinul/Stack_and_•Subroutine.pdf > [Accessed on 10th February, 2011].N. K. Srinath.8085 Microprocessor: Programming and Interfacing. PHI Learning Pvt. Ltd., 2005.327 pages.•Number System and Binary Codes. Available at: <http://www.b-u.ac.in/sde_book/bca_fund.pdf> [Accessed on •24th February, 2011].Shankar. How to Interface the 8085 Microprocessor? Available at <http://www.brighthub.com/engineering/•electrical/articles/53885.aspx> [Accessed 19th February, 2011].Timing Diagram 8085. Available at: <http://www.newagepublishers.com/samplechapter/000495.pdf> [Accessed •on 10th February, 2011].Tutorial on Introduction to 8085 Architecture and Programming. Available at: <http://webphysics.davidson.•edu/faculty/dmb/py310/8085.pdf> [Accessed on 24th February, 2011].Unit 1: Number Systems and Binary Codes. Available at: <http://www.b-u.ac.in/sde_book/bca_fund.pdf>. •[Accessed on 23rd, February, 2011].

Recommended ReadingA.P.Godse, D.A.Godse, 2006. • Microprocessors and Applications. Technical Publications, 1st edition. p.738.G.T. Swamy, 2006. • Microprocessor [8085] Lab Manual. Laxmi Publications. p.70.John Uffenbeck, (1999). • Microcomputers and Microprocessors: The 8080, 8085, and Z-80 Programming, Interfacing, and Troubleshooting. Prentice Hall, 3rd edition. p.729.John Uffenbeck, 1999. • Microcomputers and Microprocessors: The 8080, 8085, and Z-80 Programming, Interfacing, and Troubleshooting. Prentice Hall, 3rd edition. p.729.Jr. Charles H. Roth, Larry L Kinney, 2009. • Fundamentals of Logic Design. CL-Engineering; 6th edition. p.758.Kenneth Ayala, 1995. • 8086 Microprocessor: Programming and Interfacing the PC. Delmar Cengage Learning, 1st edition. p.698.MohamedRafiquzzaman,1995.• Microprocessors and Microcomputer Based System Design, CRC-Press, 2nd edition. p.800.MohamedRafiquzzaman,1995.• Microprocessors and Microcomputer Based System Design. CRC-Press, 2nd edition. p.800.

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Mrs. Deepali A. Godse, Mr. Atul P. Godse, 2008. • Microprocessor & Microcontroller. Technical Publications. p.684.Mrs. Deepali A. Godse, Mr. Atul P. Godse, 2008. • Microprocessor-II. Technical Publications. p.522.Ramesh S. Gaonkar, 2004. Microprocessor • Architecture, Programming, and Applications with the 8085. Prentice Hall, 5th edition. p.820.Roger Tokheim. 1994. • Schaum’s Outline of Digital Principles. McGraw-Hill, 3rd edition. p.384.S. K. Sen, 2006. • Understanding 8085 Microprocessor and Peripheral ICs through Problems and Solutions. New Age Publications. p.175.Seymour Lipschutz. 1982. • Schaum’s Outline of Essential Computer Mathematics. McGraw-Hill, 1st edition. p.256.William Routt, 2006. • Microprocessor Architecture, Programming, and Systems Featuring the 8085. Delmar Cengage Learning, 1st edition. p. 288.

Microprocessor

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Self Assessment Answers

Chapter Ia1. b2. c3. d4. a5. b6. c7. d8. a9. b10.

Chapter IIa1. b2. c3. d4. a5. b6. c7. d8. a9. b10.

Chapter IIIa1. b2. c3. d4. a5. b6. c7. d8. a9. b10.

Chapter IVa1. b2. c3. d4. a5. b6. c7. d8. a9. b10.

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Chapter Va1. b2. c3. d4. a5. b6. c7. d8. a9. b10.

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