microsystems laboratory department of electrical & computer engineering
DESCRIPTION
MICROSYSTEMS LABORATORY DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING. Microelectronic Hysteresis. Robert W. Newcomb. Talk for FICAMC: Plovdiv August, 16, 2008 (Fifth International Conference of Applied Mathematics and Computing – Bulgaria’2008). 2. - PowerPoint PPT PresentationTRANSCRIPT
MICROSYSTEMS LABORATORYDEPARTMENT OF ELECTRICAL &
COMPUTER ENGINEERING
Microelectronic Hysteresis Robert W. Newcomb
Talk for FICAMC: Plovdiv August, 16, 2008
(Fifth International Conference of Applied Mathematics and Computing – Bulgaria’2008)
The Old Town of Plovdiv by Ivan Theofilov
• Your ancient floors float among the stars.Blue donkeys graze the silence around.The Roman road leads down along matrimonial chandeliers.A cry out of woman's flesh calls in the clock.Violet-colored philistines go to bed in the deep houses,they hear the pig, the hens, the train, the mouse.The darkness dawns with quick sensual pupils.The bridal veil flies away with the chimney's breath.Blue donkeys run on the moonlit roofs.Saints take off in a cloud from whitewashed churches,with blood-soaked lambs they welcome the bridal veil.Leopards gaze with amber eyes from the doorsteps.Among box trees bacchantes with satin bandspour fragrant myrrh out of bronze rhytons ...
Ivan Theofilov was born in Plovdiv in 1931 and graduated from the Theatre Academy in Sofia. He is an honorary citizen of Plovdiv. The poem translated here is from Geometry of the Spirit, published by Free Poetic Society, Sofia, 1996, and translated by Zdravka Mihaylova
2
Main topic of talkThe mathematics for the design of VLSI CMOS circuits for hysteresis controlled by a voltage or current. Possible uses: Chaotic circuits, robust oscillators, memory,debouncing, pixel holding, emulation of chemical reactions, artificial neural networks,buildings in earth quakes
Items for discussion: Microlectronic hysteresis conceptThe main idea, curve with movable load lineRepresentation via semistate equationsKey circuits usedSome examples
3
The concept for microelectronics Hysteresis (ancient Greek = to lag behind)
a) Static: piecewise multi/single valued [reason Spice won't run DC analysis on hysteresis]along withb) Dynamic: single valued given initial conditions
Typical (static): binary bent
4
Binary hysteresis curves
5
Example of use for holding pixels in presence of noise6
Main Idea
Slide a load line, which depends upon the hysteresis input parameter, across a nonlinearfunction to give two or more intersections inone region.
==>
7
CMOS circuit and bent V-I hysteresisusing inverters
8
CMOS bent hysteresis design curves
9
Designing all CMOS V-I hysteresis
10
CMOS inverter bent hysteresis
11
Hysteresis use in chaos generation
12
Multilevel hysteresis13
Typical binary hysteresis circuitOTA = operational transconductance amplifier
= voltage controlled current source
14
Variable hystereses15
4 quadrant current mode hysteresis
16
Variable hysteresis from last circuit17
Hysteresis in several dimensions
18
From UMCP dissertation of Yu Jiang
Circuit to realize 2D hysteresis 19
Dynamics via Semistate Equations
Edx/dt = A(x) + Bu y = Cx
u = input, y = output, x = semistate B, C, E constant matrices, E may be singular A(x) nonlinear to generate hysteresis
20
Op-amp circuit for hysteresis21
Semistate equations for op-amp example
1xyu12k)x212k(11x0
)2f(xokσ1xoσdt1dx
)invd(v)2
r1r
(1outv
dtds step,unit 1(x) ));d1(v21(
oσs okσoutv
are equations semistate then the2/r1r12k 1(x)),2(-1f(x)
,dv2 x,outv1 x,invulet
22
OTA circuit for hysteresis
23
OTA example semistate equations
2xy)1f(xTI2x0
2x-ug1xgdt
1dx
gsC
are equations semistate theuin vy,2xouti ,1xdWith v
)invdvg(dt)dvd(
gsCouti
)df(vTIouti
24
OTA CMOS circuit25
OTA curves
5 4 3 2 1 0 1 2 3 4 51.1 10 4
8.8 10 5
6.6 10 5
4.4 10 5
2.2 10 5
0
2.2 10 5
4.4 10 5
6.6 10 5
8.8 10 5
1.1 10 4
IT epsI
IT epsI
iOTA vd( )
0
vdmaxvdmin vd
gimax 2IT
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Sliding load line on OTA curve
5 4 3 2 1 0 1 2 3 4 51.1 10 4
8.8 10 5
6.6 10 5
4.4 10 5
2.2 10 5
0
2.2 10 5
4.4 10 5
6.6 10 5
8.8 10 5
1.1 10 4
IT epsI
IT epsI
iOTA vd( )
0
igi go 2 vi2 go( )( ) vd[ ]
igi go vi2 go( ) vd( )
igi go vi2 go( ) vd( )
igi go 2 vi2 go( ) vd( )
vdmaxvdmin vdHysteresis for case of last curves. Uses two curves, upper & lower
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Resulting OTA hysteresis, Iout vs Vin
5 4 3 2 1 0 1 2 3 4 51.1 10 4
8.8 10 5
6.6 10 5
4.4 10 5
2.2 10 5
0
2.2 10 5
4.4 10 5
6.6 10 5
8.8 10 5
1.1 10 4
IT epsI
IT epsI
hu vi go( )
hl vi go( )
vimaxvimin vi
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OTA VLSI layout29
Neural type cell circuit
30
Neural type cell hysteresis31
CMOS resistor from OTA
92,12,1 2)(1
21
KKVVAKIAR
ssadjadj
M9 Vadj
M1
M3 M4
M2V+ V-
M5 M6
M7 M8
Io(IR+) -Io(IR-)M10
M11
Floating resistor; can bepositive or negative (by reversing green Leads to M1 & M2)
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PSpice Simulation: Positive Floating Resistor Circuit
• Observations– Linear I-V region centered at V+ – V- = 0V– IR+ and IR- show good symmetry– Vadj modulates I-V linearity range
IR+
IR-
Vadj=-
2.4v …
-3.4vVadj=-
3.4v …
-2.4v
0.6
0.0
-0.6
-0.3
0.3
0.0 0.75 1.5-0.75-1.5V+ – V- [V]
-6.0 -4.0 -2.0 0.0 2.0 4.0 6.0
V+ – V- [V]
IR+,
IR- [
A
]
IR+,
IR- [
A
]
1.0
0.0
-1.0
-0.5
0.5
magnified
33
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Reference: V. Petrov, M. Peifer, J. Timmer, “Structural Stability Analysis of a Cell Cycle Control Model,” Comptes rendus de l’Academie bulgare des Sciences, Tome 58, No. 1, 2005, pp. 19 – 24.
u)1)(k2k
1(2z
)2σ)(x1σ)x(xok1(1z
0:d(.)/dtfor uz2kx1kdt
dzzokx21σ2)21(3xdt
dx
x
1.3 1.13 0.95 0.78 0.61 0.43 0.26 0.08670.0867 0.26 0.43 0.61 0.78 0.95 1.13 1.31
0.90.80.70.60.50.40.30.20.1
00.10.20.30.40.50.60.70.80.9
10.922
0.922
z1 x( )
0
z2 x 2 u3( )
z2 x u3( )
z2 x u3( )
z2 x 2 u3( )
xmaxxmin x
Plot for σ1=- σ2=1, ko=1=k2=2k1
u3=0.136 at = slopes
Kinetic cells
Circuit to give Iout=(Ix+Iy)2/(2Iw)
Subtract Ix2/(2Iw) &
Iy2/(2Iw)to get
I=IxIy/Iw
Iterate (= cascadeconnections) to getcubic, etc.
W. Gai, H. Chen, E. Seevinck, “Quadratic-translinear CMOS Multiplier divider circuit,” Electronic Letters, May 1997, p. 860
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Configuration to give cubic products
36
NPN differential pair
Apply differential voltage Vd and tail current Io thenIout=I2-I1=Io·tanh(Vd/(2VT)), VT=thermal voltage=KT/Q I2+I1=Io => 2·I2=Io(1+tanh(Vd/2VT)
2·I1=Io(1-tanh(Vd/2VT)
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Multiplier via npn differential pairIout=(I4+I6)-(I3+I5)
=Io·tanh(Vx/2VT)tanh(Vy/2VT)
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Cubic via npn differential pair: Iout=Io·tanh(vx)tanh(vy)tanh(vz)
39
<=from previous=>
<=take diff=>
VLSI Transistors
Two basic types with two complementary of each: MOSFET: NMOS & PMOS [piecewise square law]
BJT: npn & pnp [exponential law]
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NMOS LawFor VGS ≤ Vth ID=0 off
For VGS>Vth
ID=(VGS-Vth)2 if VGS-VthVDS saturation
=(2(VGS-Vth)VDS-VDS2) if VGS-Vth<VDS Ohmic
=(Cox/2)(W/L)
If ≠ 0 multiply by (1+VDS); for now Vth>0
41
Useful CMOS current circuits42
Setting up semistate equationsUse graph theory: vb & ib = branch voltages and currents
vt & il = tree voltages and link (cotree) currents KCL: 0t = Cib KVL: 0l= Tvb
==> vb = CTvt ib = TTil
ib=idevice+isource=id+is ; vb=vd+vs
by equivalences for devices id=Y(vd)
43
Useful equivalences44
Example of setting up equations
T5b
i4b
i3b
i2b
iin
i1biib;bi11010
0110100
Cutset equations = KCL at nodes I and II
45
Device characterization
)V(vI)(vI0
vv
CCCC
s0i
i0101001101
0i
00
vv
v;
)V(vI)vsC(v
0)(vI
0
iiiii
i
dd2S21D12
1in
din
2
1t
dd2S2
21
1D1
5d
4d
3d
2d
1d
d
46
Final semistate equations
tv01outv
ini01
)ddV2(vS2I)1(vD1I0
dttdv
1111
C
47
Idea of an extension
In terms of binary hysteresis canset up a Preisach’s type of theory:
N
1n(u)nhnw
u
ouw(x)dh(x)y(u)
Where h is binary hysteresis and w is a weight
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Alternate CMOS OTA hysteresis
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CMOS OTAVout/Vin hysteresis circuit50
Vout/Vin OTA hysteresis51
VLSI Layout for 1.2U AMI fabrication 526 main transistors10ux10u, cap 38ux32u
Vdd
Gnd
In
OutVr
Vb