microwave monolithic power amplifier designecee.colorado.edu/~ecen5014/chuck-mmic power amplifier...

MICROWAVE MONOLITHIC POWER AMPLIFIERDESIGN

MICROWAVE MONOLITHIC POWER AMPLIFIERDESIGN

Microwave monolithic integrated circuits (MMICs) areused extensively in virtually every commercial and mil-itary microwave system. Monolithic implementations ofmost receiver and transmitter building blocks are com-mercially available, covering a multitude of applicationsand frequency bands. These functions include but are notlimited to mixers, modulators, switches, digital/analog at-tenuators, digital/analog phase shifters, low-noise ampli-fiers (LNAs), driver amplifiers, and power amplifiers (PAs).Many of these MMICs are based on gallium arsenide(GaAs) or indium phosphide (InP) material systems (1–3).However, increasingly, many new monolithic circuit func-tions are being realized with silicon-based technologies, ex-amples of which are silicon germanium (SiGe), metal oxidebased devices Complementary Metal Oxide Semiconduc-tor (CMOS), Laterally Diffused Metal Oxide Semiconduc-tor (LDMOS), and blended technologies (SiGe-BiCMOS)(3, 4). An emerging semiconductor technology for mi-crowave high-power applications is gallium nitride (GaN),which may be epitaxially deposited on silicon carbide(SiC) or silicon substrates (5). These devices have theunique combination of simultaneous high-voltage andhigh-frequency operation, and they are well suited for thenext generation of high-performance power amplifiers.

Power amplifier MMICs are of particular importancein modern microwave systems. It is not uncommon forthe PA MMIC to be the most expensive component in thesystem. It is also not unusual for it to be the componentthat dominates system reliability. For radar and electronicwarfare (EW) applications, these devices are often run atnear-saturated output power levels. For analog and digi-tal communication systems, linear operation is required,and the power amplifier may be run at a high bias current,high supply voltage, and/or output power levels where theefficiency is low. In either case, the PA MMICs are likelythe highest power dissipation and hottest components inthe microwave subsystem driving thermal management re-quirements for the entire system. Clearly, the performanceand reliability of the power amplifier MMICs will have asignificant influence on the operation of the overall system.

Monolithic power amplifiers have some significant ad-vantages over designs constructed from discrete compo-nents. MMIC power amplifiers are usually much smallerand lighter than discrete circuits. There will be less perfor-mance variation unit to unit for the “as-built” circuits or,conversely, less postfabrication tuning and adjustment ofthe amplifiers to achieve a set level of uniformity. Becauseother circuit functions are available in monolithic for-mat, an opportunity exists for higher levels of integrationand complexity for MMIC power amplifiers. Entire trans-mit/receive systems have been successfully integrated onto a single die (6). Additional degrees of freedom are avail-able to the circuit designer. For example, the transistor

cells used in the circuit can be designed for optimum elec-trical and thermal performance. One is not restricted to aparticular set of available transistor cell sizes, as is thecase with a discrete amplifier. For MMIC power ampli-fiers that incorporate multiple gain stages, the impedancelevels between the stages are arbitrary and can be op-timized for bandwidth, gain, and efficiency. Discrete PAcircuits tend to be designed for a fixed real impedance, typ-ically 50 �, such that they can be cascaded. As the operat-ing frequency increases, discrete circuit architectures be-come more difficult to realize. Above 10 GHz, the selectionof high-quality surface mount components used for quasi-lumped element matching becomes limited and distributedcircuit approaches are more common (7). Above 18 GHz,monolithic implementations for the power amplifier startto become the only feasible option.

Monolithic circuits do have some significant drawbacks.A smaller power amplifier footprint means that more heatmust be removed from the backside of the MMIC, whichcan impact the cost and complexity of the thermal man-agement system. Thermal management issues at the next-level assembly typically get flowed back to the MMIC man-ufacturer as a higher backside temperature requirementfor which the device must maintain reliable operation. Forthe power amplifier designer, reliable operation generallymeans that transistor channel temperature must not ex-ceed some maximum value (2). MMIC components can bemore costly than discrete circuits. The most direct way toreduce MMIC cost is to make the die as small as possi-ble. However, in the case of power amplifiers, die size com-paction is in direct conflict with maintaining a low channeltemperature. Amplifiers constructed with discrete compo-nents are relatively easy to tune, element values can beadjusted, metal traces can be cut or widened, etc. Some lim-ited circuit tuning is possible for MMIC power amplifiers.However, adjustments are limited and require specializedequipment and highly skilled personnel. Generally speak-ing, one has to get it right the first time when designingMMIC components.

The general subject of microwave power amplifierdesign has been covered extensively in the published lit-erature. Excellent references on power amplifier circuits,architecture, applications, analysis, and modes of opera-tion are readily available. It is of course not possible to listthem all, and the reader is referred to a few excellent, con-cise publications (2, 3, 8–11). This article focuses on con-siderations, approaches, and methods that are of greaterconcern to monolithic power amplifier design. The conceptsdiscussed apply to MMICs using bipolar devices (BipolarJunction Transistor (BJT), Heterojunction Bipolar Tran-sistor (HBT), etc.) or unipolar transistors (Metal Semicon-ductor Field Effect Transistor (MESFET), PseudomorphicHigh Electron Mobility Transistor (PHEMT), High Elec-tron Mobility Transistor (HEMT), Field Effect Transistor(FET), etc.). However, the material that follows will focuson the latter. The first section reviews an example specifi-cation for a high-frequency, narrowband, saturated poweramplifier MMIC. The next sections cover transistor cellanalysis and selection for the case of a 0.15-�m GaN onSiC device. This is followed by the description and appli-cation of a methodology for synthesizing and realizing the

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright © 2013 John Wiley & Sons, Inc.

2 Microwave Monolithic Power Amplifier Design

Table 1. Example MMIC Power Amplifier Specification

Specification Unit Minimum Maximum

Frequency GHz 22 24Small signal gain dB 16Small signal gain flatness dBpp 1Input return loss dB 12Output power: P3dB dBm 37Power-added efficiency: P3dB % 35Power supply current: P3dB A Info. onlyPower supply voltage V 19 21Die size (width × length) mm2 2.5 × 3.5MMIC backside temp. Deg 95

MMIC matching networks in microstrip format. The articleis concluded with the discussion of some practical consid-erations, including the impact of off-chip components andstability analysis.

MMIC POWER AMPLIFIER SPECIFICATIONS

The first step in the design of a MMIC power amplifier isan analysis of the specifications that define the circuit. De-pending on the intended application, a given MMIC PAmay be described by a long and varied list of specifica-tions. Most power amplifiers, however, do have some keyperformance parameters in common. An example specifica-tion for a microwave power amplifier intended for a high-efficiency saturated operation is shown in Table 1, alongwith a detailed description of each parameter and how therequirement can impact circuit design. Note that the pa-rameters listed in Table 1 are generally with respect tosome system reference impedance, commonly 50 �.

1. Frequency: Defines the frequency band over whichthe remainder of the specifications applies. The op-erating frequency of the amplifier will be a factor indetermining the transistor process (gate length andmaterial system) that is used for the design as wellas for the transistor unit cell size (cell periphery andgate finger length).

2. Small Signal Gain: Defines the minimum and maxi-mum linear gain (Gss) for the amplifier. This is equiv-alent to the s-parameter S21. The specified amount ofsmall signal gain will determine how many stages ofamplification will be required.

Gss(dB) =∣∣S21(dB)

∣∣ = 20log( ∣∣∣Vout

Vin

∣∣∣ ) (1)

3. Small Signal Gain Flatness: The amount in deci-bels that the small gain of a particular amplifier isallowed to vary over the operational frequency range.

4. Input Return Loss: Specifies how close the inputimpedance of the amplifier has be to some referenceimpedance. For most microwave systems, the refer-ence impedance is 50 �. This parameter is equivalentto the s-parameter S11 and is defined in equation 2for a 50-� reference impedance.

RL(dB) = −∣∣S11(dB)

∣∣ = −20log

(∣∣∣∣Zin − 50�

Zin + 50�

∣∣∣∣)

(2)

5. Output Power—P3dB: Defines the minimum out-put power (Pout) for the amplifier at an input powerlevel (Pin) that compresses the gain 3 dB from thesmall signal level. The minimum amplifier outputpower level determines the total periphery of the out-put transistor cells. The output power value in Table1 is given in a commonly used decibel scale referencedto 1 mW. The conversion between Watts and dBm isshown in Equation 3.

P(dBm) = 10 log

[P(mW)1 mW

](3)

6. Power-Added Efficiency (PAE)—P3dB: Definesthe minimum PAE for the amplifier at an inputpower level that compresses the gain 3 dB from thesmall signal level. Power-added efficiency is oftengiven in percent and is defined below. Note that theDC power (PDC) is the total consumed power for theinput power associated with the specified outputpower, not the small signal or quiescent DC power.

%PAE = 100Pout(W) − Pin(W)

PDC(W)= 100

Pout(W) − Pin(W)VDC(V )IDC(A)

(4)

7. Power Supply Current—P3dB: The power supplycurrent (IDC) drawn by the amplifier at an inputpower level that compresses the gain 3 dB from thesmall signal level. This is listed as “information only”for this example meaning that the customer willwant to know what the current is but is not placingpass/fail limits on the value. This is not uncommonwhen a maximum output power is not specified.For example, what if the fabricated design produces38 dBm of output power and is greater than 40% ef-ficient? It would still be specification compliant butwill draw considerable more supply current than a37-dBm amplifier at the same PAE. An estimationof this current level is useful for sizing the systempower supply as well as various components on theMMIC such as metal traces, thin-film resistors, andthe number of bondwires required to connect thepower supply.

8. Power Supply Voltage: Defines the minimum andmaximum available power supply voltages (VDC) forthe amplifier. This parameter influences process se-lection, as a given transistor technology will havea maximum operating voltage. The supply voltagelevel can also impact the circuit architecture and thinfilm capacitor design.

9. Die Size: Defines the maximum die size for thefabricated MMIC. The die size of course has a di-rect impact on the cost of the MMIC. However, it isalso specified due to limited available space at thenext-level assembly or the MMIC is replacing an ex-isting part and has to be precisely the same size. Inmost cases, it is desirable to make the die as small aspossible while maintaining an acceptable maximumchannel temperature.

10. MMIC Backside Temperature: This parameteroften reflects the user’s ability to manage the

Microwave Monolithic Power Amplifier Design 3

thermal interface between the MMIC and thenext-level assembly at some assumed level of powerdissipation. This is the MMIC backside temperaturethat one would use for thermal analysis to determinetransistor channel temperature.

TRANSISTOR CELL SELECTION AND DESIGN

The next task is the design and selection of an appropriatetransistor cell for the output stage of the circuit. Severalterms have been introduced, and it may be helpful at thispoint to review an example that illustrates how these pa-rameters interact with each other. Given the 20-V powersupply voltage and relatively high-frequency operation, a0.15-�m gate length GaN on SiC HEMT process will beconsidered for this design. The foundry that will be build-ing this MMIC has data and models available for the FETcell shown in Fig. 1. This transistor cell is constructed ofeight gate fingers, each being 75 �m long for a total devicesize of 600 �m. The separation of the gate fingers, the gate-to-gate pitch, is 15 �m. A smaller pitch will result in bet-ter electrical performance; however, the transistor junctiontemperature will also be higher. Note that the transistoris configured as common source with the source connectedto the MMIC backside ground plane on two sides with sub-strate vias.

A good way to assess transistor cell performance for aspecific application is to subject the device to load/sourcepull testing. Load/source pull characterization is a mea-surement technique where tuners at the input and outputof the device are adjusted to optimize some performanceparameter of interest (1, 3, 8, 10, 12). Ideally, one wouldanalyze measured load pull data on a candidate transistorcell. However, in the absence of measured data, the loadpull test can be emulated with a circuit simulator, givenan accurate nonlinear model for the transistor cell is avail-able. Transistor cell load pull data under different tuningconditions over a range of frequencies is often availablefrom the foundry. Efficiency-tuned load pull data measuredat 23 GHz for the device shown in Fig. 1 is plotted in Fig. 2.The tuners were adjusted for maximum power-added ef-ficiency at 2–3 dB of gain compression. The transistor isbiased at a quiescent bias condition of Vds = 20 V and

Figure 1. An 8 × 75 �m FET cell layout.

Figure 2. 23-GHz PAE tuned load pull for an 8 × 75-�m GaN0.15-�m FET.

Ids = 60 mA. The maximum observed value of PAE is 52%,and it occurs at an input power of about 23 dBm. The out-put power was measured to be 32.3 dBm or 1.7 W, and thegain is compressed about 2.5 dB from the 11.8 dB observedat 8 dBm of input power (approximately small signal). Us-ing Equation 4, the power supply current IDC at 23 dBm ofinput power is 144 mA, which is more than double the qui-escent current. The load and source reflection coefficients(50-� system) for optimum efficiency tuning at 23 GHzwere measured to be �S = 0.76 /173◦ and �L = 0.76/122◦.This transistor cell performs well at the center frequencyof the amplifier specified in Table 1 and is a good candi-date for this design. The load pull data indicate that theelectrical performance of this transistor cell is acceptable.However, will the transistor junction temperature resultin a reliable operation given the maximum MMIC back-side temperature listed in Table 1? The power dissipatedby the device is calculated with the following:

PD(W) = PDC(W) + Pin(W) − Pout(W) = PDC(1 − % PAE/100)(5)

For the data shown in Fig. 2 under optimal PAE tuning con-ditions, this works out to be 1.38 W or 2.3 W/mm of deviceperiphery. A somewhat higher power dissipation should beconsidered in the thermal analysis to provide margin. Athermal simulation of the transistor shown in Fig. 1 for a3.4-W/mm power dissipation and 95◦C backside tempera-ture is shown in Fig. 3. The maximum projected junctiontemperature under this condition is around 160◦C. Datafor maximum allowable transistor junction temperatureversus device lifetime should be available from the manu-facturer.

Ideally, if one were to combine four of these transis-tors, it should be possible to achieve an output power of4 × 1.7 W = 6.8 W, or 38.3 dBm. Of course, a matching net-work will need to be designed to transform the 50-� loadimpedance connected to the amplifier output such thatthe efficiency-tuned impedance determined from the loadpull data is presented to each transistor cell. This circuitwill also have to function as a power combiner, summingthe power from the four transistors to a single output forthe amplifier. Real output matching networks are not loss-less, and the loss tends to increase as the number of FET


Figure 3. Thermal simulation for an 8 × 75-�m GaN 0.15-�m FET cell with 3.4 W/mm dissipation.

cells being combined increases. Surprisingly, for narrow-band (10–20% bandwidth) amplifiers, the output matchingnetwork loss is not a strong function of operating frequency.These circuits use distributed transmission lines to real-ize series inductance. The loss of these lines does increasewith frequency. However, less inductance is required athigh frequency. In other words, the loss per unit lengthincreases but the overall length tends to decrease, and thetwo effects more or less cancel. The approximate values foroutput matching network loss for narrowband circuits onsemi-insulating substrates (GaAs, GaN on SiC, InP) lossare listed in Table 2 for increasing levels of binary transis-tor cell combining. Also shown in Table 2 is the impact thatoutput network loss has on efficiency. For an output match-ing network with 0.8 dB of loss, the maximum achievableefficiency is reduced to 83%. In other words, if the tran-sistors are 100% efficient and have infinite gain, then thePAE for the amplifier would be 83%.

Therefore, including the estimated output network loss,a MMIC combining four 8 × 75-�m transistor cells couldproduce up to 38.3 dBm − 0.4 dB = 37.9 dBm = 6.2 W.However, an actual device will probably deliver less powerfor several reasons. The maximum backside temperaturelisted in Table 1 is probably higher than the backside tem-perature for the die subjected to load pull testing. Theoutput matching network will not perfectly match the tran-sistors over the entire operating frequency band of the am-plifier, nor will it present exactly the same load impedanceto all four cells. There will also be some process variation

Table 2. Approximate Output Matching Network Loss and Im-pact on Efficiency

Number of Cells Loss (dB) �Efficiency

1 0.2 0.952 0.3 0.934 0.4 0.918 0.6 0.8716 0.8 0.83

from device to device within a given lot and manufacturingvariation lot to lot. The transistor cells present on the fab-ricated MMIC will not be exactly the same as those testedat load pull. In other words, additional margin should beincluded when selecting a transistor cell size. Assuming afour-way combined output network, it would be prudent touse an 8 × 75-�m FET cell to meet the output power re-quirement specified in Table 1. The linear gain shown inFigure 2 is about 11 dB, which is short of the minimum16 dB of small signal gain called for in Table 1. This ampli-fier will need at least two stages of gain using this 0.15-�mGaN process technology.

OUTPUT MATCHING NETWORK DESIGN

The transistor output tuning condition determined fromload pull testing is useful for designing the output match-ing network. The function of the output matching networkwill be to transform the 50-� output load impedance topresent the efficiency-tuned load to each of the four tran-sistor cells. Recall that at 23 GHz, load pull testing deter-mined that the optimum load reflection coefficient in a 50-�system was �L = 0.76 /122◦. This is easily converted into aload impedance, as follows:

�L = ZL − 50�

ZL + 50�⇒ ZL = 50�

1 + �L

1 − �L

= 8.86 + j27.05 � (6)

That implies that the output impedance of the transistorcan be modeled as the conjugate of Equation 6 such thatmaximum power transfer occurs when conjugate matched.The conjugate of Equation 6 is in the form of a series RCnetwork; however, an analysis of load pull data suggeststhat the frequency dependence of this transistor outputmodel actually behaves more like a parallel RC circuit.Converting the conjugated impedance given in Equation 6into a parallel RC network:

Y ∗L = 1

Z∗L

= 18.86 − j27.05

= 10.94 + j33.39 mS = 1Rp

+ jωCp

(7)


Figure 4. Output matching network problem.

where ω is the angular frequency in rad/s. Therefore, theoutput model will be a parallel RC with the following val-ues:

Rp = 10.01094

= 91.4� Cp = 0.033392 � ×23 GHz

= 0.23 pF

Load pull data is often provided in manufacturerdatasheets in Rp and Cp format. The output matching prob-lem for four-way combining is shown on the left side ofFig. 4. Ideally, all four transistors are driven in phase andhave identical output voltages. In other words, the match-ing network is operating in the even mode. Under even-mode excitation, the input nodes of the matching networkcan be arbitrarily connected together with a lumped ele-ment component. Because the voltage is identical at allfour nodes, no current will flow in the connected element,and it will have no influence on even-mode circuit opera-tion. Even-mode only excitation is an important assump-tion, as it allows for reductions in the circuit that can sim-plify network synthesis greatly. Under the even-mode as-sumption, the four outputs can be connected together andthe matching problem recast as shown on the right side ofFig. 4. A prototype matching network is given in Fig. 5. Thegoal is to achieve a real impedance, over the operating fre-quency of the amplifier, of Rp /4, which equals 22.9 �. Thefirst 0.92-pF shunt capacitor represents the output capaci-tance of the four transistor cells, 4Cp . Some of the circuit el-ements shown in Fig. 5 reflect the need to bias and connectthe circuit to the outside world. The first shunt inductor is

intended to supply the drain bias voltage to the transistorsand is high-frequency grounded by a 30-pF bypass capaci-tor. For relatively narrow bandwidth designs, this inductorcan be used to tune out some of the transistor output capac-itance, 4Cp . To prevent power supply current from flowingthrough the 50-� load, a 6-pF series DC blocking capacitoris placed near the output of the network. The final 0.25-nH inductor in series with the 50-� load models one ormore bondwires connected to the output of the amplifier.It is best to include the bias circuitry and MMIC inter-face elements early in the design process such that theycan be seamlessly integrated into the matching network.The 50.7-pH shunt inductor is sized to resonate with 4Cp

in the frequency range of interest approximately reduc-ing the problem to matching 22.9 � to 50 �. A standardlow-pass matching topology consisting of series inductorsand shunt capacitors is used to accomplish this. The simu-lated frequency of the prototype output matching networkis plotted in Fig. 6. The real part of the input impedanceis predicted to be 22.9 ± 1 � over the 22–24 GHz operatingfrequency band. The reactive component is simulated to be0 ± 2.2 �.

Under the assumption of even-mode excitation, the pro-totype matching circuit can be transformed into a four-waycombiner. An intermediate step is shown in Fig. 7, wherethe left side of the circuit has been separated into two par-allel connected channels. This circuit is equivalent to theoriginal prototype. If the two inputs are driven in-phasewith equal amplitude signals (even-mode), there will be no

Figure 5. Prototype lumped element output matching network.


Figure 6. Frequency response of prototype network.

current flowing in the connecting trace, and this connectionmay be removed separating the two inputs. This procedurecan be continued, yielding the final lumped element four-way output matching network shown in Fig. 8.

Now the lumped element circuit shown in Fig. 8 willhave to be converted into a microstrip circuit that can befabricated with MMIC process technology. Some practicalmatters need to be addressed at this point. Process designrules will place some restrictions on realizing a microstripimplementation of the matching network. An analysis ofthe load pull data collected on the 8 × 75-�m transistorcell revealed that under saturated conditions, the devicedraws about 144 mA of current. There are four of theseFETs in the output stage of this amplifier for an approx-imate total current draw with a margin of 600 mA. Semi-conductor manufacturers provide design rules for theirprocesses, and this document will define safe maximum

Figure 7. Equivalent even-mode two-way combiner circuit.

Figure 8. Final even-mode four-way lumped element combiner circuit.


Figure 9. Approximate equivalent circuits for sections of trans-mission line.

ratings for the various process elements. For example, as-sume that the maximum current that a conductor canhandle is 15 mA/�m of line width. The trace used to re-alize the 0.2-nH bias inductor will need to be at least600 mA/15 mA/�m = 40 �m wide if the amplifier is biasedfrom one side of the circuit only. Now if the amplifier canbe biased from both sides of the circuit, then the bias linewill have to be at least 20 �m wide. The designer must en-sure that all current-carrying elements are sized to handlethe expected current densities. The transistor cell shownin Fig. 1 has physical dimensions and one or more processdesign rules governing how close together these FETs canplaced. For example, there will be a design rule restrictingthe minimum separation between substrate vias, for nowassume 100 �m. This rule will force the center-to-centertransistor drain bus separation between adjacent cells tobe at least 420 �m. In other words, the transmission linerealizations for some of the inductors that connect the tran-sistor cells together cannot be arbitrarily short.

Approximate lumped element equivalent circuits forsections of transmission line take the form of the “Tee”and “Pi” networks shown in Fig. 9. Therefore, the induc-tors shown in Fig. 8 can be replaced by sections of mi-crostrip transmission line where some amount of shuntcapacitance will be absorbed into the line. The remainingshunt capacitance can be realized as metal-insulator-metal(MIM) capacitors or open-circuited transmission line stubs(13). Typically, the dielectric material for MIM capacitorsis silicon nitride. Many MMIC manufacturers will providea capacitance density for their MIM capacitance, as wella maximum operating voltage. Typical MIM capacitancedensities range from 200 pF/mm2 to 1200 pF/mm2. Bear inmind that the higher the capacitance density, the lowerthe operating voltage. A recommended procedure is to re-place circuit elements in Fig. 8 one at a time with elementsfrom the foundry process design kit (PDK). After each ele-ment is replaced, then re-optimize the circuit to replicateFigure 6 as closely as possible. For example, replace all ofthe 0.2nH inductors with transmission line sections thatare 40 �m wide and optimize the line length. Next, re-place the 7.5-pF and 15-pF shunt capacitors with foundrykit models. These capacitors will have a nonzero electricallength. The via connected to the bottom plate will have in-ductance and the capacitor itself will have a physical dis-tance that the RF current must traverse before reachingthe via contact. The trace that replaced the 0.2-nH induc-tors will therefore need to be shortened slightly to recoverthe original frequency response once foundry models forthe shunt bypass capacitors have been added. Repeat thisprocedure with each element in the circuit until all induc-tors have been replaced with sections of microstrip trans-

Figure 10. Microstrip realization of the output matching net-work.

mission line and all capacitors have been replaced with thePDK models. A possible MMIC compatible realization ofthe output matching network is shown in Fig. 10. Trans-mission line sections are realized as a microstrip line (9,13). The SiC substrate is 100 �m thick and has a dielec-tric constant of εr = 9.7. The metallization is gold and isassumed to 6 �m thick. The values of the shunt capaci-tors are listed on the drawing, and they are constructedon top of substrate vias to provide a ground connectionfor the bottom plate to the back of the MMIC. Note thatcurved “trombone” sections of line are used to reduce theoverall length of the network. The patch of microstrip atthe far right side is the output bondpad required for bond-wire attachment to the next component in the system. Atthis point, the width dimension of the MMIC can be esti-mated as the width of the circuit shown in Fig. 10, plus any“keep out” region between the actual edge of the MMIC andthe metallization. Design rules for the “keep out” regionwill be available from the foundry that is building the de-vice. A representative number for GaN on SiC is 125 �m.Based on the output matching network layout shown inFig. 10, the width of the MMIC is estimated to be 2.0 mm,which is well within the 2.5 mm maximum dimension listedin Table 1.

The simulated frequency response for the inputimpedance of this circuit is near identical to that of theprototype network shown in Fig. 6. The predicted dissi-pative loss for the output matching network is plotted inFig. 11. Dissipative loss is calculated from the network s-parameters with Equation 8. Less than 0.3 dB of loss is pro-jected for the output matching network at 22 GHz puttingthe estimated amplifier output at 38 dBm or 6.3 W. Notethat the simulated output matching network loss is in linewith the approximate value of 0.4 dB listed in Table 2 for


Figure 11. Predicted loss for the output matching network.

four-way combining.

Loss(dB) = −10 log

( |S21|21 − |S11|2

)(8)

INTERSTAGE MATCHING NETWORK DESIGN

The linear gain specification listed in Table 1 is 15 dB min-imum, and the linear gain shown in the load pull data isaround 11 dB. To meet the linear gain requirement, an ad-ditional gain stage will be required. The network betweenamplifier stages is referred to as an interstage matchingnetwork and has many functions. This network providesgate bias voltage to the second (output) stage and drainbias voltage to the first (input) stage. The interstage cir-cuit is sometimes used to compensate for negative gainslope versus frequency that will occur for the output stage.These transistors are more than capable of causing oscil-lations. Amplifier stabilization circuits, the intentional in-troduction of loss, are included as needed in the interstagenetwork. This is particularly true for even-mode excitation,and these stability circuits often cause the interstage net-work loss to be somewhat higher than that of the outputmatching network. According to the load pull data, eachoutput transistor cell must be driven with at least 23 dBmof power to reach 3 dB of gain compression. In other words,given the input stage transistor cell size, the interstage net-work must present a good enough load to the output of thefirst stage devices such that they produce sufficient powerto drive the output stage. To make matters worse, neitherthe source nor the load impedance is purely real, as thenetwork is loaded by the highly reactive input impedanceof the output stage transistors. Nevertheless, interstagenetworks can be designed to cover these requirements ac-ceptably.

Step 1 is to estimate how large the first stage transis-tor cells need to be to overcome the loss of the interstagematching network and drive the output stage to peak effi-ciency with sufficient margin for temperature and part-to-part variation. So why not just make the first-stage FETsas big as the output stage devices? The first stage tran-sistors do not contribute to the overall output power of theamplifier; however, they do consume DC power. If these de-vices are made too large, then the power-added efficiency

of the amplifier will be impacted in a negative way. If thefirst-stage FETs are made too small, then there will not besufficient power to drive the output stage to 3 dB of com-pression, and both output power and PAE will be adverselyaffected. The latter situation is far worse, and it is recom-mended that one err on the side of oversizing the first stagetransistors and accepting a few percentage points of lowerefficiency. This procedure can be somewhat iterative be-cause it is based on an initial estimate of the interstagenetwork loss. Examining the load pull data shown in Fig.2, it took about 23 dBm of input power to drive the tran-sistor to peak PAE. Because there are four transistors inthe output stage of this design, the first stage will have todeliver 29 dBm of power measured at the input of the out-put stage devices. Now assume a worst case of 2 dB of lossfor the interstage network, such that the first-stage tran-sistors will have to deliver a total 31 dBm of output power.The load pull data shown in Fig. 2 were probably measuredat room temperature; however, this amplifier will need tooperate with a +95◦C MMIC backside temperature. A goodrule of thumb for power amplifiers is a gain temperaturecoefficient of –0.015 dB/◦C/stage. Assuming a +25◦C MMICbackside temperature for the load pull measurement, theoutput stage gain for a +95◦C base could drop by as muchas 0.015 × (95◦C – 25◦C) = 1.05 dB. The mechanical tunersused for the load pull test also have a physical limitation onhow high the magnitude reflection coefficient can be thatis presented to the device. The source tuner at the transis-tor input probably cannot tune these devices for maximumgain at 23 GHz. In other words, the gain capability of thetransistor under investigation may be higher than whatis measured at load pull. Taking this under consideration,the output power required from the first-stage transistorsis approximately 31–32 dBm. However, most of the allowed3 dB of gain compression for the entire amplifier will occurin the output stage to reach peak efficiency. According tothe load pull data, the transistor is 2 dB compressed whendriven to peak PAE, meaning that only 1 dB of gain com-pression is allowed in the first stage. The output power forthese devices at 1 dB of gain compression is about 29 dBm.Two 8 × 75-�m FETs will be able to deliver 32 dBm at 1 dBof gain compression when tuned for efficiency. This is a goodinitial guess for the first-stage transistor periphery, as itaccounts for gain compression and provides some marginto the estimated 31–32-dBm requirement.

At this point, one should do a sanity check on the DCpower budget. The projected output power is 38 dBm andthe current draw from the output devices will be about4 × 144 mA = 576 mA. The amplifier gain at 3 dB of gaincompression must exceed 13 dB, so the maximum inputpower will be 38 dBm – 13 dB = 25 dBm or 316 mW. Solv-ing Equation 4 for DC current given a 35% minimum PAEand a 20 V DC supply projects a total current budget of856 mA or 289 mA for the first stage. The load pull data at1 dB of gain compression shows a current draw of 96 mAper 8 × 75-�m FET cell or 192 mA for two such devices.Therefore, a first stage constructed with two 8 × 75-�mtransistor cells supports the drive requirement over tem-perature as well as the current budget, so long as the 2 dBassumption for the interstage loss is fairly accurate. Thematching problem for the interstage network is shown in


Figure 12. Interstage matching network problem.

Fig. 12 along with the conversion to an even-mode two-portcircuit.

Clearly, one will need a model for the transistor cellsto design the interstage network. Ideally, this would bea nonlinear model supplied by the foundry manufactur-ing the MMIC. Suitable nonlinear models should be avail-able in the process design kit for the technology of choice.Nonlinear models can have convergence issues and willresult in having a longer simulation time than a linearequivalent. During the initial design phase, it is sometimesadvantageous to use linear models and load pull data torepresent the transistor cells. This allows the designer toinvestigate quickly different circuit topologies and synthe-size matching networks that are reasonably close to opti-mum. Of course, the final design optimization should beperformed under large signal conditions with a nonlinearmodel. A commonly used linear equivalent circuit modelfor the device shown in Fig. 1 is illustrated in Fig. 13. Thismodel includes the gate and drain feed networks as well asthe inductance of the two substrate vias connected to thesource. Note that the controlling voltage for the voltage-controlled current source (VCCS) is across Cgs and Ri. Thecomplex exponential governing the phase of the currentsource is handled within the circuit simulator and the userneed only enter the parameter τ. There are many excellentreferences on linear circuit modeling of microwave FETsfor the interested reader (1–3, 14–19).

A prototype even-mode interstage matching network isshown in Fig. 14. Note that a DC block, drain/gate biasinductors, and bypass capacitors are integrated into thecircuit topology. Some resistors are included, which can beuseful for stabilizing the amplifier and compensating forgain slope versus frequency. Using even-mode transforma-tions, as was done for the output network, this circuit canbe configured as a two-way to four-way divider networkas shown on the left side of Fig. 12. The simulated inputimpedance for the interstage network is plotted in Fig. 15.Note that the bandwidth of the interstage is not as wide asthe output matching network (Fig. 6). The output match-ing network had a reactive source impedance but a purelyreal 50-� load. The interstage network has reactive sourceand load impedances, which will reduce the bandwidth fora matching circuit of similar complexity.

Following the same procedure used for designing theoutput matching network, a microstrip implementation ofthe interstage network was generated and optimized. Theresulting circuit layout added to the output network isshown in Fig. 16. The frequency response of the microstripversion of the interstage is predicted to be essentially iden-tical to that of the lumped element prototype plotted in Fig.15. The predicted loss of the microstrip interstage match-ing network as a function of frequency is given in Fig. 17.Note that the network loss is projected to be 2 dB or lessover the operating band of the amplifier and decreases

Figure 13. Linear circuit model for an 8 × 75-�m GaN transistor.


Figure 14. Prototype even-mode interstage matching network.

Figure 15. Frequency response of prototype interstage network.

as the frequency increases. This positive slope versus fre-quency will compensate for some of the negative gain slopecharacteristic of the transistors. The simulated small sig-nal frequency response of the circuit configured as shownon the left side of Fig. 12 is plotted in Fig. 18. The sim-ulated linear gain over the 22–24 GHz design frequencyband is about 11 dB and relatively flat. Accounting for thesimulated loss of the matching networks, this transistor isproducing about 13 dB of linear gain. This is about 1.3 dB

Figure 17. Predicted loss for the interstage matching network.

more gain than was measured at load pull, suggesting thatthe input tuner may not have sufficient range to match theinput of this device.

INPUT MATCHING NETWORK DESIGN

The input matching network problem is shown in Fig. 19.This network supplies gate bias voltage to the first stagetransistors and performs the necessary division of the

Figure 16. Microstrip realization of the interstage and output matching networks.


Figure 18. Simulated small signal frequency response of the cir-cuit shown in Fig. 12.

input signal. Like the interstage, the input network is of-ten used to compensate for gain slope versus frequency andto provide amplifier stabilization through the intentionalintroduction of loss. Most microwave systems operate intoa 50-� impedance reference and the input matching net-work should be designed such that the input impedance

of the amplifier is approximately equal to 50 �. A proto-type even-mode network for a candidate input matchingnetwork is shown in Fig. 20. Following the procedure usedfor the other networks, a microstrip realization of the cir-cuit was developed. The two-stage MMIC with input, in-terstage, and output matching networks is illustrated inFig. 21. Note that the chip edge is now included and labelshave been added to identify the MMIC bondpads. Labelingcan usually be done with a Silicon Nitride layer such thatthe proximity of the labels to the actual circuitry will havea negligible impact on amplifier performance. The overalllength of the MMIC is estimated to be 3.2 mm. The simu-lated small signal frequency response for the amplifier isplotted in Figure 22. Linear gain, gain flatness, input re-turn loss and die size are all meeting the requirementsset forth in Table 1. Now a large signal simulation ofthe power amplifier MMIC should be performed. Usingthe manufacturer-supplied nonlinear transistor model, theprojected output power and efficiency at 3 dB of gain com-pression is plotted in Fig. 23. The quiescent bias conditionis Vd = 20 V and Id = 360 mA, requiring a gate voltageof –2.38 V. The output power is predicted to be greaterthan 38 dBm (6.3 W), which provides some degree of mar-gin over the 37-dBm (5-W) specification for manufacturing

Figure 19. Input matching network problem.

Figure 20. Prototype even-mode input matching network.


Figure 21. MMIC layout with input, interstage, and output matching networks.

Figure 22. Simulated small signal frequency response for the PAMMIC.

and temperature variation. The power-added efficiency issimulated to be in excess of 40% over the operating band ofthe amplifier, again providing margin to the 35% require-ment. The total DC current draw when operated at 3 dB

Figure 23. Large signal simulated results for the completeMMIC design.

of gain compression varies between 767 mA and 843 mA,depending on frequency.

The simulations shown thus far are based on microstripcircuit element models resident within the simulation en-vironment. Whereas these models generally have good ac-curacy, whenever possible the network models should beverified with electromagnetic simulation. This will accountfor mode generation and electromagnetic coupling betweensections of the circuit that will not be predicted by themicrostrip element models. Small adjustments may be re-quired after the electromagnet simulations reoptimize thepredicted amplifier performance.

EXTERNAL COMPONENT AND INTERCONNECTEFFECTS

Generally speaking, it is not good to have significant lev-els of gain outside the specified operating frequency rangeof the amplifier. Out-of-band terminating impedances aretypically not well controlled, increasing the likelihood of os-cillation and other issues such as noise power generation,jamming sensitivity, unintended frequency conversion, etc.A wideband simulation of the amplifier is plotted in Fig. 24,and there is significant gain at low frequency. The reasonfor this is the bypass capacitors on the MMIC are not ahigh enough value to provide an AC ground (bypass) at lowfrequency. Apparently, this amplifier will require some “offchip” capacitors and the impact of these components shouldbe included in the circuit simulation. Simulated amplifierfrequency responses for two different bypass circuits areshown in Figs. 25 and 26. The inductor models a bondwireconnecting the MMIC to the off-chip components. The cir-cuit inset in Fig. 25 achieves a low-frequency bypass with a0.01-�F capacitor to ground. Examining the plot, the gainhas indeed been reduced at a very low frequency. How-ever, things are actually worse around 2 GHz where thecircuit has positive gain and several sharp resonant peaks


Figure 24. Simulated wideband frequency response for the PAMMIC.

Figure 25. Simulated wideband frequency response for a0.01-�F bypass capacitor.

are present. What has happened is that the 0.01-�F ca-pacitor is an AC ground effectively connecting the bond-wire inductance to ground. This inductor may now paral-lel resonate with the on-chip bypass capacitors effectivelynegating (open circuiting) them at the resonant frequency.Now consider the bypass circuit and simulation shown inFig. 26. Placing a 13-� resistor in series with the 0.01-�F off-chip capacitor greatly improves the situation as the

Figure 26. Simulated wideband frequency response with the ad-dition of a 13-� resistor.

low-frequency gain has been reduced to about –17 dB andthe sharp resonances are no longer present.

STABILITY CONSIDERATIONS AND ANALYSIS

At this point, one should assess the stability of the ampli-fier. A commonly used measure of the stability of a two-portnetwork is the k-factor. The k-factor is calculated from thetwo-port network s-parameters of the amplifier and is use-ful as a rough indicator of amplifier stability (9, 13).

k = 1 − |S11|2 − |S22|2 − |S11S22 − S12S21|22 |S12S21| (9)

If k > 1, then the two-port network will not oscillate forany passive source and load terminating impedance in theabsence of external feedback. Of course, there is a lot offeedback occurring within the amplifier, as well as modesof oscillation that do not depend on source/load impedance.In other words, k > 1 does not necessarily guarantee thata multistage amplifier is unconditionally stable; however,k < 1 does guarantee that it is not unconditionally stable.So keeping an eye on the k-factor during the design phaseis good practice until a more rigorous stability analysis canbe performed on the completed circuit.

Although k-factor analysis may be useful for spottingserious stability issues, it is not useful for rigorously de-termining the stability of a multistage amplifier with mul-tiple FET cell combining (20). Several rigorous stabilityanalysis techniques are described in the literature (21, 22).One method familiar to analog circuit designers is the loopgain analysis (4). To apply loop gain stability analysis to aMMIC power amplifier, one must first alter the linear FETmodel to gain access to the circuit loop in a manner thatdoes not load the circuit. A linear FET model suitable forloop gain analysis is shown in Fig. 27. Some foundry de-sign kits do not allow the user to edit the transistor circuitmodels. In this case, it is recommended that the foundrytransistor model s-parameters be fit to the circuit modelshown in Fig. 13.

Note that two VCCS have been added to the transistormodel. These additional components serve two purposes.First, they act as high-impedance buffers such that what-ever is connected to the ports labeled Vin and Vout will notload the circuit under investigation. Second, they shift theground reference. Simply connecting high-impedance portsto the top of the current source and Cgs would place V1 andV2 across these points and the circuit ground, not acrossthe current source and Cgs and Ri as shown in Fig. 27. Notethat the controlling voltage for the VCCS, which was ini-tially across the series combination of Ri and Cgs, is movedto an external voltage controlled voltage source (VCVS)with unity gain. The controlling voltage of a second unitygain VCVS is connected across the series combination ofRi and Cgs. This VCVS is functioning as a high-impedancevoltmeter to measure the voltage that appears across Ri

and Cgs, which was the original location of the controllingvoltage for the current source in the FET model shown inFig. 13. Note that if the Vin and Vout nodes are connectedtogether, then the circuit shown in Fig. 27 is equivalentto the linear circuit model in Fig. 13. Therefore, all the


Figure 27. Linear FET model suitable for loop gain analysis.

linear transistor models in the circuit simulation can bereplaced with the circuit shown in Fig. 27 with the Vin andVout ports connected together. The circuit works as follows:inject a 1-V signal into the Vin port, which is connected tothe controlling port of the VCCS. This activates the tran-sistor model current source and the resulting current flowsthroughout the amplifier network causing a voltage to ap-pear at the Vout port, the controlling port for the VCCS inthe original transistor model shown in Fig. 13. If this re-turn signal has a magnitude greater than or equal to 1 Vand is in-phase, it is self sustaining and will grow into anoscillation. The complex ratio of Vout to Vin is called theloop gain (LG) of the circuit, which may be plotted in polarformat.

LG = Vout

Vin(10)

To perform stability analysis disconnect, the Vin andVout ports of one of the transistors in the circuit, leavingthese ports connected for all of the other transistors. Cal-culate the complex loop gain and plot in polar format. Ifthis curve encircles the polar point 1 and at angle of 0◦,then the amplifier is oscillating. Amplifier stability can bea strong function of the terminating impedances connectedto the input and output ports of the amplifier. Ideally, bothof these impedances would be a constant 50 � for all fre-quencies; however, in reality this condition is not practical.Outside of the operating frequency range of the system thatthe amplifier is embedded in, the terminating impedancescan deviate significantly from 50 �. In practice, one shouldtry to demonstrate stability for arbitrary passive termi-nating impedances–in other words, input and output re-flection coefficients of unity magnitude with an arbitraryangle between 0◦ and 360◦. One also has to be concernedabout transistor variation, from unit to unit and over tem-perature. A good rule of thumb is to attempt to demon-strate amplifier stability with the following modificationsto the transistor model. Increase gm by 30%, decrease Cgs

by 30%, and increase Cgd by 30%. This will generally pro-duce a worst-case scenario for amplifier stability coveringdevice-to-device variation and variation over temperature.

Figure 28. Loop gain plot for Q3 under worst-case conditions.

A loop gain plot for transistor Q3 is shown in Fig. 28. Forthis analysis, all circuit transistors have been modified toproduce a worst-case stability scenario. The analysis is car-ried out over a wide enough frequency range such that loopgain trace approaches the center of the chart for the upperand lower frequency sweep limits. The trace starts at thecenter of chart for the lower frequency limit of 0.5 GHz andis approaching the center for the high-frequency limit of70 GHz. The trace does not encircle the unity gain pointdenoted by the red X, and the amplifier is therefore sta-ble with respect to Q3. The worst-case phase margin is 60◦

occurring at 20.8 GHz. Similar plots will need to be gener-ated for all of the transistors in the circuit above the lineof half symmetry (Fig. 29).

The assumption of even-mode operation has been usedseveral times in the development of this amplifier cir-cuit. However, it is possible for this circuit to operatein the odd mode as well. There will be an unavoidableodd-mode component due to microstrip discontinuities,


Figure 29. MMIC half and quarter symmetry lines.

unintended coupling, and process variation across theMMIC for the transistors, capacitors, line widths, etc.Therefore, amplifier stability for odd-mode operation mustalso be considered. Under the even-mode assumption, ad-jacent transistors operate in phase, meaning that zero cur-rent would flow in a connection between them. In otherwords, virtual open circuits are located at the MMIC linesof symmetry as indentified in Fig. 29. For the case of odd-mode operation, adjacent transistors operate 180◦ out ofphase and a virtual short circuit will exist along the linesof symmetry. Because this amplifier combines four transis-tors in the output stage, there are two different odd-mode

circuits to consider. The half symmetry circuit is formedby placing a virtual short along the MMIC horizontal cen-ter line as shown in Fig. 29. Any circuit elements touchingthe half symmetry line are to be shorted to ground in thecircuit simulation. This amplifier also has quarter sym-metry; again, parts of the circuit touching this line are tobe shorted to ground in the simulation. Half and quarterodd-mode circuits for this MMIC are illustrated in Fig. 30.Odd-mode stability analysis is carried out as previouslydescribed, disconnecting the loop gain ports one at a timefor the transistors in the odd-mode circuit and generatingloop plots. Note that odd-mode stability is not a function

Figure 30. Half and quarter symmetry odd-mode circuits.


Figure 31. Half and quarter symmetry odd-mode loop gain plotfor Q3 under worst-case conditions.

of the terminating impedances because the amplifier in-put and outputs ports are short circuited. Loop gain plotsfor transistor Q3 quarter and half symmetry circuits areshown in Fig. 31. Again, all circuit transistors have beenmodified to produce a worst-case stability scenario, and theanalysis is performed over a 0.5-GHz to 70-GHz frequencyrange. The traces do not encircle the unity gain point de-noted by the red X and the amplifier is therefore odd-modestable. However, the phase margin for the quarter symme-try circuit is only 38◦ at 23.5 GHz. Fortunately, odd-modestability can be greatly improved with very little impacton even-mode circuit performance. So-called “odd-mode re-sistors” can be connected between the transistor cells asshown in Fig. 32. For the even-mode operation, the volt-age across these resistors will be zero; they will dissipate

no power and have no impact on amplifier performance. Inpractice, these resistors are realized as thin-film resistorswith finite dimensions so they will add a small parasiticcapacitance that can be easily absorbed into the matchingnetworks. For odd-mode operation, the situation is very dif-ferent. These resistors are divided by the lines of symmetryinto two series-connected resistors. Each of them is half thevalue of the original, with the node between the resistorsgrounded by the symmetry line. This grounded shunt re-sistor has a significant impact on odd-mode stability. Loopgain plots for the odd-mode circuits are shown in Fig. 33with 20-� odd-mode stability resistors placed between thetransistor cells. This analysis was performed for the sameconditions as that shown in Fig. 31 and the phase marginhas increased to 115◦.

Figure 33. Half and quarter symmetry odd-mode loop gain plotfor Q3 with odd-mode resistors.

Figure 32. Two-stage MMIC block diagram with the inclusion of odd-mode stability resistors.


CONCLUSION

The performance of the power amplifier MMICs can lit-erally make or break the chances of having a successfuldesign and can affect the operation of modern microwavesystems. The advent of high-voltage MMIC technologies,such as gallium nitride, has resulted in more advanced andbetter performing system architectures. However, takingfull advantage of the higher operating voltage leaves littlemargin for error in the electrical and thermal design of thepower amplifier MMIC. This is particularly true at a highfrequency where high-quality discrete devices and match-ing components are no longer available and a monolithicimplementation of the circuit is the only option. To illus-trate a design approach, a two-stage saturated power am-plifier MMIC example has been presented. The key steps inthe design process have been described and demonstrated,starting with a description of the power amplifier specifi-cations. This was followed by an examination of transistorlevel data and the selection of a unit cell with appropriateelectrical and thermal characteristics. Next, the variousmatching networks were synthesized and implemented ina microstrip, and then an entire circuit was analyzed toensure stable operation under worst-case conditions.

ACKNOWLEDGMENTS

The author would like to thank Chris Rodenbeck for his ini-tial recommendation to write this article and Cassie Strick-land at John Wiley & Sons, Inc. for cheerfully putting upwith my multiple requests for deadline extensions. I wouldlike to thank the reviewers for insightful comments thatimproved the accuracy and quality of the work, and EliReese and Kenneth Wills for proofreading the original sub-mission. Finally, thanks goes to TriQuint Semiconductorsenior management for supporting this project and pro-viding the necessary resources to complete the document.

BIBLIOGRAPHY

1. J. M. Golio. Microwave MESFETs & HEMTs. Artech House:Boston, MA, 1991.

2. R. Goyal. Monolithic Microwave Integrated Circuits: Technol-ogy and Design. Artech House: Boston, MA, 1989.

3. G. D. Vendelin, A. M. Pavio, and U. L. Rohde. Microwave Cir-cuit Design Using Linear and Nonlinear Techniques. John Wi-ley and Sons: New York, 2005.

4. P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer. Analysisand Design of Analog Integrated Circuits. John Wiley & Sons:New York, 2009.

5. R. F. Davis and M. S. Shur. GaN Based Materials andDevices—Growth, Fabrication, Characterization and Perfor-mance. World Scientific: Singapore, 2004.

6. S. Koch, I. Kallfass, R. Weber, A. Leuther, M. Schlechtweg, andS. Saito. A Fully Integrated, Compound Transceiver MIMICutilizing Six Antenna Ports for 60GHz Wireless Applications,in IEEE CSIC Symposium, 2009, pp 37–40.

7. C. F. Campbell and M. Poulton, Compact Highly Integrated X-Band Power Amplifier Using Commercially Available DiscreteGaN FETs, in Asia-Pacific Microwave Conference, 2011, pp243–246.

8. S. C. Cripps. RF Power Amplifiers for Wireless Communica-tions. Artech House: Boston, MA, 1999.

9. G. Gonzalez. Microwave Transistor Amplifiers—Analysis andDesign. Prentice-Hall Inc.: Upper Saddle River, NJ, 1997.

10. P. Colantonio, F. Giannini and E. Limiti, High Efficiency RFand Microwave Solid State Power Amplifiers, John Wiley &Sons, 2009.

11. F. H. Raab, P. Asbeck, S. Cripps, P. B. Kenington, Z. B. Popovic’,N. Pothecary, J. F. Sevic, and N. O. Sokal. Power Amplifiers andTransmitters for RF and Microwave. IEEE Trans. MicrowaveTheory Tech. 2002, 50(3), pp 814–826.

12. S. C. Cripps. A Theory for the Prediction of GaAs FET Load-Pull Power Contours, in IEEE Int. Microwave Symp. 1983, pp221–223.

13. D. M. Pozar. Microwave Engineering. Addison-Wesley: Read-ing, MA, 1990.

14. W. Curtice and R. Camisa. Self-Consistent GaAs FET Mod-els for Amplifier Design and Device Diagnostics. IEEE Trans.Microwave Theory Tech. 1984, 32, pp 1573–1578.

15. H. Kondoh. Accurate FET Modeling from Measured S-Parameters. IEEE Intl. Microwave Symp. 1986, pp 377–380.

16. N. Rorsmann, M. Garcia, C. Karlsson, and H. Zirath. AccurateSmall-Signal Modeling of HFET’s for Millimeter-Wave Appli-cations. IEEE Trans. Microwave Theory Tech. 1996, 44, pp432–437.

17. S. Yanagawa, H. Ishihara, and M. Ohtomo. AnalyticalMethod for Determining Equivalent Circuit Parameters ofGaAs FET’s. IEEE Trans. Microwave Theory Tech. 1996, 44,pp 1637–1641.

18. M. Berroth and R. Bosch. Broad-Band Determination ofthe FET Small-Signal Equivalent Circuit. IEEE Trans. Mi-crowave Theory Tech. 1990, 38, pp 891–895.

19. G. Dambrine, A. Cappy, F. Heliodore, and E. Playez. ANew Method for Determining the FET Small Signal Equiv-alent Circuit. IEEE Trans. Microwave Theory Tech. 1988, 36,pp 1151–1159.

20. A. Platzker, W. Struble, and K. Hetzler. Instabilities Diagno-sis and the Role of K in Microwave Circuits, in IEEE Int. Mi-crowave Symp., 1993, pp 1185–1188.

21. W. Struble and A. Platzker. A Rigorous Yet Simple Method ForDetermining Stability of Linear N-Port Networks, in GaAs ICSymp., 1993, pp 251–254.

22. K. Wang, M. Jones, and S. Nelson. A New Cost-Effective,4-Gamma Method for Evaluating Multi-Stage Amplifier Sta-bility, in IEEE Int. Microwave Symp., 1992, pp 829–832.

CHARLES CAMPBELL

microwave monolithic power amplifier designecee.colorado.edu/~ecen5014/chuck-mmic power amplifier...

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