midterm2-2
TRANSCRIPT
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MIDTERM TEST 2 (60-265)
Saturday, 23 March 2002 Time: 3.30 pm to 5.30 pm (2 hrs)
Students
Name:
Student
Number:
Seat Number
Q.1(a) The content of a 4-bit shift register is initially 1101.
It is shifted to the right six times with the serial input being 101101.What is the content of the register aftereach shift?
(b) Show the external connections necessary to construct a 64K X 8 ROM by usingthe following components:4 number 16K X 8 ROM chips, each with its Enable input.1 number 2-to-4 Decoder
(c) Represent the following conditional control statement by two register transferstatements with control functions:
if (P = 1) then (R1 R2);
else if (Q = 1) then (R1 R3)
(d) Register A holds the 8-bit binary number 11011001. For each of the followingtwo cases, determine the B operand and the logic micro-operation to be performedin order to change the value in A to
(i) 01101101(ii) 11111101 (20 Marks)
Q.2Draw the logic diagram of a 2-to-4 line decoder with only NOR gates. Include anenable input. Give the truth table of the decoder. (15 Marks)
Q.3A 4-bit binary counter has the following controls:
Synchronous Parallel loadingIncrement
Draw its block diagram showing only all the inputs and outputs.Show how an AND gate and an INVERTER can be used to convert the 4-bitbinary counter to a divide-by-12 counter. (10 Marks)
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Q.4
a) An 8-bit register R contains the binary value 10011100.
Determine the sequence of binary values in R in each of the following four
cases: after an arithmetic shift right;followed by a logical shift-left;followed by a circular shift-right;followed by an arithmetic shift-left.
Discuss whether the last operation of arithmetic shift left leads to a multiplicationby 2 or not.
b) A 4-line common bus system is to be constructed for data transfer from four 4-bit registers P, Q, R and S. Use 4 x 1 multiplexers to construct the system. Drawthe bus system, showing the four bus lines clearly.
(25 Marks)
Q.5A circuit is to provide the operations of addition and subtraction of two 4-bitoperands. It should also provide the facility of incrementing to one of the twooperands.Use XOR gates, 1-bit full-adders, a 4-bit counter with parallel-loadand other necessary components to construct the circuit. Draw a neat circuitdiagram and give the function table for the circuit. (30 Marks)
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60-265
MIDTERM TEST 2
SOLUTION
Q1
a)
The content of a 4-bit counter is initially 1101.
Serial input = 101101
We use the last 4 bits (1101)
After 1st shift 1110
After 2nd shift 0111
After 3rd shift 1011
After 4th shift 1101
After 5th shift 0110
After 6th shift 1011
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b)
2^16 = 64k2^14 = 16k
c)
3
2
1
02 to 4 line
decoder
E Address
Data
E Address
Data
E Address
Data
E Address
Data
A14
A15
Data Lines
8 8 8 8
14 14 14 14
Address
A0 A13
14
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P: R1 R2
PQ: R1 R3
d)
(i) A = 11011001
B = 10110100 XOR
-------------------
011011101
(ii)A = 11011001
B = 00100100 OR
-------------------
11111101
Q2. 2-to-4 line decoder
Truth table
S1 S0 D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
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D0
D1
D2
S1
E
D3
D0
D1
D2
D3
S0 S1S1 S0
E
S0
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Q3
Divide by 12 counter
Counts from 0000 to 1011
Q4 a)
First Operation 10011100
Second Operation 11001110
Third Operation 10011100
Fourth Operation 01001110
Fifth Operation 10011100
I0 D0
D1
I1 D24 Bit Binary
I2 Counter
I3 D3INR Load
Clock
0
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The last operation leads to an OVERFLOW.
Hence it does not lead to a multiplication by 2.
b)4-bit bus using MUX
0 1 2 3 0 1 2 3 0 1 2 3
4 to 1
MUX
0 1 2 3
0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
P SRQ
S0
S1
D1
D2
D3
D0
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Q5.
Function Table
C INR L F S D
0 0 1 B D + B D + B
1 0 1 B D - B D - B
X 1 0 X X D + 1
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F0F1
F2
F34 XOR
GATES
Cin
FA
Co
Cin
FA
Co
Cin
FA
Co
Cin
FA
Co
I0
D0
I1D1
I2
D2I3 D3
INR Load
B0
B1
B2Register
B
B3
C
S3
S2
1 bit Full Adders
Unused
S0
S1
INR L
4 bitCounter
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