Milli-Scale Polysilicon Structures Chris Kellert , Mauro Ferrari*

Department of Materials Science and Mineral Engineeringt* Department of Civil Engineering*

University of California at Berkeley Berkeley, California 94720

ABSTRACT

Polysilicon machines composed of beams up to I JO µm high, 18 µm wide and 1000 µm long have been fabricated by CYD molding. Silicon wafers are patterned by etching trenches up to 110 µm deep to form molds of arbitrary shape. Hexagonal honeycomb geometry is used to form 3 dimensionally rigid parts. These rnilli-scale struc­tures have been integrated with surface silicon devices. After etch release, the molded parts are removed from the mold, and the mold wafers are reused to fabricate more parts. This technology has been applied to produce (1) membrane particle filters with 50 µm tall stiffening ribs, (2) 3 mm diameter, 45 to 65 µm thick, micro tensile testing machines for transmission electron microscopy, and (3) hol­low tubing, with a height to wall thickness ratio of I 05, suitable for conducting fluids.

INTRODUCTION

High aspect ratio structures that would normally be associated with

LIGA can now be made of CYD polysilicon. We call this HEXSIL

the HEXagonal honeycomb is an efficient geometry for making rigid structures with thin films, and SILicon allows conventional surface silicon micromachines and CMOS electronics to be fabri­cated in subsequent overlying layers. There has long been a need to make CYD structures of arbitrary shape with dimensions perpen­dicular to the plane of the wafer greater than 20 µm.The CYD pro­cess can only deposit thin films on surfaces. If those surfaces are the opposing faces of a deep narrow trench, the growing films will merge to form a solid beam. The thickness of the beam will be twice the thickness of the deposited film. A groove remains in the surface over the center of the trench where the films grew together (this can be smoothed by continuing to deposit beyond the time at which the sidewalls merge).

Figure I shows the basic fabrication procedure. The first step is to etch trenches in the silicon wafer. The depth of the trenches is equal to the desired height of the beams. The width of the trenches is equal to the width of the beams plus twice the thick­ness of the sacrificial oxide that is deposited in step 2. The trench volume that remains after oxide deposition, is filled with polysili­con (POLY 1) in step 3. The surface layer of polysilicon can be pat­terned if desired, but the grooves centered over the trenches make photolithography difficult. This can be remedied by lapping and polishing (step 4). A lapped and polished surface at this stage can be seen in figure 5.

The desired thickness of surface polysilicon (POLY 2) can now be deposited and patterned to make surface structures which are anchored to the HEXSIL foundation (step 5). In step 6 the sacri­ficial oxide is dissolved in 49% HF with about 0.1 % triton X-100 surfactant. The parts are removed from the wafer, and the wafer is returned to step 2 for another mold cycle. Since the same wafer can be used to mold parts many times, a wide variety of silicon machin­ing methods for trench forming would be economically viable, and several different levels of trench depth could be machined in the same wafer.

The central features of this work are:

1. Mass production of CVD parts via r,wsable molds

2. DEPOSIT SACRIFICIAL OXIDE LAYER

�(.) >­(.) "C 0 E

3. DEPOSIT POLY 1

a. Q)

- 4. LAP AND POLISH

a: w u. <(

z a: 5.

:::, w a:

REUSE MOLD WAFER·

... · . . . ·.� ............... : :-.............. ......... . .

: ; i:

Deliver finished

•

FINISHED PARTS

•

- wafer - poly 1Hi'''' sacrificial oxide liiiEI poly 2

FIGURE 1. Steps in the molding cycle. Note that the mold wafer is in an "infinite loop".

0-9640024-0-X/hh1994/$20©1994TRFDOI 10.31438/trf.hh1994.31

132 Solid-State Sensors, Actuators, and Microsystems WorkshopHilton Head Island, South Carolina, June 12-16, 1994

2. Integration of size ranges: milli-scale structures carryingmicro-scale devices which in turn support nano-scale fea­tures

3. The potential for adding electronics that conform to themolded structure in both size and mass.

Figure 2 shows a membrane particle filter (patent applied for) with nano-scale ( <100 A) pore construction (not visible) inte­rior to the 6 µm thick surface silicon which is integrated with milli­scale support ribs 48µm high, 9 µm wide, and 500 �lm long. Figure 3 shows a cross section of a stiffening rib of the filter. Lapping (pro­cessing step 4) was not done in this case. Figure 4 shows the central part of a microtensile testing machine (patent applied for) for use in the transmission electron microscope (TEM) that consists of rigid honeycomb levers connected by flexures. It is actuated by in­plane thermal expansion from resistive heating of its 3 mm diame­ter 45 µm thick support frame (see also figure 14).

This work extends the range of what is achievable by means of sidewall processing strategies. Previous workers have used side­wall structures to make micro-scale devices (ref I). Micro-scale hollow beams have also been made (ref 2). These cannot handle milli-scale forces that are of interest in many applications. Micro­scale structures have been plasma etched directly from the wafer (ref 3), but depth has been limited to less than 20 µm. Milli-scale structures have been made by wet etching silicon, but designs are highly constrained by crystallographic planes (ref 4). LIGA (refs 5,6) provides a unique path to plated metal or molded plastic struc­tures, but silicon parts cannot be made.

A technology is useful only to the extent that it can be eco­nomically integrated into a complete working system that performs a useful job. Integrated systems that can operate over the continu­ous range of forces and displacements from nano-scale to milli­scale require fabrication strategies that can yield a continuous range of machine sizes in 3 dimensions, unconstrained by crystal planes. This report offers such a strategy.

PROCEDURE

Trench etching:

Thermal oxide and CVD silicon dioxide have been used as masks. One µm of oxide is needed for each 20 µm of depth to be etched into the wafer. A LAM Research Rainbow etcher was used in plasma etching mode (power to the top electrode). The condi­tions used were 400 seem He, 180 seem Cl2 , 425 mT, 300 W, elec­trode gap 0.8 cm. The etch rate for silicon was 40 µm per hour. A 7 second SF6 pre-etch (100 seem, 200 W, 400mT, I cm gap) was used to remove any native oxide. During the chlorine etch a thin layer of white material forms on the silicon side walls. When the etch depth reaches about 45 µm, the thickness of the sidewall deposit is high enough for internal stress to make it start peeling away from the wall. This obstructs the path of ions entering the trench, and may deflect them into the sidewalls causing accelerated lateral etching. Conditions must be adjusted to maintain just enough deposit to protect the sidewalls from etching to obtain vertical side­walls deeper than 45µm. The white deposit (which is insoluble in 49% HF, 20% KOH, or 120° C piranha) can be reduced by increas­ing the chlorine concentration in the plasma (e.g., 200 seem Cl 2, 350 seem He).

Another feature of concern is the final roughness of the trench sidewalls and bottoms. After the plasma etch, the wafers are put in a tube furnace for wet oxidation at 1100° C for 2.5 hours to grow 1 micron of oxide. This is then completely removed by a 49% HF wet etch. If this smoothing treatment is not done, stress concen­trations are severe enough to cause the sacrificial oxide layer to form many tiny cracks. The surface mobility of the polysilicon dur­ing deposition allows it to fill these cracks so that very thin polysil­icon spikes are left protruding from the bottoms of the polysilicon beams.

FIGURE 2. Surface silicon membrane filter integrated with 48 µm tall molded ribs.

FIGURE 3. Cross section through filter membrane and 48 µm stiffening rib prior to etch release from the wafer.

FIGURE 4. Centr_al part of a �EXSIL microtensile testing machine 45 µm thick and 3 mm in diameter. The thin tensile specimen is visible near the center between the long straight springs.

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Smoothing has also been accomplished by timed isotropic etch with a solution of 65% nitric acid, 3% ammonium fluoride, and 32% DI water at room temperature.

An example of a mold surface that is ready for the sacrificial oxide to be deposited is shown in figure 6.

Sacrificial Oxide:

The methods that have been used to create the layer of sacri­ficial oxide are:

1. Thermal oxidation of the wafer. This consumes siliconfrom the mold, so it should only be done once for smoothing the etched surface.

2. CVD polysilicon (580" C, 65 A/min), followed by com­plete conversion of this layer to oxide by wet thermal oxidation at 1100" C. This produces a very conformal coating regardless of trench aspect ratio, and does not consume the mold. The trench can be made permanently narrower by depositing polysilicon and not oxidizing it. This allows higher aspect ratios than can be achieved directly by plasma etching.

3. CVD phosphosilicate glass (PSG) at 450" C, 140 A;minute, 8% phosphorous in the film. The thickness of the deposit decreases with depth in the trench. An anneal in nitrogen for 1 hour at 1000· C is done to densify the PSG. PSG provides a relatively fast etching layer (up to about 20 µm per minute in 49% HF).

4. CVD undoped oxide (low temperature oxide, LTO) at450' C. Conformity is comparable to that of PSG. If nonconductive polysilicon structures are needed, then a layer of LTO may be deposited over the PSG to prevent diffusion of phosphorous into the polysilicon during the stress relief anneal.

Any combination of these methods can be used depending on the requirements of the finished pan. The best dimensional toler­ances are achieved by oxidation of 580' C CVD polysilicon since it is extremely conformal with uniform thickness. A thin layer of PSG may be applied to decrease the time required for etch release. The thicker the PSG is, the greater are the dimensional variations that occur due to depleted deposition with trench depth, and surface ten­sion effects during reflow. If the densification anneal is done at 1050" C the molded parts are very smooth with specularly reflect­ing surfaces, but then a larger scale (5 to 20 ftm) waviness develops due to surface tension of the free surface of the PSG. The oxide layer shown in figure 3 was made by first growing 2.2 µm of ther­mal oxide from the mold surface. Then 1.1 µm of PSG was depos­ited,and densified at 1000" C for 1 hour in nitrogen. This provides a fast etching layer. Then 0.8 µm of CVD polysilicon was deposited at 580" C, and then completely oxidized at 1100" C in pyrogenic steam for 6 hours. It can be seen that the sharp corners at the mouth of the trench cause the PSG to increase its radius of curvature by moving material towards the center of the trench, thereby constrict­ing it. When the polysilicon is deposited to form the molded pan, it is choked off at this PSG constriction before the wider cross section down in the trench can be completely filled. This leaves a void in the middle of the beam. The thermal oxidation is not completely conformal at the trench corners either, but the major contribution to the distortion appears to be from the PSG. This should not be a problem in most structural applications.

It can be seen in figure 3 that the oxide lining is actually rougher than the walls of the etched trench. Thinner PSG and lower densification temperatures should minimize this. Oxidation of in situ phosphorous doped polysilicon may be another way to produce a fast etching layer that would be more conformal.

Polyslllcon Deposition:

All CVD polysilicon in this work was formed undoped at 580" C with a deposition rate of 0.39 µm per hour, I 00 seem silane, at 300 mT. The as-deposited film is expected to be essentially amor­phous or very fine grained (ref 7). It has high tensile stress Uudging by the cracks that open up in excessively thick deposits). Annealing

o=

ooo oooo

0000 oo

FIGURE 5. Top view after lapping back to the original wafer surface showing the tops of the single crystal silicon columns, the PSG (dark rings), and the molded polysilicon honeycomb.

FIGURE 6. Oblique view of a region of the mold wafer that forms the honeycomb structure. Etch depth is 45 µm, undercut 2 µm. Hexagonal columns are located on 25 µm centers.

.., �

FIGURE 7. T hermal expansion frame of TEM microtensile tester. View of the bottom surface of the molded polysilicon which replicates the roughness of the sacrificial oxide.

134

is required to relieve the stress before removing the parts from the wafer so that they remain straight and flat. In this work, all polysili­con anneals were done at 1000' C for I hour in nitrogen. Polysili­con film thicknesses used have ranged from 0. 9 to 8 µm. Thick films can be built up by annealing after accumulating 4 microns of growth. An attempt to grow an 8 µm thick film without an interme­diate anneal resulted in cracks through the film. The opening of the cracks indicate that the stress was highly tensile. The cracks occurred during the deposition, then as polysilicon continued to form, the fragments were welded back together sufficiently for most of the machines to be usable.

Higher deposition rates could be achieved at higher temper­atures, but the effects of larger grain size, deposition rate as a func­tion of trench depth, and concentration of impurities at the grain boundaries would have to be evaluated for each particular applica­tion.

Phosphorous Diffusion Anneal:

Additional annealing in nitrogen may be done to increase the electrical conductivity of the polysilicon by diffusing phospho­rous into it from the PSG layer. Diffusions have been done at I ooo·C and at 1050° C for one hour in the case of the tensile testing machine which works by ohmic heating and therefore must be con­ductive.

Lapping and Polishing:

The most effective way to maintain flat surfaces amenable to photo­lithography is by lapping and polishing. In this work a slurry of 0.3 µm deagglomerated gamma alumina (Buehler Inc) in glycerin was used. The films deposited on the back of the wafer should also be lapped (alternatively they can be etched) as needed to keep the wafer flat. The wafer will warp if stressed material is removed from one side only.

Etch Release:

The sacrificial oxide is dissolved with 49% HF with a sur­factant (triton X-100, at a concentration of about 0.1 %) in complete darkness. If a surfactant is not used, the released silicon surfaces are hydrophobic and will stick together to minimize contact with the aqueous solution. Enough surfactant must be present to form a monolayer on all surfaces. The use of an opaque container is a pre­caution against photon induced etching of silicon.

Mold Extraction:

The apparatus to remove the parts from the wafer in a con­trolled manner has not been fabricated as yet. Several crude meth­ods have been used for experimental purposes. The wafer can be submerged in a solution that forms gas bubbles which either float, or push the parts out. Freshly mixed piranha (5 parts sulfuric acid, 1 part 30% hydrogen peroxide) is preferred. Greater force can be obtained by soaking the wafer in saturated aqueous sodium bicar­bonate, and then immersing it in 5% aqueous acetic acid. Lower temperatures or concentrations may be used to obtain gentler action.

A layer of sticky wax, or double sided tape, may be put on a glass slide and pressed lightly against the wafer. If the slide is then pulled straight up, the devices stuck to it will be pulled out of the mold.

Molded parts with a depth of 45 µm and trench wall clear­ance of 3 µm on each side of the beams are easy to remove by these methods.

Figure 9 shows the planned strategy of etching the trenches in an n-type silicon wafer and then using photoelectrochemical etching (refs 8,9) to form straight 5 µm diameter pores extending to the back of the wafer. Pore formation should occur only at the bot­toms of the trenches since the electric field will direct the holes (generated by photons impinging on the back side of the wafer) to those locations. These pores are narrow enough to be plugged by

i

FIGURE 8. HEXSIL beam after removal from 11 O µm deep mold. A smooth surface was not maintained when etching to this depth.

Hydraulic Ejection of Molded Parts (proposed)

• wafers • poly 1□ wax •poly2

fluid passageways (photoelectrochemically etched in n-type wafer)

FIGURE 9. A proposed method for controlled removal of parts from the mold wafer.

FIGURE 10. Polysilicon structural panel with 300 µm high corrugations, and 4 µm wall thickness after removal from the mold wafer.

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1.

2. BOND WAFERS TOGETHER

■ -5. ETCH RELEASE WITH HF, AND PULL MOLD WAFERS APART

6. FINISHED PART

• wafer: single crystal siliconTh':@ sacrificial oxide• polysilicon

FIGURE 11. Method for molding tubes and vessels

seen in figure 2). These minimize stress concentrations. The designs with square

walled outer perimeters were not quite as robust. Wafer molds for filters have been put through 2 molding cycles, and there

does not seem to be any fundamental reason why they could not continue to be

used for thousands of cycles.

Tensile Testers:

10 µm relative motion between opposing levers was achieved with 120 ma 60 Hz ac (de current will be used in the TEM). This deflection of the 64 µm tall, 14

µm wide, 1000 µm long, folded spring corresponds to a calculated force of 500 µN applied to the test specimen. A design error caused one link in the mechanism to rotate about 10 degrees which wasted much of the pure translation that was desired. When this is corrected, performance should improve. The strategy of using in-plane thermal expansion is convenient since no additional materials have to be deposited. Rigidity in 3 dimensions is required since the thermal expansion is small and can be lost entirely if any part warps out of plane. The use of levers and flexures maximizes the output force available, in contrast to thermal bimorphs where one side has to stretch the other side creating internal stress at the expense

of useful force.

Structural Panels:

Figure 10 shows a structural panel after it was removed from the wafer on which it was formed. The polysilicon film is 4 µm thick, and the height of the cor­rugations is 300 µm. Continuous sheets up to 4 cm x 6 cm were produced. The mold wafer was patterned with a dicing saw. The saw can make deep trenches with smooth vertical side walls, but the pattern is limited to straight lines.

Tubing Manifolds:

Figure 12 shows a free standing rectangular polysilicon tube that could be used for conducting fluids. This was made by cutting grooves in a wafer with a dicing saw, coating it with oxide, and bonding to another oxide coated wafer, with a flat surface, to form passageways open only at the periphery of the wafer assem­bly. Figure 11 shows the general strategy for molding vessels with tubing ports.

FUTURE WORK

Figure 13 shows a proposed strategy for anchoring a layer of single crystal silicon (SCS) to the HEXSIL foundation. At this point the ass.embly looks like a conventional SOI wafer and could be processed as such to fabricate CMOS cir­cuits. The SCS layer is then patterned to leave islands of appropriate shape to con­form to the footprint of the machine. Freestanding flexible sinusoidal metallized SCS interconnects provide electrical pathways between SCS islands on different parts of the machine that will move relative to each other. After etch release from the mold wafer, this would provide a submilligram machine carrying the submilli­gram of electronics that interface it to the world. Thus the dead weight and volume of the silicon die is eliminated. The capability to produce such devices will be important in applications where mass or volume must be minimized. Figure 14

the sacrificial oxide, so polysilicon will not form in them. Then after the oxide is etched out with HF, fluid pressure applied from the back of the wafer would generate sufficient flow through the pores to carry the parts out of the mold. The overall efficiency of the molding cycle will be increased by using hydraulic ejection of parts since smaller clearances would suffice for mold extraction. Therefore a thinner layer of sacrificial oxide could be used and less time would be needed to deposit it. To preserve the organization of the parts, the front of the mold wafer may be bonded to a wax coated transfer wafer prior to etch release.

RESULTS

The fabrication strategy described above has been used to make the following:

FIiters:

Quantitative testing remains to be done, but the stiffening rib patterns most resistant to handling breakage were found to be the hexagonal ones, and the ones with a circular outer perimeter (as

FIGURE 12. Rectangular grid with 1 mm spacing of rectangular polysilicon tubing 21 O µm x 11 o µmin cross section with wall thickness of 2 µm.

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1. MECHANICAL STRUCTURES FORMED IN MOLD WAFER

JlirTI 2. BUILD SOI ASSEMBLY

3. ANCHOR SINGLE CRYSTAL LAYER TO HEXSIL

4. FABRICATE STANDARD CMOS ELECTRONICS

5. PATTERN SINGLE CRYSTAL LAYER

rr-I I

71 6. RELEASE INTEGRATED MACHINE FROM MOLD

1111 wafers - polysilicon

PSG f� thermal oxide

-·· - - -... ·· - CMOS devices

FIGURE 13. Proposed method for inte9rating microelectronics with micromechanics by eliminating the silicon die

schematically illustrates the application of this idea to the microten­sile testing machine for use in the TEM where no space is available for a die. In this case piezoresistive strain gages, wheatstone bridges, and buffers are needed on the device.

CONCLUSIONS

General methods for forming high aspect ratio CVD poly­silicon structures with reusable molds etched in silicon wafers have been demonstrated. Parts could be made from any material that deposits conformally on trench walls, and can withstand the etch release.

Substantially vertical sidewalls were achieved with depths of 45 µm. Dimensional tolerances could be held to 2 µm in any direction by taking the anticipated lateral undercut and post-etch surface smoothing of the mold into account during mask design. Additional adjustment can be made to the mold by depositing 580

°

C polysilicon onto it to make the etched trenches narrower. In appli­cations where curved sidewalls are acceptable, heights of I 10 µm have been achieved. This strategy provides the machine designer

lll!IIHEJCSIL

- 81HCll.f CRYSTAL SILICON

- POLYBaUCON ANCHORS: HEX&IL TOSINOLiCRYSTALRICON

FIGURE 14. Schematic implementation of 3 mm diameter HEXSIL micro tensile testing machine with attached CMOS layer for use in the TEM.

with a pathway to milli-scale polysilicon structures which can accommodate forces and deflections in excess of 0. I N and IO µm respectively.

The demonstrated devices are intended to be directly installed in the using system. There is no intervening device pack­aging . This improves system performance/volume, but requires careful handling prior to installation. To the extent that electronics can be built on foundations that are also mechanically functional, diverse new niches will be opened for evolving MEMS. Neural sen­sors (ref 10) are a well known example (although they do not have moving parts).

The economics of long-lived capital intensive molds that has been so successful in the plastics industry can now be utilized in CVD microfabrication.

ACKNOWLEDGEMENTS Partial support for this work was provided by the National Science Foundation,

Award number ECS 9023714, and through Mauro Ferrari's National Young Investigator Award.

The students and professors of the Berkeley Sensors and Actuator Center (BSAC) and the staff of the Berkeley Microfabrication Laboratory have been extremely helpful with technical advice.

All fabrication was done at the Berkeley Microfabrication Laboratory. REFERENCES

2

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