modern test and measure: april 2015

April 2015

Interview with Chris Armstrong

Director of Product Marketing for Rigol

Applying Multi-rate Digital Filtering

The SPI Protocol at High Frequencies

Rigol’s Advanced New Product Line Delivers on Innovation

Transforming the Industry

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CONTENTS

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READY TO LAUNCH

For the launch of the Tiva C Series Connected LaunchPad, TI has partnered with Exosite, mentioned briefly above, to provide easy access to the LaunchPad from the Internet. The LaunchPad takes about 10 minutes to set up and you can immediately interact with it across the Internet and do things like turn an LED on and off remotely from the website and see the reported temperature as well. It can also display approximate geographic location based on the assigned IP address and display a map of all other connected LaunchPad owners if they are active and plugged-in to Exosite. “In addition, it supports a basic game by enabling someone to interface to the Connected LaunchPad through a serial port from a terminal while someone else is playing with them through their browser. It is basically showing how you can interact remotely with this product and a user even if you are across the globe,” Folkens explained.

START DEVELOPING

The Tiva C Series Connected LaunchPad is shipping now and the price is right; at $19.99 USD, it is less than half the price of other Ethernet-ready kits. The LaunchPad comes complete with quick start and user guides, and ample online support to ensure developers of all backgrounds are well equipped to begin creating cloud-based applications. “We have assembled an online support team to monitor the Engineering-to-Engineering (or E2E) Community,” Folkens said. “Along with this, you also got a free Code Composer Studio Integrated Development Environment, which allows developers to use the full capability. We also support other tool chains like Keil, IAR and Mentor Embedded.

Affordable, versatile, and easy to use, the Tiva Series Connected LaunchPad is well suited for a broad audience and promises to facilitate the expansion of ingenious IoT applications in the cloud. As Folkens concluded, “The target audiences actually are the hobbyists, students and professional engineers. A better way of looking at it is that we are targeting people with innovative ideas and trying to help them get those ideas launched into the cloud.”

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CONTENTS

CONTENTS

3

4

10

2024

34

40

TECH SERIESImplementing Digital Filter Packages Multi-rate Digital Filtering for Extended Frequency Range

INDUSTRY INTERVIEWTransforming the Test IndustryInterview with Rigol’s Chris Armstrong

PRODUCT WATCHAMETEK Sorensen SG SeriesProgrammable DC Power Supplies

EEWEB FEATURESThe Basics of Ball Grid Arrays Tips for Low-volume PCB Assembly

TECH REPORTUnderstanding the SPI Protocol ConstraintsHow to Use the Protocol at 100MHz

The SG Series from AMETEK is available with two types of controls: the SGA, which uses simple analog controls, and the SGI, which includes a variety of intelligent controls, including sequencing, constant power mode, and multi-language support. Products from both series are based on a 5kW power module, with single-chassis configurations combining up to 6 to form a 30kW supply. If you need more power, you can configure up to two supplies in series or 5 supplies in parallel to act as a single supply, providing up to 150kW of DC power.

AMETEK Sorensen SG Series Programmable DC Power Supplies

Modern Test & Measure

how to apply digital filters

44


A while back, we reviewed some basics on how to

apply digital filters to sort out signals with undesirable

elements riding on top of them, i.e. a square wave that’s

being corrupted by a sinusoidal signal creeping in from

somewhere in your system design. Now, let’s look at

how to extend the range of cutoff frequencies for digital

filters, allowing them to be used even more effectively.

Applying Multi-stage, Multi-rate

By David Maliniak Technical Marketing Communication Specialist Teledyne LeCroy

DIGITAL FILTERING

http://blog.teledynelecroy.com/2014/03/using-digital-filters.html

http://blog.teledynelecroy.com/2014/03/using-digital-filters.html

5

TECH SERIES

5

A while back, we reviewed some basics on how to

apply digital filters to sort out signals with undesirable

elements riding on top of them, i.e. a square wave that’s

being corrupted by a sinusoidal signal creeping in from

somewhere in your system design. Now, let’s look at

how to extend the range of cutoff frequencies for digital

filters, allowing them to be used even more effectively.

Applying Multi-stage, Multi-rate

By David Maliniak Technical Marketing Communication Specialist Teledyne LeCroy

DIGITAL FILTERING

66


With Teledyne LeCroy’s Digital Filter Package (DFP2), users can select any of seven standard

filter types or define a custom filter for application to measured data. You can specify a range of pass-band limits and transition (roll-off) widths for any filter, which are implemented as digital finite impulse response (FIR) filters. The range of band-edge frequencies is a function of the oscilloscope’s effective sampling rate. Using the available math traces on Teledyne LeCroy oscilloscopes, you can implement multi-stage, multi-rate filters to extend the range of the DFP2 package’s filter limits. Let’s see how this works with an example of a signal (Figure 1). This is a signal you’ll commonly find in switching power-supply measurements. The measured waveform contains a 63kHz pulse-width-modulated signal riding on top of a 60Hz sine wave. Removal of the 60Hz signal requires a high-pass filter with a pass-band edge above 60Hz.

While this filter can be implemented with the DFP2 filters, doing so at a 10 Msample/s sampling rate means using filters with a very large number of taps. If we want to reduce the filter size, we must reduce the sampling rate. There are two ways to go about this. One is to reduce the length of the oscilloscope’s acquisition memory; the other is to decimate the data using the sparse math function.

Figure 1. The input signal shows both the desired 63kHz signal along with a 60Hz component. Zoom trace Z1 shows the 60Hz component in detail.

Figure 2. Shown is the series of math operations used to implement a multi-stage, multi-rate digital filter.

Using the available

math traces on Teledyne

LeCroy oscilloscopes,

you can implement

multi-stage,

multi-rate filters to

extend the range of the

DFP2 package’s

filter limits.

Reducing the sampling rate increases the possibility of aliasing the data, especially with a harmonic-rich signal like this one. To limit the possibility of aliasing, the data can be sampled at a high rate and then low-pass filtered, using a digital filter, before decimation. This combination of filtering and decimation before performing another filtering operation on the data is called “multi-stage, multi-rate” digital filtering. It allows you to reduce the effective sampling rate with minimal risk of aliasing, thus extending the usable range of the DFP2 filters.

The multi-stage, multi-rate implementation is shown in Figure 2. The upper trace is the acquired waveform sampled at 10 Msamples/s. The goal is to reduce that sampling rate by 10:1. We accomplished this by first low-pass-filtering the acquired data with a bandwidth of less than 50% of the desired effective sampling rate of 1 Msamples/s. Math trace F2 is the signal after low-pass filtering with a bandwidth of 500kHz. Math trace F3 applies the sparse math function, which is used to decimate waveform data. The decimation ratio of 10:1 is set using the Sparsing Factor variable in the Math dialog box (accessed using the Math Setup menu). The resulting decimation is 10:1 and the effective sampling rate is 1 Msamples/s.

Digital Filter Packagexxxxxx

7

TECH SERIES

7

With Teledyne LeCroy’s Digital Filter Package (DFP2), users can select any of seven standard

filter types or define a custom filter for application to measured data. You can specify a range of pass-band limits and transition (roll-off) widths for any filter, which are implemented as digital finite impulse response (FIR) filters. The range of band-edge frequencies is a function of the oscilloscope’s effective sampling rate. Using the available math traces on Teledyne LeCroy oscilloscopes, you can implement multi-stage, multi-rate filters to extend the range of the DFP2 package’s filter limits. Let’s see how this works with an example of a signal (Figure 1). This is a signal you’ll commonly find in switching power-supply measurements. The measured waveform contains a 63kHz pulse-width-modulated signal riding on top of a 60Hz sine wave. Removal of the 60Hz signal requires a high-pass filter with a pass-band edge above 60Hz.

While this filter can be implemented with the DFP2 filters, doing so at a 10 Msample/s sampling rate means using filters with a very large number of taps. If we want to reduce the filter size, we must reduce the sampling rate. There are two ways to go about this. One is to reduce the length of the oscilloscope’s acquisition memory; the other is to decimate the data using the sparse math function.

Figure 1. The input signal shows both the desired 63kHz signal along with a 60Hz component. Zoom trace Z1 shows the 60Hz component in detail.

Figure 2. Shown is the series of math operations used to implement a multi-stage, multi-rate digital filter.

Using the available

math traces on Teledyne

LeCroy oscilloscopes,

you can implement

multi-stage,

multi-rate filters to

extend the range of the

DFP2 package’s

filter limits.

Reducing the sampling rate increases the possibility of aliasing the data, especially with a harmonic-rich signal like this one. To limit the possibility of aliasing, the data can be sampled at a high rate and then low-pass filtered, using a digital filter, before decimation. This combination of filtering and decimation before performing another filtering operation on the data is called “multi-stage, multi-rate” digital filtering. It allows you to reduce the effective sampling rate with minimal risk of aliasing, thus extending the usable range of the DFP2 filters.

The multi-stage, multi-rate implementation is shown in Figure 2. The upper trace is the acquired waveform sampled at 10 Msamples/s. The goal is to reduce that sampling rate by 10:1. We accomplished this by first low-pass-filtering the acquired data with a bandwidth of less than 50% of the desired effective sampling rate of 1 Msamples/s. Math trace F2 is the signal after low-pass filtering with a bandwidth of 500kHz. Math trace F3 applies the sparse math function, which is used to decimate waveform data. The decimation ratio of 10:1 is set using the Sparsing Factor variable in the Math dialog box (accessed using the Math Setup menu). The resulting decimation is 10:1 and the effective sampling rate is 1 Msamples/s.

http://teledynelecroy.com/options/productseries.aspx?mseries=301&groupid=80

http://teledynelecroy.com/options/productseries.aspx?mseries=301&groupid=80

88


The combination

of filtering and decimation

before performing another

filtering operation on the data is

called “multi-stage, multi-rate”

digital filtering.

Figure 3. Shown is a comparison of the input and output spectra with a 40dB reduction of the 60Hz component in the lower (output) trace. The right side shows the 60Hz component before and after filtering.

In Figure 3, a comparison of the input and output frequency spectra shows that the 60Hz component has been reduced by 40dB. This can be seen in the right-hand zoom trace comparison. The high-pass filtering does not affect spectral components above 300Hz.

Math trace F4 is the setup for the high-pass filter. The cutoff frequency is 200Hz with a transition zone width of 50Hz. Note that the 60Hz component has been greatly reduced by the filtering process. With this example, we can see how multi-stage, multi-rate filtering extends the usable range of the DFP2 digital filters.

Click here

http://www.rigolna.com/

1010


PROTOCOL

By Frederic Leens (Byte Paradigm) and Alan Lowne (Saelig Company Inc.)

Understanding the constraints of using the SPI Protocol at 100MHzThe Serial Peripheral Interface (SPI) protocol is in widespread use today for chip-to-chip communications, which does not come without its challenges. SPI is not a very well defined protocol and many “flavors” of SPI coexist on the market today. SPI does not even define the clock frequency to be used—unlike a protocol such as I²C. Common frequencies for SPI are between 10MHz and 20MHz; however, with technologies like FPGAs, it is easy to choose clock frequencies that go up to 50MHz or even 100MHz, and testing a product with using a 100MHz SPI signal requires controlling the protocol parameters.

The

at Higher Frequencies

SPI

11

TECH REPORT

11

PROTOCOL

By Frederic Leens (Byte Paradigm) and Alan Lowne (Saelig Company Inc.)

Understanding the constraints of using the SPI Protocol at 100MHzThe Serial Peripheral Interface (SPI) protocol is in widespread use today for chip-to-chip communications, which does not come without its challenges. SPI is not a very well defined protocol and many “flavors” of SPI coexist on the market today. SPI does not even define the clock frequency to be used—unlike a protocol such as I²C. Common frequencies for SPI are between 10MHz and 20MHz; however, with technologies like FPGAs, it is easy to choose clock frequencies that go up to 50MHz or even 100MHz, and testing a product with using a 100MHz SPI signal requires controlling the protocol parameters.

The

at Higher Frequencies

SPI

1212


Serial Peripheral Interface (SPI): An Overview

SPI is fairly straightforward: it is a master-slave protocol scheme, with one single Master on the bus. The Master initiates the communications (read or write) with the slaves and notably sends the reference clock signal to all the slaves. It uses at least four signal lines: SCLK (clock), MOSI (Master-Out-Slave-In), MISO (Master-In-Slave-Out) and one SS (slave select) line per slave. The Master uses one clock edge to send data and the opposite edge in the same period to sample the data sent back by the slave.

The figure at the left depicts a read operation. This is the longest path from the Master to the Slave and back.

The path starts at the Master’s output. The clock signal SCLK is present at the output pin of the Master and is propagated on the (wire or trace) connection between the Master and the Slave. The Slave responds by using this clock edge (e.g. the rising edge) to provide the requested data on its MISO pin (this is “MISO @ Slave”). Between the reception of the SCLK signal at the Slave’s clock input and the moment when the requested data is present at the MISO output, there is a delay tSSCLKtoOut (‘Slave SCLK to data output’).

The data on MISO is then propagated from the Slave to the Master MISO input. The Master uses the falling edge of SCLK to sample this data [1]. With a standard SPI protocol, data is generated on one edge and sampled on the opposite edge within the same clock cycle.

The green area shows the timing budget that is available to the Master for sampling the data. This budget must be sufficient to allow the master to properly sample data, and it depends on the characteristics of the Master’s I/O and technology.

Based on the timings labeled on the picture at far left, we have the following simple expression:

TSamp = TSCLK / 2 - tprop_SCLK - tSSCLKtoOut - tprop_data

Numbers in Action

Example 1: SCLK interface at 4MHz. Master and Slave are interconnected with simple 15cm wires that have a propagation delay of 100ps/cm. The wires on the SCLK and the MISO are identical. The slave has a 6ns clock to output delay.

No problem here: there is plenty of margin, even with a slow master requiring, e.g. 5ns of setup time.

Example 2: SCLK interface at 100MHz. Master and Slave are interconnected with simple 10cm traces that have a propagation delay of 64ps/cm.

Using SPI protocol at Higher Speeds Page 1

Using the SPI Protocol At Higher Frequencies

Frederic Leens (Byte Paradigm) and Alan Lowne (Saelig Company Inc.)

Understanding the constraints of using the SPI protocol at 100MHz The Serial Peripheral Interface (SPI) protocol is in widespread use today for chip to chip communications, but it is not without its challenges. SPI is not a very well-defined protocol and many 'flavors' of SPI coexist on the market today. SPI does not even define the clock frequency to be used - unlike a protocol such as I²C. Common frequencies for SPI are between 10MHz and 20MHz. With technologies like FPGAs, it is easy to choose clock frequencies that go up to 50MHz or even 100MHz, and testing a product with using a 100 MHz SPI signal requires controlling the protocol parameters. Serial Peripheral Interface (SPI) - an overview SPI is fairly straightforward: it is a master-slave protocol scheme, with one single master on the bus. The Master initiates the communications (read or write) with the slaves and notably sends the reference clock signal to all the slaves. It uses at least 4 signal lines: SCLK (clock), MOSI (Master-Out-Slave-In), MISO (Master-In-Slave-Out) and one SS (slave select) line per slave. The master uses one clock edge to send data and the opposite edge in the same period to sample the data sent back by the slave.

The figure below depicts a read operation. This is the longest path from the master to the slave and back.


Symbol Description

TSCLK SCLK period

tprop_SCLK SCLK propagation delay from master to slave

tSSCLKtoOut Slave clock (SCLK) to output delay: delay between the clock edge at slave input and the data at the slave MISO output.

tprop_data MISO Data propagation delay from slave to master

TSamp Timing budget available to the master for sampling the read back data.

The path starts at the Master's output. The clock signal SCLK is present at the output pin of the Master and is propagated on the (wire or trace) connection between the Master and the Slave. The Slave responds by using this clock edge (e.g. the rising edge) to provide the requested data on its MISO pin: this is 'MISO @ slave'. Between the reception of the SCLK signal at the Slave's clock input and the moment when the requested data is present at the MISO output, there is a delay tSSCLKtoOut ('Slave SCLK to data output'). The data on MISO is then propagated from the Slave to the Master MISO input. The Master uses the falling edge of SCLK to sample this data1. With a standard SPI protocol, data is generated on one edge and sampled on the opposite edge within the same clock cycle. The green area shows the timing budget that is available to the Master for sampling the data. This budget must be sufficient to allow the master to properly sample data, and it depends on the characteristics of the Master's I/O and technology. Based on the timings labeled on the picture above, we have the following simple expression:


1 In reality, it can also use an internal clock signal, a delayed version of SCLK or a resynchronized version of SCLK. Of course, in this case, the timing relationship between the SCLK signal at its input and the internal clock used for sampling the data must be taken into account.


Putting some numbers in …. Example 1: SCLK interface at 4 MHz. Master and Slave are interconnected with simple 15cm wires that have a propagation delay of 100ps/cm. The wires on the SCLK and the MISO are identical. The slave has a 6ns clock to output delay.

Symbol Value

TSCLK 250 ns (= 1/(4 MHz))

tprop_SCLK 1.5 ns (= 15 x 100 ps)

tSSCLKtoOut 6 ns

tprop_data 1.5 ns

TSamp 250 /2 - 1.5 - 6 - 1.5 = 116 ns

No problem here: there is plenty of margin, even with a slow master requiring - e.g. 5ns of setup time. Example 2: SCLK interface at 100MHz. Master and Slave are interconnected with simple 10cm traces that have a propagation delay of 64ps/cm.

Symbol Value

TSCLK 10 ns

tprop_SCLK 0.64 ns

tSSCLKtoOut 6 ns

tprop_data 0.64 ns

TSamp 10 /2 - 0.64 - 6 - 0.64 = -2.28 ns (!)

The available budget is negative as seen from the waveforms:



Symbol Value

TSCLK 250 ns (= 1/(4 MHz))


tSSCLKtoOut 6 ns

tprop_data 1.5 ns

TSamp 250 /2 - 1.5 - 6 - 1.5 = 116 ns


Symbol Value

TSCLK 10 ns

tprop_SCLK 0.64 ns

tSSCLKtoOut 6 ns

tprop_data 0.64 ns

TSamp 10 /2 - 0.64 - 6 - 0.64 = -2.28 ns (!)


[1] In reality, it can also use an internal clock signal, a delayed version of SCLK or a resynchronized version of SCLK. Of course, in this case, the timing relationship between the SCLK signal at its input and the internal clock used for sampling the data must be taken into account.

13

TECH REPORT

13

Serial Peripheral Interface (SPI): An Overview

SPI is fairly straightforward: it is a master-slave protocol scheme, with one single Master on the bus. The Master initiates the communications (read or write) with the slaves and notably sends the reference clock signal to all the slaves. It uses at least four signal lines: SCLK (clock), MOSI (Master-Out-Slave-In), MISO (Master-In-Slave-Out) and one SS (slave select) line per slave. The Master uses one clock edge to send data and the opposite edge in the same period to sample the data sent back by the slave.

The figure at the left depicts a read operation. This is the longest path from the Master to the Slave and back.

The path starts at the Master’s output. The clock signal SCLK is present at the output pin of the Master and is propagated on the (wire or trace) connection between the Master and the Slave. The Slave responds by using this clock edge (e.g. the rising edge) to provide the requested data on its MISO pin (this is “MISO @ Slave”). Between the reception of the SCLK signal at the Slave’s clock input and the moment when the requested data is present at the MISO output, there is a delay tSSCLKtoOut (‘Slave SCLK to data output’).

The data on MISO is then propagated from the Slave to the Master MISO input. The Master uses the falling edge of SCLK to sample this data [1]. With a standard SPI protocol, data is generated on one edge and sampled on the opposite edge within the same clock cycle.

The green area shows the timing budget that is available to the Master for sampling the data. This budget must be sufficient to allow the master to properly sample data, and it depends on the characteristics of the Master’s I/O and technology.

Based on the timings labeled on the picture at far left, we have the following simple expression:


Numbers in Action

Example 1: SCLK interface at 4MHz. Master and Slave are interconnected with simple 15cm wires that have a propagation delay of 100ps/cm. The wires on the SCLK and the MISO are identical. The slave has a 6ns clock to output delay.

No problem here: there is plenty of margin, even with a slow master requiring, e.g. 5ns of setup time.

Example 2: SCLK interface at 100MHz. Master and Slave are interconnected with simple 10cm traces that have a propagation delay of 64ps/cm.


Using the SPI Protocol At Higher Frequencies

Frederic Leens (Byte Paradigm) and Alan Lowne (Saelig Company Inc.)

Understanding the constraints of using the SPI protocol at 100MHz The Serial Peripheral Interface (SPI) protocol is in widespread use today for chip to chip communications, but it is not without its challenges. SPI is not a very well-defined protocol and many 'flavors' of SPI coexist on the market today. SPI does not even define the clock frequency to be used - unlike a protocol such as I²C. Common frequencies for SPI are between 10MHz and 20MHz. With technologies like FPGAs, it is easy to choose clock frequencies that go up to 50MHz or even 100MHz, and testing a product with using a 100 MHz SPI signal requires controlling the protocol parameters. Serial Peripheral Interface (SPI) - an overview SPI is fairly straightforward: it is a master-slave protocol scheme, with one single master on the bus. The Master initiates the communications (read or write) with the slaves and notably sends the reference clock signal to all the slaves. It uses at least 4 signal lines: SCLK (clock), MOSI (Master-Out-Slave-In), MISO (Master-In-Slave-Out) and one SS (slave select) line per slave. The master uses one clock edge to send data and the opposite edge in the same period to sample the data sent back by the slave.

The figure below depicts a read operation. This is the longest path from the master to the slave and back.


Symbol Description

TSCLK SCLK period

tprop_SCLK SCLK propagation delay from master to slave

tSSCLKtoOut Slave clock (SCLK) to output delay: delay between the clock edge at slave input and the data at the slave MISO output.

tprop_data MISO Data propagation delay from slave to master

TSamp Timing budget available to the master for sampling the read back data.

The path starts at the Master's output. The clock signal SCLK is present at the output pin of the Master and is propagated on the (wire or trace) connection between the Master and the Slave. The Slave responds by using this clock edge (e.g. the rising edge) to provide the requested data on its MISO pin: this is 'MISO @ slave'. Between the reception of the SCLK signal at the Slave's clock input and the moment when the requested data is present at the MISO output, there is a delay tSSCLKtoOut ('Slave SCLK to data output'). The data on MISO is then propagated from the Slave to the Master MISO input. The Master uses the falling edge of SCLK to sample this data1. With a standard SPI protocol, data is generated on one edge and sampled on the opposite edge within the same clock cycle. The green area shows the timing budget that is available to the Master for sampling the data. This budget must be sufficient to allow the master to properly sample data, and it depends on the characteristics of the Master's I/O and technology. Based on the timings labeled on the picture above, we have the following simple expression:


1 In reality, it can also use an internal clock signal, a delayed version of SCLK or a resynchronized version of SCLK. Of course, in this case, the timing relationship between the SCLK signal at its input and the internal clock used for sampling the data must be taken into account.



Symbol Value

TSCLK 250 ns (= 1/(4 MHz))


tSSCLKtoOut 6 ns

tprop_data 1.5 ns

TSamp 250 /2 - 1.5 - 6 - 1.5 = 116 ns


Symbol Value

TSCLK 10 ns

tprop_SCLK 0.64 ns

tSSCLKtoOut 6 ns

tprop_data 0.64 ns

TSamp 10 /2 - 0.64 - 6 - 0.64 = -2.28 ns (!)




Symbol Value

TSCLK 250 ns (= 1/(4 MHz))


tSSCLKtoOut 6 ns

tprop_data 1.5 ns

TSamp 250 /2 - 1.5 - 6 - 1.5 = 116 ns


Symbol Value

TSCLK 10 ns

tprop_SCLK 0.64 ns

tSSCLKtoOut 6 ns

tprop_data 0.64 ns

TSamp 10 /2 - 0.64 - 6 - 0.64 = -2.28 ns (!)


[1] In reality, it can also use an internal clock signal, a delayed version of SCLK or a resynchronized version of SCLK. Of course, in this case, the timing relationship between the SCLK signal at its input and the internal clock used for sampling the data must be taken into account.

1414


Option 2: Slow the bus down until sufficient margin is available. If the Master requires at least 2ns of setup time to properly sample the data, we can deduce the bus maximum frequency of operation:

By reversing the expression and replacing tSamp by the minimum setup time (tsetup):

TSCLK ≥ 2x (tsetup + tprop_SLCK + tSSCLKtoOut + tprop_data)

TSCLK ≥ 2x (2 + 0.64 + 6 + 0.64) = 18.56ns

This means that the SCLK frequency can be at max: 1/ 18.56ns = 53.87MHz if a “pure SPI” protocol has to be used with the provided system.

Option 3: Use another Master edge for sampling data. As seen on the diagram above, the next rising edge probably has sufficient timing margin to sample the data. Calculating the timing budget for this edge:

TSamp (Next rising edge) = TSCLK / 2 + TSamp

TSamp (Next rising edge) = 5 - 2.28 = 2.72ns

The next rising edge can indeed be used for sampling if, for instance, the Master needs at least 2ns of margin to sample data.

This option should be considered as viable. The purpose of going for higher bus speeds is all about getting a larger bandwidth for transmitting data. There are many components like memory, DACs and ADCs on the market today that already “tweak” the protocol slightly in order to get more total throughput.


So, the transition on MISO occurs 2.28ns after the SPI conventional sampling edge. The higher interface frequency does not allow the use of a standard SPI protocol because the total timing budget is insufficient for the selected connections and slave characteristics.

Which options are there to ensure proper sampling at this speed?

Option 1: Shorten the connections and find a Slave with a shorter clock to output delay (such a “faster slave” may simply not be available). Using shorter or “faster” connections will also have a very limited impact because this is the smallest share of the “missing” timing budget.



Symbol Value

TSCLK 250 ns (= 1/(4 MHz))


tSSCLKtoOut 6 ns

tprop_data 1.5 ns

TSamp 250 /2 - 1.5 - 6 - 1.5 = 116 ns


Symbol Value

TSCLK 10 ns

tprop_SCLK 0.64 ns

tSSCLKtoOut 6 ns

tprop_data 0.64 ns

TSamp 10 /2 - 0.64 - 6 - 0.64 = -2.28 ns (!)


15

TECH REPORT

15

Option 2: Slow the bus down until sufficient margin is available. If the Master requires at least 2ns of setup time to properly sample the data, we can deduce the bus maximum frequency of operation:

By reversing the expression and replacing tSamp by the minimum setup time (tsetup):

TSCLK ≥ 2x (tsetup + tprop_SLCK + tSSCLKtoOut + tprop_data)

TSCLK ≥ 2x (2 + 0.64 + 6 + 0.64) = 18.56ns

This means that the SCLK frequency can be at max: 1/ 18.56ns = 53.87MHz if a “pure SPI” protocol has to be used with the provided system.

Option 3: Use another Master edge for sampling data. As seen on the diagram above, the next rising edge probably has sufficient timing margin to sample the data. Calculating the timing budget for this edge:

TSamp (Next rising edge) = TSCLK / 2 + TSamp

TSamp (Next rising edge) = 5 - 2.28 = 2.72ns

The next rising edge can indeed be used for sampling if, for instance, the Master needs at least 2ns of margin to sample data.

This option should be considered as viable. The purpose of going for higher bus speeds is all about getting a larger bandwidth for transmitting data. There are many components like memory, DACs and ADCs on the market today that already “tweak” the protocol slightly in order to get more total throughput.


So, the transition on MISO occurs 2.28ns after the SPI conventional sampling edge. The higher interface frequency does not allow the use of a standard SPI protocol because the total timing budget is insufficient for the selected connections and slave characteristics.

Which options are there to ensure proper sampling at this speed?

Option 1: Shorten the connections and find a Slave with a shorter clock to output delay (such a “faster slave” may simply not be available). Using shorter or “faster” connections will also have a very limited impact because this is the smallest share of the “missing” timing budget.



Symbol Value

TSCLK 250 ns (= 1/(4 MHz))


tSSCLKtoOut 6 ns

tprop_data 1.5 ns

TSamp 250 /2 - 1.5 - 6 - 1.5 = 116 ns


Symbol Value

TSCLK 10 ns

tprop_SCLK 0.64 ns

tSSCLKtoOut 6 ns

tprop_data 0.64 ns

TSamp 10 /2 - 0.64 - 6 - 0.64 = -2.28 ns (!)


1616


Going Further

Consider a very poorly designed system, with large propagation delays on the wires and a “slave-clock-to-output” time as large as 8ns, keeping a 100MHz working frequency. The “clock-to-output” delay takes 80% of a clock period and will certainly create problems for a “pure SPI” protocol.

Example 3: SCLK interface at 100MHz; Master and Slave are interconnected with simple 15cm traces that have a propagation delay of 100ps/cm. Slave “clock-to-output” is 8ns.

From the diagram above, it can readily be seen that the data can’t be sampled by the clock falling edge, as it is usually defined for SPI. However, in addition, the data is ready for sampling at the input of the Master only 6ns after this edge, i.e. 1ns after the next rising edge of the clock. The first clock edge available for sampling at the Master input is the next clock period’s falling edge, with a margin as large as 4ns.

In order to adequately test SPI protocols at various clock speeds, it may be essential to use a serial protocol adapter that can accommodate custom SPI variations. Byte Paradigm’s SPI Storm is a USB-connected PC-based serial protocol host adapter useful for functional testing on systems using SPI and many other serial protocols. SPI Storm operates at up to 100MHz and notably includes a custom protocol definition engine that provides full control of data sampling times sample data from any “SPI-like” Slave and handle the situations described above.

Conclusions

Keeping a sufficient timing margin for sampling data on an SPI interface is not an easy task when the interface’s clock is in the 100MHz range. The “standard SPI” interface protocol, which specifies generating data on one edge of the SCLK and sampling data on the opposite edge within the same period is actually quite a tough constraint at higher speeds. But using a faster clock is desirable in order to reach higher data throughput using a serial protocol, and the technologies available on the market today are certainly able to handle such speeds. For this reason, many non-standard serial protocols derived from SPI are commonly used today. One of the main solutions for being able to use clock frequencies as high as 100MHz consists in sampling Readback data during the next clock period in order to give sufficient time to the Slave to respond—and still keep a communication scheme where the reference clock is provided by the Master.


So the transition on MISO occurs 2.28 ns after the SPI conventional sampling edge. The higher interface frequency does not allow the use of a standard SPI protocol because the total timing budget is insufficient for the selected connections and slave characteristics. Which options are there to ensure proper sampling at this speed? Option 1: Shorten the connections and find a Slave with a shorter clock to output delay (such a 'faster slave' may simply not be available). Using shorter or 'faster' connections will also have a very limited impact because this is the smallest share of the 'missing' timing budget. Option 2: Slow the bus down until sufficient margin is available. If the Master requires at least 2 ns of setup time to properly sample the data, we can deduce the bus maximum frequency of operation: By reversing the expression and replacing tSamp by the minimum setup time (tsetup):

TSCLK ≥ 2 x (tsetup + tprop_SLCK + tSSCLKtoOut + tprop_data)

TSCLK ≥ 2x (2 + 0.64 + 6 + 0.64) = 18.56 ns This means that the SCLK frequency can be at max: 1/ 18.56 ns = 53.87 MHz if a 'pure SPI' protocol has to be used with the provided system. Option 3: Use another Master edge for sampling data. As seen on the diagram above, the next rising edge probably has sufficient timing margin to sample the data. Calculating the timing budget for this edge:

TSamp (Next rising edge) = TSCLK / 2 + TSamp TSamp (Next rising edge) = 5 - 2.28 = 2.72 ns

The next rising edge can indeed be used for sampling if, for instance, the Master needs at least 2 ns of margin to sample data. This option should be considered as viable. The purpose of going for higher bus speeds is all about getting a larger bandwidth for transmitting data. There are many components like memory, DACs and ADCs on the market today that already 'tweak' the protocol slightly in order to get more total throughput. Going further … Consider a very poorly designed system, with large propagation delays on the wires and a 'slave clock to output' time as large as 8 ns, keeping a 100 MHz working frequency. The „clock to output‟ delay takes 80% of a clock period and will certainly create problems for a 'pure SPI' protocol. Example 3: SCLK interface at 100 MHz; Master and Slave are interconnected with simple 15 cm traces that have a propagation delay of 100ps/cm. Slave „clock to output‟ is 8 ns.

Symbol Value

TSCLK 10 ns

tprop_SCLK 1.5 ns


tSSCLKtoOut 8 ns

tprop_data 1.5 ns

TSamp 10 /2 - 1.5 - 8 - 1.5 = -6 ns (!)

From the diagram above, it can readily be seen that the data can't be sampled by the clock falling edge, as it is usually defined for SPI, but, in addition, the data is ready for sampling at the input of the Master only 6 ns after this edge, i.e. 1 ns after the next rising edge of the clock. The first clock edge available for sampling at the master input is the next clock period's falling edge, with a margin as large as 4 ns. In order to adequately test SPI protocols at various clock speeds, it may be essential to use a serial protocol adapter that can accommodate custom SPI variations. Byte Paradigm's SPI Storm is a USB-connected PC-based serial protocol host adapter useful for functional testing on systems using SPI and many other serial protocols. SPI Storm operates at up to 100 MHz and notably includes a custom protocol definition engine that provides full control of data sampling times sample data from any “SPI-like” slave and handle the situations described above. Conclusions Keeping a sufficient timing margin for sampling data on an SPI interface is not an easy task when the interface's clock is in the 100 MHz range. The 'standard SPI' interface protocol which specifies generating data on one edge of the SCLK and sampling data on the opposite edge within the same period is actually quite a tough constraint at higher speeds. But using a faster clock is desirable in order to reach higher data throughput using a serial protocol, and the technologies available on the market today are well able to handle such speeds. For this reason, many non-standard serial protocols derived from SPI are commonly used today. One of the main solutions for being able to use clock frequencies as high as 100 MHz consists in sampling Readback data during the next clock period in order to give sufficient time to the Slave to respond - and still keep a communication scheme where the reference clock is provided by the Master.


tSSCLKtoOut 8 ns

tprop_data 1.5 ns

TSamp 10 /2 - 1.5 - 8 - 1.5 = -6 ns (!)


17

TECH REPORT

17

Going Further

Consider a very poorly designed system, with large propagation delays on the wires and a “slave-clock-to-output” time as large as 8ns, keeping a 100MHz working frequency. The “clock-to-output” delay takes 80% of a clock period and will certainly create problems for a “pure SPI” protocol.

Example 3: SCLK interface at 100MHz; Master and Slave are interconnected with simple 15cm traces that have a propagation delay of 100ps/cm. Slave “clock-to-output” is 8ns.

From the diagram above, it can readily be seen that the data can’t be sampled by the clock falling edge, as it is usually defined for SPI. However, in addition, the data is ready for sampling at the input of the Master only 6ns after this edge, i.e. 1ns after the next rising edge of the clock. The first clock edge available for sampling at the Master input is the next clock period’s falling edge, with a margin as large as 4ns.

In order to adequately test SPI protocols at various clock speeds, it may be essential to use a serial protocol adapter that can accommodate custom SPI variations. Byte Paradigm’s SPI Storm is a USB-connected PC-based serial protocol host adapter useful for functional testing on systems using SPI and many other serial protocols. SPI Storm operates at up to 100MHz and notably includes a custom protocol definition engine that provides full control of data sampling times sample data from any “SPI-like” Slave and handle the situations described above.

Conclusions

Keeping a sufficient timing margin for sampling data on an SPI interface is not an easy task when the interface’s clock is in the 100MHz range. The “standard SPI” interface protocol, which specifies generating data on one edge of the SCLK and sampling data on the opposite edge within the same period is actually quite a tough constraint at higher speeds. But using a faster clock is desirable in order to reach higher data throughput using a serial protocol, and the technologies available on the market today are certainly able to handle such speeds. For this reason, many non-standard serial protocols derived from SPI are commonly used today. One of the main solutions for being able to use clock frequencies as high as 100MHz consists in sampling Readback data during the next clock period in order to give sufficient time to the Slave to respond—and still keep a communication scheme where the reference clock is provided by the Master.


So the transition on MISO occurs 2.28 ns after the SPI conventional sampling edge. The higher interface frequency does not allow the use of a standard SPI protocol because the total timing budget is insufficient for the selected connections and slave characteristics. Which options are there to ensure proper sampling at this speed? Option 1: Shorten the connections and find a Slave with a shorter clock to output delay (such a 'faster slave' may simply not be available). Using shorter or 'faster' connections will also have a very limited impact because this is the smallest share of the 'missing' timing budget. Option 2: Slow the bus down until sufficient margin is available. If the Master requires at least 2 ns of setup time to properly sample the data, we can deduce the bus maximum frequency of operation: By reversing the expression and replacing tSamp by the minimum setup time (tsetup):

TSCLK ≥ 2 x (tsetup + tprop_SLCK + tSSCLKtoOut + tprop_data)

TSCLK ≥ 2x (2 + 0.64 + 6 + 0.64) = 18.56 ns This means that the SCLK frequency can be at max: 1/ 18.56 ns = 53.87 MHz if a 'pure SPI' protocol has to be used with the provided system. Option 3: Use another Master edge for sampling data. As seen on the diagram above, the next rising edge probably has sufficient timing margin to sample the data. Calculating the timing budget for this edge:

TSamp (Next rising edge) = TSCLK / 2 + TSamp TSamp (Next rising edge) = 5 - 2.28 = 2.72 ns

The next rising edge can indeed be used for sampling if, for instance, the Master needs at least 2 ns of margin to sample data. This option should be considered as viable. The purpose of going for higher bus speeds is all about getting a larger bandwidth for transmitting data. There are many components like memory, DACs and ADCs on the market today that already 'tweak' the protocol slightly in order to get more total throughput. Going further … Consider a very poorly designed system, with large propagation delays on the wires and a 'slave clock to output' time as large as 8 ns, keeping a 100 MHz working frequency. The „clock to output‟ delay takes 80% of a clock period and will certainly create problems for a 'pure SPI' protocol. Example 3: SCLK interface at 100 MHz; Master and Slave are interconnected with simple 15 cm traces that have a propagation delay of 100ps/cm. Slave „clock to output‟ is 8 ns.

Symbol Value

TSCLK 10 ns

tprop_SCLK 1.5 ns


tSSCLKtoOut 8 ns

tprop_data 1.5 ns

TSamp 10 /2 - 1.5 - 8 - 1.5 = -6 ns (!)



tSSCLKtoOut 8 ns

tprop_data 1.5 ns

TSamp 10 /2 - 1.5 - 8 - 1.5 = -6 ns (!)


Click here

Click here

http://www.saelig.com

www.siglentamerica.com

Keysight

www.keysight.com/find/triggerchallenge


2020

Ball grid arrays are the boon and bane of engineers and printed circuit board designers all over the world. Their unparalleled pin

density and low-lead inductance are essential in today’s high pin count, high-frequency integrated circuits. However, that same pin density and unique interface create a challenge unique unto themselves. These challenges need to be faced head on since the ball grid array (BGA) is prevalent in modern PCBs. While there are entire textbooks that cover the topic of BGAs, their use, and their fanout techniques, the quick overview provided here offers a good starting point for improving BGA designs.

Basics of

BALL GRID

(BGAs)ARRAYS

2121

EE WEB FEATURE

Ball grid arrays are the boon and bane of engineers and printed circuit board designers all over the world. Their unparalleled pin

density and low-lead inductance are essential in today’s high pin count, high-frequency integrated circuits. However, that same pin density and unique interface create a challenge unique unto themselves. These challenges need to be faced head on since the ball grid array (BGA) is prevalent in modern PCBs. While there are entire textbooks that cover the topic of BGAs, their use, and their fanout techniques, the quick overview provided here offers a good starting point for improving BGA designs.

Basics of

BALL GRID

(BGAs)ARRAYS


2222

While the basic BGA concept has remained the same, they have been changing in dimensions since their introduction, with smaller pitches and smaller outlines. Certain BGAs have no connections in the center, while others have pins all across the bottom of the package. For simpler BGAs, with greater pitch and space in the middle of the BGA, manual routing can be accomplished without creating a breakout pattern. As the pitch decreases and pin count goes up, the amount of connections required makes the semi-random placement of traces unfeasible. While increasing layers of the board can be a shortcut to make it simpler to route the traces, this creates increased cost and greater reliability concerns, which should be avoided. If it is possible to reduce the layer requirements by more thoughtful layouts, then do so, only increasing the layer count as a last option.

As the different ball patterns on the board give rise to different optimal fanouts or escape routing, it’s important

to carefully look at the patterns and ask various questions; How far apart are the balls? Are they parallel and equidistant, or do they have greater spacing in one direction? Does the pattern change? What is your minimum trace width and spacing? With answers to these questions in hand, you can either decide on how to best approach the fanout yourself, or you can turn to the Internet to see if someone else has already developed a solution to this problem.

Due to their complex nature, BGAs are heavily dependent on vias, and it is essential to know how and where to use them. Where possible, to save money and increase reliability, you should use mechanical drilling for the vias. However, this has the drawback of creating a hole through all layers of the board when you may only want to connect to one or two layers. Blind microvias give you the option of only drilling down to the layer needed, or you can use laminated buried vias that can be used to change layers within the PCB. Unfortunately, this technology is expensive and unreliable. Yet, at times, it’s indispensable. If it is not possible to properly breakout the BGA, contact your PCB manufacturer to ask about the company’s capabilities and cost for microvias.

A BGA, having the leads beneath the package itself, is most easily soldered using a reflow process. Small balls of solder are attached to the part itself by the manufacturer which, when flowed, create the electrical and physical connection between the BGA and the PCB. Most assembly houses use automated X-ray inspection (AXI) to verify the solder joints since there is no other way to see the connections.

The pads for BGAs typically fall under two styles, solder mask defined pads and non-solder mask defined pads. The biggest difference is whether the solder mask encroaches on the pad or not. Generally, non-solder mask defined pads are recommended because of the increased surface area for bonding, however the solder mask defined pads decrease the chance of bridging and may be needed with smaller pitches.

Despite the complexity and difficulty inherent with the use of BGAs, the increased performance and space savings frequently merit the challenges and potential headaches. As with all processes, time and practice will make the challenge of BGA design a second-nature skill that will become invaluable.

Advanced Assembly was founded to help engineers assemble their prototype and low-volume PCB orders. Based on years of experience within the printed circuit board industry, Advanced Assembly developed a proprietary system to deliver consistent, machine surface mount technology (SMT) assembly in 1-5 days. It’s our only focus. We take the hassle out of PCB assembly and make it easy, so you can spend time on other aspects of your design.

20100 E. 32nd Pkwy #225 | Aurora, CO 80011 | www.aapcb.com | 1-800-838-5650

“Due to their complex nature, BGAs are heavily dependent on vias, and it is essential to know how and where to use them.”

“While the basic BGA concept has remained the same, they have been changing in dimensions since their introduction, with smaller pitches and smaller outlines.”

www.aapcb.com

2323

EE WEB FEATURE

While the basic BGA concept has remained the same, they have been changing in dimensions since their introduction, with smaller pitches and smaller outlines. Certain BGAs have no connections in the center, while others have pins all across the bottom of the package. For simpler BGAs, with greater pitch and space in the middle of the BGA, manual routing can be accomplished without creating a breakout pattern. As the pitch decreases and pin count goes up, the amount of connections required makes the semi-random placement of traces unfeasible. While increasing layers of the board can be a shortcut to make it simpler to route the traces, this creates increased cost and greater reliability concerns, which should be avoided. If it is possible to reduce the layer requirements by more thoughtful layouts, then do so, only increasing the layer count as a last option.

As the different ball patterns on the board give rise to different optimal fanouts or escape routing, it’s important

to carefully look at the patterns and ask various questions; How far apart are the balls? Are they parallel and equidistant, or do they have greater spacing in one direction? Does the pattern change? What is your minimum trace width and spacing? With answers to these questions in hand, you can either decide on how to best approach the fanout yourself, or you can turn to the Internet to see if someone else has already developed a solution to this problem.

Due to their complex nature, BGAs are heavily dependent on vias, and it is essential to know how and where to use them. Where possible, to save money and increase reliability, you should use mechanical drilling for the vias. However, this has the drawback of creating a hole through all layers of the board when you may only want to connect to one or two layers. Blind microvias give you the option of only drilling down to the layer needed, or you can use laminated buried vias that can be used to change layers within the PCB. Unfortunately, this technology is expensive and unreliable. Yet, at times, it’s indispensable. If it is not possible to properly breakout the BGA, contact your PCB manufacturer to ask about the company’s capabilities and cost for microvias.

A BGA, having the leads beneath the package itself, is most easily soldered using a reflow process. Small balls of solder are attached to the part itself by the manufacturer which, when flowed, create the electrical and physical connection between the BGA and the PCB. Most assembly houses use automated X-ray inspection (AXI) to verify the solder joints since there is no other way to see the connections.

The pads for BGAs typically fall under two styles, solder mask defined pads and non-solder mask defined pads. The biggest difference is whether the solder mask encroaches on the pad or not. Generally, non-solder mask defined pads are recommended because of the increased surface area for bonding, however the solder mask defined pads decrease the chance of bridging and may be needed with smaller pitches.

Despite the complexity and difficulty inherent with the use of BGAs, the increased performance and space savings frequently merit the challenges and potential headaches. As with all processes, time and practice will make the challenge of BGA design a second-nature skill that will become invaluable.



“Due to their complex nature, BGAs are heavily dependent on vias, and it is essential to know how and where to use them.”

“While the basic BGA concept has remained the same, they have been changing in dimensions since their introduction, with smaller pitches and smaller outlines.”

http://www.aapcb.com


2424

Design-for-manufacturing (DFM) is a well-known term and an essential part of the design process. Perhaps just as important, yet not as well-known, is the

concept of design-for-assembly (DFA). If you optimize your circuit board so that it is produced flawlessly, but make it so the board can only be assembled by tedious hand soldering, then you have saved cents per board on manufacturing just to increase the cost by dollars per board on assembly. To avoid this, both the manufacturing and the assembly need to be taken into account during the design phase. Fortunately, there is generally no need to compromise between manufacturing or assembly, and in most cases you should be able to design a board that is both highly manufacturable and easily assembled. The first step in being able to design-for-assembly is to understand the assembly process. This process will be discussed in depth to show how a board goes from an unpopulated printed circuit board (PCB) to a final product, ready to be packaged and sent to consumers.

Assembly Methods

PCB

2525

EE WEB FEATURE

Design-for-manufacturing (DFM) is a well-known term and an essential part of the design process. Perhaps just as important, yet not as well-known, is the

concept of design-for-assembly (DFA). If you optimize your circuit board so that it is produced flawlessly, but make it so the board can only be assembled by tedious hand soldering, then you have saved cents per board on manufacturing just to increase the cost by dollars per board on assembly. To avoid this, both the manufacturing and the assembly need to be taken into account during the design phase. Fortunately, there is generally no need to compromise between manufacturing or assembly, and in most cases you should be able to design a board that is both highly manufacturable and easily assembled. The first step in being able to design-for-assembly is to understand the assembly process. This process will be discussed in depth to show how a board goes from an unpopulated printed circuit board (PCB) to a final product, ready to be packaged and sent to consumers.

Assembly Methods

PCB


2626

x

Y

S

R

The first absolutely critical step of the assembly process happens before the PCBs have been manufactured; the first step is to contact your assembly house and talk to them about the project. Communication should be a constant throughout the life of the product with continual feedback and discussion between the two parties. While we will discuss the general processes of an assembly, each house will have its own methods, strengths, and requirements that you should become familiar with and either prepare for or take advantage of. Depending on the assembly house, you will likely be assigned an account manager who will help you interface with different members of the team as necessary. If possible, go visit the assembly house in person, meet the team, and look at the process. This is a great time to get a feel for a company, its staff responsiveness, and professionalism. Take a look at the production floor and check to make sure that proper electrostatic discharge (ESD) precautions are taken, that current projects are organized, and that the overall facility is clean of dust, debris, and chemicals. Long delays in communication, conflicting feedback from different members of the team, or disorganized facilities are signs that you may have trouble later on.

In preparation to submit your boards for assembly, there are certain items that you need to provide to the assembly house so they know what to do once they receive your boards. The first is

your bill of materials (BOM), which should include part number, description, value, reference number, and package type. It is advised that this information be complete and accurate or the assembly house will almost certainly place parts in the wrong places. If there is something that looks odd to them, a good assembly house will stop and ask for clarification. However, most small inaccuracies, perhaps an unintentional swap of a 100K and 100 ohm resistor that are both 0402 packages, will not be something they can catch. Besides the BOM, an X-Y-rotation-side (XYRS), or centroid, file will be required for most assembly houses. The XYRS file contains the X- and Y- coordinates, rotational angle, and which side of the board each part is placed. This information is used by the pick-and-place machine for SMT components. Nearly all computer-aided design (CAD) programs for PCB design will be able to export the XYRS file directly, and those that cannot will likely have a module or extension that will give them the capability. Finally, the Gerber files for your board should be included in your submission to the assembly house. Specifically needed are the copper files, silkscreen, and solder paste for both sides of the board. The silkscreen helps with orientation of which way is up, the copper tell the engineers how to line up the XYRS information, and the solder paste allows them to create a solder stencil if necessary. While not always necessary, it is helpful to include fiducials either on the entire panel of PCBs, or if being done board by board, fiducials on the individual boards. For most boards, these three files

are all that is necessary to assemble a board. However, an assembly drawing may be needed to complete the board if there are special instructions (board marking, special mounting, etc.)

Once the assembly house has received all of the requisite information, they will begin by reviewing what they have been sent. They will catch more obvious errors and work with you to get them resolved. A few assembly companies run designs through internally developed verification software, which use the aforementioned manufacturing files to create digital images of a design and help catch part-to-footprint errors. Then, depending on if it is a turn-key process, they can order parts and/or boards on your behalf. If ordering assembly only, you will need to ship them the boards and the parts, making sure to provide the appropriate overages. Again, proper paperwork and labelling is crucial. If your BOM and board match each other with the appropriate reference designators, but you mislabel the parts when providing them, there will, at best, be delays. At worst, the entire run can require rework, considerably

increasing assembly costs. Check with the assembler for kitting checklists or recommended best practices. Some companies will even send you custom kitting labels free of charge to help with accurate kit preparation.

Pick-and-Place Machines

The physical process at the assembly starts with setting up the pick-and-place machines. This involves loading the XYRS files and all of the different parts into the machines. Reels and trays are manually loaded and some pick-and-place machines can even accept cut tape. Certain assembly houses will hand populate a board and then scan that into the pick-and-place machines to “teach” them the correct locations of the different parts. While this is effective, it takes even longer and can sometimes lead to large setup costs. For small runs, some assembly houses will use hand placement for every board. This is very time consuming and creates inconsistency for both solder-paste application and component placement. There are a few companies that specialize in machine-assembling low-quantity

“Communication should be a constant throughout the life of the product with continual feedback and discussion between the two parties.”

XYRS Information

2727

EE WEB FEATURE

x

Y

S

R

The first absolutely critical step of the assembly process happens before the PCBs have been manufactured; the first step is to contact your assembly house and talk to them about the project. Communication should be a constant throughout the life of the product with continual feedback and discussion between the two parties. While we will discuss the general processes of an assembly, each house will have its own methods, strengths, and requirements that you should become familiar with and either prepare for or take advantage of. Depending on the assembly house, you will likely be assigned an account manager who will help you interface with different members of the team as necessary. If possible, go visit the assembly house in person, meet the team, and look at the process. This is a great time to get a feel for a company, its staff responsiveness, and professionalism. Take a look at the production floor and check to make sure that proper electrostatic discharge (ESD) precautions are taken, that current projects are organized, and that the overall facility is clean of dust, debris, and chemicals. Long delays in communication, conflicting feedback from different members of the team, or disorganized facilities are signs that you may have trouble later on.

In preparation to submit your boards for assembly, there are certain items that you need to provide to the assembly house so they know what to do once they receive your boards. The first is

your bill of materials (BOM), which should include part number, description, value, reference number, and package type. It is advised that this information be complete and accurate or the assembly house will almost certainly place parts in the wrong places. If there is something that looks odd to them, a good assembly house will stop and ask for clarification. However, most small inaccuracies, perhaps an unintentional swap of a 100K and 100 ohm resistor that are both 0402 packages, will not be something they can catch. Besides the BOM, an X-Y-rotation-side (XYRS), or centroid, file will be required for most assembly houses. The XYRS file contains the X- and Y- coordinates, rotational angle, and which side of the board each part is placed. This information is used by the pick-and-place machine for SMT components. Nearly all computer-aided design (CAD) programs for PCB design will be able to export the XYRS file directly, and those that cannot will likely have a module or extension that will give them the capability. Finally, the Gerber files for your board should be included in your submission to the assembly house. Specifically needed are the copper files, silkscreen, and solder paste for both sides of the board. The silkscreen helps with orientation of which way is up, the copper tell the engineers how to line up the XYRS information, and the solder paste allows them to create a solder stencil if necessary. While not always necessary, it is helpful to include fiducials either on the entire panel of PCBs, or if being done board by board, fiducials on the individual boards. For most boards, these three files

are all that is necessary to assemble a board. However, an assembly drawing may be needed to complete the board if there are special instructions (board marking, special mounting, etc.)

Once the assembly house has received all of the requisite information, they will begin by reviewing what they have been sent. They will catch more obvious errors and work with you to get them resolved. A few assembly companies run designs through internally developed verification software, which use the aforementioned manufacturing files to create digital images of a design and help catch part-to-footprint errors. Then, depending on if it is a turn-key process, they can order parts and/or boards on your behalf. If ordering assembly only, you will need to ship them the boards and the parts, making sure to provide the appropriate overages. Again, proper paperwork and labelling is crucial. If your BOM and board match each other with the appropriate reference designators, but you mislabel the parts when providing them, there will, at best, be delays. At worst, the entire run can require rework, considerably

increasing assembly costs. Check with the assembler for kitting checklists or recommended best practices. Some companies will even send you custom kitting labels free of charge to help with accurate kit preparation.

Pick-and-Place Machines

The physical process at the assembly starts with setting up the pick-and-place machines. This involves loading the XYRS files and all of the different parts into the machines. Reels and trays are manually loaded and some pick-and-place machines can even accept cut tape. Certain assembly houses will hand populate a board and then scan that into the pick-and-place machines to “teach” them the correct locations of the different parts. While this is effective, it takes even longer and can sometimes lead to large setup costs. For small runs, some assembly houses will use hand placement for every board. This is very time consuming and creates inconsistency for both solder-paste application and component placement. There are a few companies that specialize in machine-assembling low-quantity

“Communication should be a constant throughout the life of the product with continual feedback and discussion between the two parties.”

XYRS Information


2828

orders. Using a proprietary software system, they have automated the set-up process, making it cost-effective and fast to set-up the pick-and-place machines—even for a single board.

For smaller runs, certain pick-and-place machines are able to deposit solder paste where necessary for surface-mount technology (SMT) parts, but it is much more common for a solder stencil to be used. Depending on the method, either the Gerber file for the paste layer is uploaded into the pick and place or the stencil and solder paste are physically loaded. In the case of SMTs that will be wave soldered, a glue file or stencil will need to be provided so that the SMTs can be held in place during the wave soldering process.

Once the pick-and-place machine is setup, PCBs are either manually placed in the machine or the boards are brought in via a conveyor system. The boards are then clamped into position, and the pick-and-place machine uses an optical inspection machine to detect variations in the placement of the board in regards to X, Y, and theta. At this stage, use of fiducials is most important since the machine can reference the fiducials as absolute points on the board and then accommodate for small, yet potentially catastrophic, misalignments. The pick-and-place machine automatically places the stencil on the board, deposits a dab of solder paste, and wipes the board, smoothing the solder paste across the stencil and covering the appropriate places on the PCB. The board is either moved or the stencil removed, and the board begins to be populated.

Pick-and-place machines can only place parts on one side of the board, after which they will need to be taken out, soldered, and potentially run through the pick-and-place to take care of the back side. Surface-mount parts are kept in place by the surface tension of the solder paste if they are to be reflowed, otherwise they are simply glued in place in preparation for the wave-soldering process. As the pieces are placed onto the board, there is sometimes a literal push as the pick-and-place puts the parts on the board. This push, or pressure downward on the board, is typically benign, but with thin boards, or panels with only a bare minimum of connecting tabs between the boards, you may see the board flex. As the pick-and-place moves away, the

board snaps back to its original form, sometimes flicking pieces off the board. If your design calls for thin boards or minimal break tabs, it is recommended to speak with your assembly house to make certain that this will not cause a problem.

Solder

With the board solder pasted or glued and populated, the board is ready to actually be soldered. If there are only a few boards, the assembly house is likely to simply hand solder the board. While this is a slow method, it requires no setup time and limits the amount of thermal stress on the components as the application of heat is highly localized. If the boards are comprised of primarily surface-mount devices, fine pitch or bottom terminated devices, or more than a handful of boards are going to be made, reflow soldering is the likely choice. Reflow is much easier to design for than wave soldering but is less than ideal for through-hole components as well as being more expensive. Wave

soldering is an older, very mature technology and has excellent success with through-hole components. Wave soldering surface-mount components adds complexity, but it is generally better to design a mixed-technology board to be either wave-soldered or reflow-soldered than to require both. Depending upon the process, boards may be delivered to another station to insert pressfit parts, or complete any TH soldering.

Testing

Once the boards have cooled enough to handle, the final step before shipment is testing. There are an impressively wide array of tests that can be performed on assembled PCBs. The most simple is the visual inspection. When the boards are complete, a trained inspector looks over the boards to find obvious problems such as missing parts, tombstoned passives, or components that were not actually soldered. This can be followed by an automated optical inspection (AOI) in which a computer inspects the board. Older inspection software compared new boards with a known good board, or a golden board, but newer inspection systems compare the produced boards with the electronic files from which they were produced. These two inspections are standard with almost every assembly house but further tests can be performed if requested. The automated X-ray inspection is a tool very frequently used with BGA and other leadless devices, to make sure that proper solder connections were made between the integrated circuits (IC) and the board. Electrical testing can also be used at this point, either via a joint-test-action-group

“It is helpful to include fiducials either on the entire panel of PCBs, or— if being done board by board—fiducials on the individual boards.”

Board Flexing Under Pressure

PCB and Solder Stencil

Hand Soldering

2929

EE WEB FEATURE

orders. Using a proprietary software system, they have automated the set-up process, making it cost-effective and fast to set-up the pick-and-place machines—even for a single board.

For smaller runs, certain pick-and-place machines are able to deposit solder paste where necessary for surface-mount technology (SMT) parts, but it is much more common for a solder stencil to be used. Depending on the method, either the Gerber file for the paste layer is uploaded into the pick and place or the stencil and solder paste are physically loaded. In the case of SMTs that will be wave soldered, a glue file or stencil will need to be provided so that the SMTs can be held in place during the wave soldering process.

Once the pick-and-place machine is setup, PCBs are either manually placed in the machine or the boards are brought in via a conveyor system. The boards are then clamped into position, and the pick-and-place machine uses an optical inspection machine to detect variations in the placement of the board in regards to X, Y, and theta. At this stage, use of fiducials is most important since the machine can reference the fiducials as absolute points on the board and then accommodate for small, yet potentially catastrophic, misalignments. The pick-and-place machine automatically places the stencil on the board, deposits a dab of solder paste, and wipes the board, smoothing the solder paste across the stencil and covering the appropriate places on the PCB. The board is either moved or the stencil removed, and the board begins to be populated.

Pick-and-place machines can only place parts on one side of the board, after which they will need to be taken out, soldered, and potentially run through the pick-and-place to take care of the back side. Surface-mount parts are kept in place by the surface tension of the solder paste if they are to be reflowed, otherwise they are simply glued in place in preparation for the wave-soldering process. As the pieces are placed onto the board, there is sometimes a literal push as the pick-and-place puts the parts on the board. This push, or pressure downward on the board, is typically benign, but with thin boards, or panels with only a bare minimum of connecting tabs between the boards, you may see the board flex. As the pick-and-place moves away, the

board snaps back to its original form, sometimes flicking pieces off the board. If your design calls for thin boards or minimal break tabs, it is recommended to speak with your assembly house to make certain that this will not cause a problem.

Solder

With the board solder pasted or glued and populated, the board is ready to actually be soldered. If there are only a few boards, the assembly house is likely to simply hand solder the board. While this is a slow method, it requires no setup time and limits the amount of thermal stress on the components as the application of heat is highly localized. If the boards are comprised of primarily surface-mount devices, fine pitch or bottom terminated devices, or more than a handful of boards are going to be made, reflow soldering is the likely choice. Reflow is much easier to design for than wave soldering but is less than ideal for through-hole components as well as being more expensive. Wave

soldering is an older, very mature technology and has excellent success with through-hole components. Wave soldering surface-mount components adds complexity, but it is generally better to design a mixed-technology board to be either wave-soldered or reflow-soldered than to require both. Depending upon the process, boards may be delivered to another station to insert pressfit parts, or complete any TH soldering.

Testing

Once the boards have cooled enough to handle, the final step before shipment is testing. There are an impressively wide array of tests that can be performed on assembled PCBs. The most simple is the visual inspection. When the boards are complete, a trained inspector looks over the boards to find obvious problems such as missing parts, tombstoned passives, or components that were not actually soldered. This can be followed by an automated optical inspection (AOI) in which a computer inspects the board. Older inspection software compared new boards with a known good board, or a golden board, but newer inspection systems compare the produced boards with the electronic files from which they were produced. These two inspections are standard with almost every assembly house but further tests can be performed if requested. The automated X-ray inspection is a tool very frequently used with BGA and other leadless devices, to make sure that proper solder connections were made between the integrated circuits (IC) and the board. Electrical testing can also be used at this point, either via a joint-test-action-group

“It is helpful to include fiducials either on the entire panel of PCBs, or— if being done board by board—fiducials on the individual boards.”

Board Flexing Under Pressure

PCB and Solder Stencil

Hand Soldering


3030

(JTAG) connection or a bed-of-nails tester. Finally, the board can be given a functional test, verifying that it starts up and performs in the way expected. The level of testing is your decision and dependent on the complexity of the board and requirements for reliability.

Defective Boards

After the testing is complete, a decision must be made. What should be done with the defective boards? If you’re producing low-cost, consumer-level products, it may not be worth the time and associated cost to repair the board. Large, expensive boards usually indicate a greater investment and are more likely to be worth taking the time to troubleshoot and salvage. Before production, the general policy on defective boards should be made; however, there will need to be decisions made on the production floor by the technicians.

“The level of testing is your decision and dependent on the complexity of the board and requirements for reliability.”



A simple tombstoned resistor would only take a few moments to fix, while a board that fails the functional test yet passes the other tests could take considerable time to troubleshoot. This is one of the many reasons that communication with the assembly house must be continual throughout the process.

Shipping

Once the boards have been confirmed as good, the assembly house will ship them off. If it were a small prototyping run, they may package the boards in antistatic bags and send them directly to you with the excess materials. For large runs, some assembly houses have the option of packaging the products for you and sending them either directly to distributors or even end consumers. These details can be worked out with your assembly house, but if the pricing is competitive enough, this can allow you

to focus on improving your product and creating the next generation instead of worrying about stocking, storing, and shipping.

Dedicated circuit board assembly houses have the expertise, experience, and equipment to quickly produce high-quality populated boards. By knowing what they do, how they do it, and how you interface with them, you can increase quality and throughput while decreasing cost. To have a better idea of what type of assembly would work best for your product, start searching for assembly houses and asking questions. Work with them to make sure that your design for assembly is on par with your design for manufacturing. With this knowledge and careful planning, your production cycle should move smoothly, manufacturing quality products quickly and inexpensively.

Bed of Nails Tester

www.aapcb.com

3131

EE WEB FEATURE

(JTAG) connection or a bed-of-nails tester. Finally, the board can be given a functional test, verifying that it starts up and performs in the way expected. The level of testing is your decision and dependent on the complexity of the board and requirements for reliability.

Defective Boards

After the testing is complete, a decision must be made. What should be done with the defective boards? If you’re producing low-cost, consumer-level products, it may not be worth the time and associated cost to repair the board. Large, expensive boards usually indicate a greater investment and are more likely to be worth taking the time to troubleshoot and salvage. Before production, the general policy on defective boards should be made; however, there will need to be decisions made on the production floor by the technicians.

“The level of testing is your decision and dependent on the complexity of the board and requirements for reliability.”



A simple tombstoned resistor would only take a few moments to fix, while a board that fails the functional test yet passes the other tests could take considerable time to troubleshoot. This is one of the many reasons that communication with the assembly house must be continual throughout the process.

Shipping

Once the boards have been confirmed as good, the assembly house will ship them off. If it were a small prototyping run, they may package the boards in antistatic bags and send them directly to you with the excess materials. For large runs, some assembly houses have the option of packaging the products for you and sending them either directly to distributors or even end consumers. These details can be worked out with your assembly house, but if the pricing is competitive enough, this can allow you

to focus on improving your product and creating the next generation instead of worrying about stocking, storing, and shipping.

Dedicated circuit board assembly houses have the expertise, experience, and equipment to quickly produce high-quality populated boards. By knowing what they do, how they do it, and how you interface with them, you can increase quality and throughput while decreasing cost. To have a better idea of what type of assembly would work best for your product, start searching for assembly houses and asking questions. Work with them to make sure that your design for assembly is on par with your design for manufacturing. With this knowledge and careful planning, your production cycle should move smoothly, manufacturing quality products quickly and inexpensively.

Bed of Nails Tester

http://www.aapcb.com

MYLINK

http://www.orderpcbs.com

MYLINK

http://www.pcbweb.com

34


TESTInterview with Chris Armstrong Director of Product Marketing for Rigol

With the electronics landscape constantly evolving to serve

the increasingly complex consumer market, it would

be easy to say that innovation occurs at every level of

product development. This is mostly true—thanks to Moore’s Law—

but historically, test and measure technology has remained relatively

unchanged, both in the price point and the technical capability. For

Rigol, a global test and measure equipment provider, this is simply

not enough. Through an overhaul of their product portfolio and an

expansion of their customer support teams, Rigol is taking aim to

transform the test industry once and for all. EEWeb spoke with Chris

Armstrong, Director of Product Marketing for Rigol, about expanding

the company’s offering and some key areas of differentiation from its

global competition.

Transforming

Industry

the

INDUSTRY INTERVIEW

35

TESTInterview with Chris Armstrong Director of Product Marketing for Rigol

With the electronics landscape constantly evolving to serve

the increasingly complex consumer market, it would

be easy to say that innovation occurs at every level of

product development. This is mostly true—thanks to Moore’s Law—

but historically, test and measure technology has remained relatively

unchanged, both in the price point and the technical capability. For

Rigol, a global test and measure equipment provider, this is simply

not enough. Through an overhaul of their product portfolio and an

expansion of their customer support teams, Rigol is taking aim to

transform the test industry once and for all. EEWeb spoke with Chris

Armstrong, Director of Product Marketing for Rigol, about expanding

the company’s offering and some key areas of differentiation from its

global competition.

Transforming

Industry

the

36


When you are in talks with a customer, how do you position Rigol against the likes of your main competitors?The markets our customers serve are all changing rapidly. Moore’s Law has driven significant price reductions in every electronics market. Computers, communications, and consumer electronics have all seen rapid price decreases while performance has increased. Only the test and measurement industry has been immune to this reality and today, four-channel scopes are still around two thousand dollars and DMMs are still around one thousand dollars—just like it was fifteen years ago. This price stability has created significant strains on customers who are continuously expected to do more with less.

Rigol is transforming the test and measurement industry by delivering the same high-quality modern instrumentation as our more well known competitors, but at significantly lower price points. This provides our customers with unprecedented value for their T&M investment. We accomplish this by utilizing standard off-the-shelf components, FPGA-based designs, and common architectures across our portfolio and then we pass this value

engineering off to our customers rather than maintaining the savings as profit. Our FPGA-based design philosophy also allows us to quickly design and deploy new products and features, expand our portfolio, and solve new customer challenges.

How has Rigol outgrown its roots as a hardware vendor? What does this shift in focus mean for Rigol?When you start up a company in this industry, you aim to build quality instruments that serve the needs of the broad market. Rigol has built a strong position in the value general-purpose test category by delivering great products like the DS1102E Oscilloscope. That scope has met the needs of tens of thousands of engineers and students and helped establish Rigol as a serious brand.

As more engineers embrace the value that Rigol brings to their bench, their advanced applications require more support both in the measurement capabilities of their equipment as well as the support they need on how to make measurements and maximize the return on their investment. We have executed against both of those needs. We have built many new SW and analysis features into our products

to help solve specific needs—from EMI testing, to embedded mixed-signal debug, to power analysis and serial bus decode.

We have expanded our portfolio to meet the specific application needs of our customers, but it goes beyond products. We have developed a world-class team of applications engineers, sales engineers, and technical support people in our US office to help customers successfully use these new and ever more powerful application packages. By getting closer to our customers and giving them great applications support we also add to the Rigol value proposition. Instead of just building hardware that you think people need, it’s about digging deeper and learning what troubles an engineer, what costs them time and money, and how you can help them engineer better and more efficiently.

What kind of opportunities have you noticed in the embedded side of test and measurement?The biggest challenge is the fragmentation of smaller engineering firms that are building more and more connected devices. This means there are more engineers doing embedded design work that is not necessarily their primary discipline. Rigol provides cost-effective, intuitive tools that help engineers doing embedded design

“Rigol is transforming the test and measurement industry by delivering the same high-quality modern instrumentation as our more well known

competitors, but at significantly lower price points.”

DS1104Z Oscilloscope – The latest generation, improving on the award-winning DS1102E

work complete their tasks. By combining analog and digital capabilities with powerful triggering and analysis capabilities, our bench instruments let even non-experts complete their board-level debug.

However, there are challenges in this area around serial debugging. Whatever the engineer is connecting their embedded designs to, they are inevitably utilizing serial data transmissions on a number of buses—some of these busses might be custom and some of them standard—but regardless the engineer needs to be able to decode bus traffic and test these interfaces. They will also need to be able to evaluate the conditions on many traces with a system view of the bus and analog signals in order to debug their embedded design.

“By getting closer to our

customers and giving them great

applications support we also

add to the Rigol value

proposition.”

INDUSTRY INTERVIEW

37

When you are in talks with a customer, how do you position Rigol against the likes of your main competitors?The markets our customers serve are all changing rapidly. Moore’s Law has driven significant price reductions in every electronics market. Computers, communications, and consumer electronics have all seen rapid price decreases while performance has increased. Only the test and measurement industry has been immune to this reality and today, four-channel scopes are still around two thousand dollars and DMMs are still around one thousand dollars—just like it was fifteen years ago. This price stability has created significant strains on customers who are continuously expected to do more with less.

Rigol is transforming the test and measurement industry by delivering the same high-quality modern instrumentation as our more well known competitors, but at significantly lower price points. This provides our customers with unprecedented value for their T&M investment. We accomplish this by utilizing standard off-the-shelf components, FPGA-based designs, and common architectures across our portfolio and then we pass this value

engineering off to our customers rather than maintaining the savings as profit. Our FPGA-based design philosophy also allows us to quickly design and deploy new products and features, expand our portfolio, and solve new customer challenges.

How has Rigol outgrown its roots as a hardware vendor? What does this shift in focus mean for Rigol?When you start up a company in this industry, you aim to build quality instruments that serve the needs of the broad market. Rigol has built a strong position in the value general-purpose test category by delivering great products like the DS1102E Oscilloscope. That scope has met the needs of tens of thousands of engineers and students and helped establish Rigol as a serious brand.

As more engineers embrace the value that Rigol brings to their bench, their advanced applications require more support both in the measurement capabilities of their equipment as well as the support they need on how to make measurements and maximize the return on their investment. We have executed against both of those needs. We have built many new SW and analysis features into our products

to help solve specific needs—from EMI testing, to embedded mixed-signal debug, to power analysis and serial bus decode.

We have expanded our portfolio to meet the specific application needs of our customers, but it goes beyond products. We have developed a world-class team of applications engineers, sales engineers, and technical support people in our US office to help customers successfully use these new and ever more powerful application packages. By getting closer to our customers and giving them great applications support we also add to the Rigol value proposition. Instead of just building hardware that you think people need, it’s about digging deeper and learning what troubles an engineer, what costs them time and money, and how you can help them engineer better and more efficiently.

What kind of opportunities have you noticed in the embedded side of test and measurement?The biggest challenge is the fragmentation of smaller engineering firms that are building more and more connected devices. This means there are more engineers doing embedded design work that is not necessarily their primary discipline. Rigol provides cost-effective, intuitive tools that help engineers doing embedded design

“Rigol is transforming the test and measurement industry by delivering the same high-quality modern instrumentation as our more well known

competitors, but at significantly lower price points.”

DS1104Z Oscilloscope – The latest generation, improving on the award-winning DS1102E

work complete their tasks. By combining analog and digital capabilities with powerful triggering and analysis capabilities, our bench instruments let even non-experts complete their board-level debug.

However, there are challenges in this area around serial debugging. Whatever the engineer is connecting their embedded designs to, they are inevitably utilizing serial data transmissions on a number of buses—some of these busses might be custom and some of them standard—but regardless the engineer needs to be able to decode bus traffic and test these interfaces. They will also need to be able to evaluate the conditions on many traces with a system view of the bus and analog signals in order to debug their embedded design.

“By getting closer to our

customers and giving them great

applications support we also

add to the Rigol value

proposition.”

38


What is Rigol doing in the reliability and lifecycle area?Our M300 product line is a data acquisition system. With an M300 system you can do all of the necessary voltage, temperature, resistance, and current measurements. It’s a full, standalone system for benchtop and lab-based acquisitions, so people use it for lifecycle testing and temperature profiling in a manufacturing or industrial setting. It’s a broad-based data acquisition set that we have developed to focus on usability and has a large format, front-panel UI for making those measurements and monitoring them in real time as well as a powerful PC software package for simple setup, monitoring, and analysis.

This enables Rigol to be a more complete provider for engineers. With our scopes and embedded design know-how Rigol’s value on the debug and design bench continues to grow. With our spectrum analyzers and RF solutions, Rigol has a unique offering around RF debug and EMI PreCompliance evaluation. With HALT/HASS testing and data acquisition products like the M300, we help engineers design for quality and manufacture to their specifications completing their most difficult projects on time and under budget with less capital equipment investment than ever before.

How has Rigol worked to develop towards being a trusted brand in the US market?We got our foot in the door on price. It is no secret that early on that, price was what convinced customers to try us out, but we have grown so rapidly because of other things. The quality of our products is uncompromised—it is reliable and people learn to depend on it. Our portfolio is expanding to new applications areas so we are growing along with the needs of our customers. We have put in place a great support team and we differentiate from the big guys with the personal attention we provide. We provide timely application content and use training to help make measurements. Last but not least, our customers continue to get products at a fair price delivering great value. That is how we have grown our brand and will continue to do so. A simple recipe really.

How does Rigol differentiate itself from similar competitors with roots in China?In some senses, it’s the same differentiation we seek in the US market. We have been in the US for almost six years, and we have built up a set of customers and users that trust us and love our equipment. I think we have continued to dive into the applications that engineers care about most and we have built up knowledge

and capabilities and have implemented it back into our products. Basically, by providing great products and great support at fair prices we leave our valued customers no reason to look anywhere else. That is the essence of loyalty.

Now that Rigol has established itself here in the US, what do you hope to see in the next five years?Over the next five years our key goal is growth. We want to delight more customers and introduce more engineers and technicians to our amazing portfolio and unique value. We want to continue to build relationships with our customers and find more application spaces where we think we can offer solutions that help them out and quickly design and deploy products that fulfill those needs. We intend to transform the T&M industry and be the world’s preeminent T&M brand. We will achieve that through four simple pillars:

• Delivering constant innovation

• Providing unprecedented customer value

• Ensuring a world class customer experience at every turn

• Expanding our portfolio to meet our customers changing needs

Rigol M300

“With HALT/HASS testing and data acquisition

products like the M300, we help engineers design for quality and manufacture

to their specifications completing their most

difficult projects on time and under budget.”

INDUSTRY INTERVIEW

39

What is Rigol doing in the reliability and lifecycle area?Our M300 product line is a data acquisition system. With an M300 system you can do all of the necessary voltage, temperature, resistance, and current measurements. It’s a full, standalone system for benchtop and lab-based acquisitions, so people use it for lifecycle testing and temperature profiling in a manufacturing or industrial setting. It’s a broad-based data acquisition set that we have developed to focus on usability and has a large format, front-panel UI for making those measurements and monitoring them in real time as well as a powerful PC software package for simple setup, monitoring, and analysis.

This enables Rigol to be a more complete provider for engineers. With our scopes and embedded design know-how Rigol’s value on the debug and design bench continues to grow. With our spectrum analyzers and RF solutions, Rigol has a unique offering around RF debug and EMI PreCompliance evaluation. With HALT/HASS testing and data acquisition products like the M300, we help engineers design for quality and manufacture to their specifications completing their most difficult projects on time and under budget with less capital equipment investment than ever before.

How has Rigol worked to develop towards being a trusted brand in the US market?We got our foot in the door on price. It is no secret that early on that, price was what convinced customers to try us out, but we have grown so rapidly because of other things. The quality of our products is uncompromised—it is reliable and people learn to depend on it. Our portfolio is expanding to new applications areas so we are growing along with the needs of our customers. We have put in place a great support team and we differentiate from the big guys with the personal attention we provide. We provide timely application content and use training to help make measurements. Last but not least, our customers continue to get products at a fair price delivering great value. That is how we have grown our brand and will continue to do so. A simple recipe really.

How does Rigol differentiate itself from similar competitors with roots in China?In some senses, it’s the same differentiation we seek in the US market. We have been in the US for almost six years, and we have built up a set of customers and users that trust us and love our equipment. I think we have continued to dive into the applications that engineers care about most and we have built up knowledge

and capabilities and have implemented it back into our products. Basically, by providing great products and great support at fair prices we leave our valued customers no reason to look anywhere else. That is the essence of loyalty.

Now that Rigol has established itself here in the US, what do you hope to see in the next five years?Over the next five years our key goal is growth. We want to delight more customers and introduce more engineers and technicians to our amazing portfolio and unique value. We want to continue to build relationships with our customers and find more application spaces where we think we can offer solutions that help them out and quickly design and deploy products that fulfill those needs. We intend to transform the T&M industry and be the world’s preeminent T&M brand. We will achieve that through four simple pillars:

• Delivering constant innovation

• Providing unprecedented customer value

• Ensuring a world class customer experience at every turn

• Expanding our portfolio to meet our customers changing needs

Rigol M300

“With HALT/HASS testing and data acquisition

products like the M300, we help engineers design for quality and manufacture

to their specifications completing their most

difficult projects on time and under budget.”

4040




41

PRODUCT WATCH

41



4242


Specs

Watch VideoTo watch a demo of the SG Series, click the image below:

HardwareSorensen offers 90 different voltage and current configurations, including a 3U model that will do up to 10V and 1200A. Both the SGA and SGI series have analog and digital remote control interfaces, including GPIB, RS232, and Ethernet, which uses the LXI standard. One of the big benefits of the SGI series is the sequencing capability that frees up your system controller and shortens test time. It not only allows you to program in standard voltage, current, or power modes, but also voltage or current ramps as well as using subroutines, looping, and pauses for highly flexible automation.

With up to 30kW from a single supply and the ability to configure multiple supplies in parallel or series, the Sorensen SG series addresses the needs of applications requiring high-power programmable DC supplies. For more info, visit ProgrammablePower.com.

Constant Voltage, Current, and Power Modes

DC Output up to 30kW per Supply

Control Interfaces

Vacuum Fluorescent

Graphical Display

3

1 2

4

Front View

Back View

CLICKXXX HEREXXXX

43

PRODUCT WATCH

43

Specs

Watch VideoTo watch a demo of the SG Series, click the image below:

HardwareSorensen offers 90 different voltage and current configurations, including a 3U model that will do up to 10V and 1200A. Both the SGA and SGI series have analog and digital remote control interfaces, including GPIB, RS232, and Ethernet, which uses the LXI standard. One of the big benefits of the SGI series is the sequencing capability that frees up your system controller and shortens test time. It not only allows you to program in standard voltage, current, or power modes, but also voltage or current ramps as well as using subroutines, looping, and pauses for highly flexible automation.

With up to 30kW from a single supply and the ability to configure multiple supplies in parallel or series, the Sorensen SG series addresses the needs of applications requiring high-power programmable DC supplies. For more info, visit ProgrammablePower.com.

Constant Voltage, Current, and Power Modes

DC Output up to 30kW per Supply

Control Interfaces

Vacuum Fluorescent

Graphical Display

3

1 2

4

Front View

Back View

http://www.eeweb.com/blog/eeweb/high-power-programmable-dc-supplies-ametek-sorensen-sg-series

http://www.eeweb.com/blog/eeweb/high-power-programmable-dc-supplies-ametek-sorensen-sg-series

Sierra Circuits:A Complete PCB Resource

PLUS: The Ground ” Myth in PrintedCircuits

“

PCB Resin Reactor+

Ken BahlCEO of Sierra Circuits

Let There Be

How Cree reinvented the light bulb

LIGHT

David ElienVP of Marketing & Business

Development, Cree, Inc.

New LED Filament Tower

Cutting Edge Flatscreen Technologies

+

+

M o v i n g T o w a r d s

a Clean Energy

FUTURE— Hugo van Nispen, COO of DNV KEMA

MCU Wars 32-bit MCU Comparison

Cutting Edge

SPICEModeling

Freescale and TI Embedded

Modules

ARMCortex

Programming

From Concept to

Reality Wolfgang Heinz-Fischer

Head of Marketing & PR, TQ-Group

Low-Power Design Techniques

TQ-Group’s Comprehensive Design Process

+

+

PowerDeveloper

Octobe r 20 13

Designing forDurability

View more EEWeb magazines— Click Here

http://bit.ly/II3Clh

modern test and measure: april 2015

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