modular multilevel converter mmc tutorial
TRANSCRIPT
Modular Multilevel Converter (MMC)
Ghazal Falahi
Modular Multilevel Converter (MMC) structure
2
SM 2
SM n
SM (n+1)
SM (n+2)
SM 1
SM (2n)
DC link
vavb
vc
u0
ipa
Udc/2
Udc/2
iaib
ic
Larm
LaLbLc
ipb ipc
uaub
uc
Rarm
D1
D2
S1
S2
ipa Vc
incinbina
Larm Larm
RarmRarm
Larm
Rarm
Larm Larm
RarmRarm
q Modular multilevel converter
1. Series connection of sub-modules
Make the arm of the converter to build
the output voltage stepwise
2. Sub-modules are Half-bridge (HB) or
Full-bridge (FB) converters
3. Each sub-module has a capacitor
with average voltage of
Udc
N
arm
leg
4. With n sub-modules in arm of the
converter output voltage has n+1 levels
MMC sub-module operation
3
D1
D2
S1
S2
ipaVc
D1
D2
S1
S2
ipaVc
D1
D2
S1
S2
ipaVc
D1
D2
S1
S2
ipaVc
iarm>0
iarm<0
Sub-module inserted
Capacitor in discharge mode
Sub-module bypassed
Sub-module inserted
Capacitor in charge mode
Sub-module bypassed
4
vavbvc
u0
ia-‐up
ia-‐low
Udc/2
Udc/2
iaib
ic
Larm
LaLbLc
ib-‐up ic-‐up
ib-‐low ic-‐low
ua
ub
uc
Rar
m
Larm Larm
Larm Larm Larm
Rar
m
Rarm
Rarm Rarm Rarm
Innervoltage
Innervoltage
Innervoltage
Innervoltage
Innervoltage
Innervoltage
N ≥Udc
Usm
Modular Multilevel Converter operation
q MMC equivalent circuit
q Number of sub-modules in MMC arm
Each arm of the converter is equivalent
To a controlled voltage source with
magnitude of and a series
inductor
Where nactive is number of inserted
sub-modules
nactive ×Udc
N
MMC advantages and disadvantages
1. Low THD
2. Low on devices and good voltage sharing for semiconductors
3. Modular structure with identical modules which has redundancy and allows to substitute failed
modules
4. Scalable and no DC link voltage limitation
5. Simple mechanical construction
6. No need for bulk filters on ac side
7. Lower losses
5
dvdt
q Advantages
q Disadvantages
1. Extra controller required for balancing of capacitor voltages
2. Need for monitoring all capacitor voltages
3. Circulating current consisting double fundamental frequency component and increases device
losses if not suppressed
MMC mathematical equations
6
icirc =ip + in2
varm = vSMi=0
n
∑ + Larmdiarmdt
+ Rarmiarm
uk −u0 = varm
uk − (vk +u0 ) = varm
Vk : Phase voltage K= a, b, c
uk (t) =Udc
2mk (t)
mk (t) =mcos(ω0t +ϕ )
q MMC mathematical model
q MMC grid connection dynamic
Arm voltage
Output voltage
Circulating current
Modulation
Output voltage
MMC operation and analysis
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)cos(22
)(,_ tVmVtV dcdcrefkarm ω−=
)cos(23
)( ϕω −+= tIIti adcarm
Upper arm reference voltage
Arm current
Varm,ref
iarm
D2 conducts S2 conducts D1 conducts S1 conducts
0
q Device operation in MMC sub-module
m = 1 φ = 0
iarm>0
S1 or D2
S1
D2
iarm<0
S2 or D1
D1
S2
Device operation principal in MMC sub-modules
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The arm current flowing out of the sub-module is considered as positive (a) and the current flowing into sub-module is considered as negative
D1
D2
S1
S2
ipaVc
D1
D2
S1
S2
ipaVc
D1
D2
S1
S2
ipaVc
D1
D2
S1
S2
ipaVc
(a) iarm>0
(b) iarm<0
0, >dt
dV refarm
0, <dt
dV refarm
0, >dt
dV refarm
0, <dt
dV refarm
q Logic of operation
1. Direction of arm current determines which devices can operate 2. The rate reference arm voltage change determines if a sub-
module is inserted or bypassed
State S1 S2 Vsm
1 ON OFF Vc
2 OFF ON 0
Semiconductor rating
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I!"#!$(t) =I!"3 ± !!" 2
2 sin!(!")
!!_!"# =!!"!4 + !!"
!
9
Valve current:
Valve rms current:
q Device voltage
Device voltage rating is the average capacitor voltage rating of sub-modules
With a margin depending on maximum allowed ripple
Udc
N
q Device current Device current in MMC is found from the following equations
Modular Multilevel Converter Conventional Control [1]
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1. An individual capacitor voltage controller
2. The averaging controller
3. The system controller
4. Modulation reference generation
PI PI
1/2
Vc*
Vcu
Ik-‐low
Ik-‐up
Icir*
Icir
VAu*
Total DC voltage controller
PIVc*
Vcju
(j=1-‐2n)
±
-1 :-Ik-up , Ik-low ≥ 0+1 :-Ik-up , Ik-low ≤ 0
VBju*
Individual DC voltage controller
Vmk(k=a,b,c)
PIi*dref
Vod
iod
PIi*qref
ω0Leq
ω0Leqioq
Voq
3dq/abc
System controller ![1] Hagiwara, Makoto, and Hirofumi Akagi. "Control and experiment of pulsewidth-modulated modular multilevel converters." Power electronics, IEEE Transactions on 24.7 (2009): 1737-1746.
VAu*
VBju* Vi/n E/(2n)
Vju* (j=1-‐n)
dAnegVAu*
VBju* Vi/n E/(2n)
Vju* (j=n+1-‐2n)
dAneg
Modulation reference generation
MMC modulation methods
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[1] Wang, Jun, Rolando Burgos, and Dushan Boroyevich. "A survey on the modular multilevel converters—Modeling, modulation and controls." Energy Conversion Congress and Exposition (ECCE), 2013 IEEE. IEEE, 2013.
Multilevel Modulation
Fundamental switching frequency
High switching frequency
Space vector PWM
Sinusoidal PWM
Level shifted PWM
Phase shifted PWM
Space vector control SHE NLM
High switching frequency modulation
techniques ü Suitable for small & large number of sub-modules
ü Lower harmonics
× High losses
Fundamental switching frequency modulation
techniques ü Suitable for large number of sub-modules
ü Lower losses
Passive components design ( Arm inductor and Sub-module capacitor)
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L ≥ Vdc2αmax
!! =1
(8!!!!!!!)( !!3!!! + !!")
!!" = !!3.!.!.!! . !.!!! 1− (!. !"#$2 )!
!!
Ps: three phase apparent power K: voltage modulation index Cosφ: power factor N: number of sub-modules, ω0 is the fundamental frequency, VC: mean value of sub-module voltages ε: sub-module voltage ripple
[1] Tu, Qingrui, et al. "Parameter design principle of the arm inductor in modular multilevel converter based HVDC." Power System Technology (POWERCON), 2010 International Conference on. IEEE, 2010. [2] Zygmanowski, Marcin, Boguslaw Grzesik, and Radoslaw Nalepa. "Capacitance and inductance selection of the modular multilevel converter." Power Electronics and Applications (EPE), 2013 15th European Conference on. IEEE, 2013.
1. Limit the circulation current
2. Limit the fault current rise rate
q Criteria to select arm inductor [1]:
q Sub-module capacitor selection [2]:
1. Provide the output power for at least one cycle
If DC link is defective
2. Limit sub-module voltage ripple
Three phase line PWM voltages and phase currents in MMC with sub-modules in each arm
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0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.6
-1
-0.5
0
0.5
1
time (secs)
Phas
e cur
rent
s (pu
)
iaibic
0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.6
-2
-1
0
1
2
time (secs)
Line
-Lin
e PW
M v
olta
ges
(pu)
VaLLVbLLVcLL
Simulation results of a grid connected MMC with 3 sub-modules in each arm in Matlab
Arm voltages and sub-module voltages of the simulated MMC
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0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.60.97
0.98
0.99
1
1.01
1.02
1.03
time (secs)
Sub-
mod
ules c
apac
itor v
oltag
es (p
u)
Vsm1Vsm2Vsm3Vsm4Vsm5Vsm6
0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.60
0.5
1
1.5
2
2.5
3
time (secs)Phas
e 1 u
pper
and
lowe
r arm
volta
ges (
pu)
References
[1] Falahi, Ghazal. "Design, Modeling and Control of Modular Multilevel Converter based HVDC Systems." PhD Dissertation NCSU (2014). [2] Falahi, Ghazal, and Alex Q. Huang. "Design consideration of an MMC-HVDC system based on 4500V/4000A emitter turn-off (ETO) thyristor." Energy Conversion Congress and Exposition (ECCE), 2015 IEEE. IEEE, 2015. [3] Falahi, Ghazal, and Alex Huang. "Control of modular multilevel converter based HVDC systems during asymmetrical grid faults." Industrial Electronics Society, IECON 2014-40th Annual Conference of the IEEE. IEEE, 2014. [4] Falahi, Ghazal, Wensong Yu, and Alex Q. Huang. "THD minimization of modular multilevel converter with unequal DC values." Energy Conversion Congress and Exposition (ECCE), 2014 IEEE. IEEE, 2014. [5] Falahi, Ghazal, and Alex Huang. "Low voltage ride through control of modular multilevel converter based HVDC systems." Industrial Electronics Society, IECON 2014-40th Annual Conference of the IEEE. IEEE, 2014.
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