module3 isa

7/31/2019 Module3 ISA

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Module 3

Instruction Set Architecture (ISA):

ISA Level

Elements of Instructions

Instructions Types

Number of AddressesRegisters

Types of Operands


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Instruction Set Architecture (ISA) Level

ISA Level defines the interface between thecompliers (high level language) and the hardware. Itis the language that both them understand


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What is an Instruction Set? The complete collection of instructions that

are understood by a CPU

Known also as Machine Code/MachineInstruction

Binary representation

Usually represented by assembly codes

User becomes aware of registers, memorystructure, data types supported by machineand the functioning of ALU


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Elements of an Instruction-1 Operation code (Opcode)

Specifies the operation to be performed (ADD, SUBetc). Specified as binary code know as OPCODE

Source Operand reference

One or more source operands (input for the operation)

Result (Destination) Operand reference

Operation produce a result (output for the operation)

Next Instruction Reference

Tells processor where to fetch the next instructionafter the execution of current instruction is completed


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Elements of an Instruction-2 Source and result operands could be:

Main memory or virtual memory

addresses is supplied for instructionreferences

CPU registers (processor registers) Oneor more registers that can be referenced

by instructions I/O device instruction specifies the I/O

module and device for the operation


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Instruction Representation In machine code each instruction has a unique bit pattern

Instruction divided into fields and with multiple formatsrefer diagram in the next slide

During execution, instruction is read into IR register in theprocessor

For human consumption (well, programmers anyway) asymbolic representation is used

Opcodes represented as mnemonics indicates the

operations e.g. ADD, SUB, LOAD

Difficult to deal in binary representation of machineinstructions

Operands can also be represented symbolically ADD A B


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Simple Instruction Format


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Instruction Types Data processing Arithmetic and logic

instructions

Data storage (main memory) memoryinstructions

Data movement (I/O) I/O instructions

Control (Program flow control) Testand branch instructions


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Number of Addresses Number of addresses per instructions can describe processor

architecture 3 addresses

Operand 1, Operand 2, Result (Destination)

May be a forth address - next instruction (usually implicit, obtainedfrom PC) Example below: T=temporary location used to store intermediate

results Not common in use Needs very long words to hold everything


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Number of Addresses 2 addresses

One address doubles as operand andresult(destination)

Reduces length of instruction and space requirements Requires some extra work

Temporary storage to hold some results Done to avoid altering the operand value


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Number of Addresses 1 address

Implicit second address

Usually a register (accumulator)

Common on early machines


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Number of Addresses 0 (zero) addresses

All addresses implicit

Uses a stack


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How Many Addresses Number of addresses per instruction is a basic design

decision

More addresses

More complex (powerful?) instructions

More registers

Inter-register operations are quicker

Fewer instructions per program

Fewer addresses

Less complex (powerful?) instructions

More instructions per program

Faster fetch/execution of instructions


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Instruction Set Design Decisions (1)

Operation repertoire

How many ops?

What can they do?

How complex are they?

Data types

Instruction formats

Length of op code field

Number of addresses


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Instruction Set Design Decisions (2) Registers

Number of CPU registers available

Which operations can be performed onwhich registers?

Addressing modes (later)

RISC v CISC


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K.K. Leung Fall 2008Pentium Registers & Addressing

Modes 16

Registers (32-bit)

base pointer Register

esi

edi

esp

ebp

stack pointer Register

eax

ebx

ecx

edx

31 0A register

B register

C registerD register

source index register

destination index register


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Modes 17

...Registers (16-bit)

esi

edi

esp

ebp

si

di

sp

bp

ax

bx

cx

dx

eax

ebx

ecx

edx

31 1615 0The least significant 16-bitsof these registers have anadditional register namethat can be used for

accessing just those 16-bits.


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Modes 18

Registers (8-bit)

ax

bx

cx

dx

eax

ebx

ecx

edx

31 1615 0

bh bl

ch cl

dh dl

ah al15 8 7 0

The 2 least significant bytes of registers eax, ebx, ecx and edx also

have register names, that can be used for accessing 8 bits.


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Modes 19

Instruction Pointer Registereip32-bit

The instruction pointer register eip holds the address of the nextinstruction to be executed. The eip register corresponds to theprogram counter register in other architectures.

eip is not normally manipulated explicitly by programs. However it isupdated by special control-flow CPU instructions (e.g. call, jmp, ret)

that are used to implement if's, while's, method calls etc.


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Modes 20

Flags Register

eflags32-bit

The eflags register holds information about the current state of the CPU. Its

32-bits are mostly of interest to the Operating System; however, some of its

bits are set/cleared after arithmetic instructions are executed, and these bitsare used by conditional branch instructions:


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Types of Operand Numbers numeric data

Integer/floating point/decimal

Limited magnitude of numbers integer/decimal

Limit precision floating point

Characters data for text and strings

ASCII, UNICODE etc.

Logical Data

Bits or flags


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Example: Types of Operand for

Pentium 4


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Module 3Instruction Set Architecture (ISA):

Addressing Modes

Instruction Formats


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Addressing ModesAddressing reference a location in

main memory/virtual memory

Immediate Direct

Indirect

Register

Register Indirect

Displacement (Indexed)


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Addressing

ModesA=contents of an address fieldin instruction

R=contents of an address fieldin instruction that refers to aregister

EA=actual (effective) address ofthe location containing the

referenced operand

(X)=contents of memorylocation X or register X


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Addressing Modes


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Immediate Addressing Operand is part of instruction

Operand = A

e.g. ADD EAX,5

Add 5 to contents of register EAX

5 is operand

No memory reference to fetch data

Fast

Limited range

OperandOpcode

Instruction


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Direct Addressing Address field contains address of operand

EA = A

e.g. ADD EAX, A Add contents of cell A to register EAX

Look in memory at address A for operand

Single memory reference to access data

No additional calculations to work out effectiveaddress

Limited address space


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Direct Addressing DiagramAddress AOpcode

Instruction

Memory

Operand


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Indirect Addressing (1) Memory cell pointed to by address field

contains the address of (pointer to) the

operand EA = (A) or EA = [A]

Look in A, find address (A) and look there

for operand e.g. ADD EAX,(A) or ADD EAX,[A]

Add contents of cell pointed to by contentsof A to register EAX


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Indirect Addressing (2) Large address space

2n where n = word length

May be nested, multilevel, cascaded

e.g. EA = (((A))) or EA = [[[A]]]

Draw the diagram yourself

Multiple memory accesses to findoperand

Hence slower


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Indirect Addressing Diagram

Address AOpcodeInstruction

Memory

Operand

Pointer to operand


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Register Addressing (1) Operand is held in register named in

address filed

EA = R

Limited number of registers

Very small address field needed

Shorter instructions

Faster instruction fetch


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Register Addressing (2) No memory access

Very fast execution

Very limited address space

Multiple registers helps performance

Requires good assembly programming orcompiler writing

c.f. Direct addressing


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Register Addressing DiagramRegister Address ROpcode

Instruction

Registers

Operand


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Register Indirect Addressing C.f. indirect addressing

EA = (R) or EA = [R]

Operand is in memory cell pointed to bycontents of register R

Large address space (2n)

One fewer memory access than indirectaddressing


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Register Indirect Addressing

DiagramRegister Address ROpcode

Instruction

Memory

OperandPointer to Operand

Registers


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Displacement Addressing Combines direct addressing and register indirect

addressing

EA = A + (R) or EA = A + [R]

Address field hold two values A = base value

R = register that holds displacement

or vice versa

3 common displacement addressing technique: Relative addressing

Base register addressing

Indexing


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Displacement Addressing

DiagramRegister ROpcode

Instruction

Memory

OperandPointer to Operand

Registers

Address A

+


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Relative AddressingA version of displacement addressing

R = Program counter, PC

EA = A + (PC) or EA = A + [PC]

i.e. get operand from A cells fromcurrent location pointed to by PC

c.f locality of reference & cache usage


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Base-Register AddressingA holds displacement

R holds pointer to base address

R may be explicit or implicit

e.g. segment registers in 80x86


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Indexed AddressingA = base

R = displacement

EA = A + R

Good for accessing arrays


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Pentium Addressing Modes Virtual or effective address is offset into segment

Starting address plus offset gives linear address

This goes through page translation if paging enabled

12 addressing modes available

Immediate

Register operand

Displacement

Base Base with displacement

Scaled index with displacement

Base with index and displacement

Base scaled index with displacement Relative


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Pentium Addressing Mode

Calculation


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Instruction Formats Layout of bits in an instruction

Includes opcode

Includes (implicit or explicit) operand(s)

Usually more than one instructionformat in an instruction set


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Instruction Formats

Four common instruction formats:

(a) Zero-address instruction. (b) One-address instruction

(c) Two-address instruction. (d) Three-address instruction.


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Instruction Length Affected by and affects:

Memory size

Memory organization Bus structure

CPU complexity

CPU speed

Trade off between powerful instruction repertoire andsaving space

Other issues: Instruction length equal or multiple tomemory transfer length (bus system)?


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Allocation of Bits Number of addressing modes if indicated implicitly

exp: certain op-odes might always call for indexing; ifexplicit one or more bits will be needed

Number of operands typical instruction has 2operands uses mode indicator for operandaddresses

Register versus memory single user register(accumulator), one operand address is implicit andconsume no instruction bits; for multiple registers afew bits are need to specify the registers


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Allocation of Bits Number of register sets have one set of general

purpose registers with 32 or more registers in the set for example sets of 8 registers only 3 bits are

needed to identify the registers, op-code willimplicitly determine which register set is beingreferenced

Address range the range of addresses that can be

referenced related to the number of bits Address granularity an address can reference a

word or byte a the designers choice byteaddressing is convenient for character manipulation


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PDP-8 Instruction Format

Fixed Length Instruction: PDP-8 Instruction Format-1


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Fixed Length Instruction: PDP-8 Instruction Format -2

Simplest instruction design

Has 12 instruction and operates on 12 bit words

3 bit op-code and 3 types of instructions

Op-code 0-5 single address memory reference including pagebit and indirect bit thus 6 basic operations

Op-code 7 defines microinstructions remaining bits are usedto encode additional operations each bit defines a specificoperations (etc clear accumulator bit 4)

Op-code 6 is for I/O operations; 6 bits used to select one of 64devices and 3 bits to specify I/O command

Also supports indirect addressing, displacement addressing andindexing

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