monolithic sensors in high-voltage deep-submicron technology

1FEE 2011, Ivan Peric

Monolithic sensors in high-voltage deep-submicron technology

Ivan Peric

University of Heidelberg, Germany


• Introduction to pixel sensors in high voltage CMOS technology

• Operation principle, advantages and disadvantages

• Summary of the project results

• Pixel types

• 1) Particle sensitive pixels with complex CMOS electronics– Test chip in 180nm technology

• 2) Integrating pixels with simple “4T” electronics– 4PMOST source follower pixels

– 4PMOST pixels with voltage amplification

– >4T CDS pixels

• Test beam and lab measurements


Pixel detector in HV CMOS technology

• Monolithic pixel sensor• 100% fill-factor• In-pixel CMOS signal processing• Good timing properties (theoretically 40 ps signal collection time)

• Radiation hard (tested to 50 MRad (x-rays) and 1015 neq (protons))

• Not expensive (monolithic sensor, no bumping, standard technology used)• 350nm technology: 8 inch wafer run: 90k€ (350nm) • 180nm technology: 120k€ and 1.5k€/wafer (1 wafer ~ 200 cm2)• Allows thinning


Detector structure

• The sensor is based on the “deep” n-well in a p-substrate• Main properties: • 1) Charge collection is based on drift• 2) CMOS signal processing electronics


Detector structure

Deep n-well

Pixel electronics in the deep n-wellP-substrate

NMOS transistorin its p-well

PMOS transistor

The CMOS signal processing electronics are placed inside the deep-n-well. PMOS are placed directly inside n-well, NMOS transistors are situated in their p-wells that are embedded in the n-well as well.


“Smart” diode array - SDA

Deep n-well

Pixel electronics in the deep n-wellP-substrate


PMOS transistor

Smart diode


SDA in high voltage CMOS technology

P-substrate


PMOS transistor

Particle

E-field

Deep n-well

Pixel electronics in the deep n-well


SDA in high voltage CMOS technology

• Although this structure can be implemented in any CMOS technology (see 65nm pixel), the best results are achieved when a standard high voltage CMOS technology with twin well is used.

• A lowly-doped deep n-well can be then used. Such an n-well can be reversely biased with a high voltage.

• In the process we used, we expect a depleted area thickness of 14 μm (20cm substrate resistance -> acceptor density ~ 1015 cm-3)

• We measure a MIP signal of ~ 2000e, ~ 50% probably originates from undepleted bulk.

• The charge generated by ionizing particles in the depleted area is collected by drift. Due to high electric field and small drift path, charge collection is very fast. We estimate ~ 40ps.

• Due to drift based charge collection we have high radiation tolerance


Strong points

• 1) Monolithic sensor

• 2) CMOS in-pixel electronics

• 3) Fast signal collection– Theoretically 40ps

• 4) Thinning possible– Since the charge collection is limited to the chip surface, the sensors can be thinned

• 5) Price and technology availability– Standard technology without any adjustment is used

– Many industry relevant applications of HV CMOS technologies assure their long tern availability

– 350nm technology: 8 inch wafer run: 90k€ (350nm)

– 180nm technology: 120k€ and 1.5k€/wafer (1 wafer ~ 200 cm2)

• 6) High tolerance to non-ionizing radiation damage – High drift speed

– Short drift path

• 7) High tolerance to ionizing radiation– Deep submicron technology

– Radiation tolerant design can be used

– PMOS transistors, that are more tolerant to radiation, can be used (in contrast to MAPS with high-resistance substrate)


Drawbacks

• 1) Capacitive feedback– We can implement the majority of important pixel circuits in CMOS, like the charge sensitive

amplifier, shaper, tune DAC, SRAM but…

– “Digitally active” CMOS logic gates in pixels should be avoided

– Possibility 1: Current mode logic can be used instead CMOS (drawback – current consumption ~ 1 A / digital gate)

– Possibility 2: Separate digital and analog circuits (drawback – a few per cent of inactive area at the chip edge)

• 2) Relatively large size of the collecting electrode– Typical values for the total n-well capacitance are

– 10fF - small 21x21 m2 pixels and simple pixel electronics (already tested)

– 200fF 55x55 m2 CMOS pixels (already tested)

– 700fF 80x400 m2 CMOS pixels (proposed long pixels for SLHC)

• 3) Lower signals than in the case of fully depleted sensors– The signals do not decrease significantly after irradiation to 1015 neq cm2


Results of the Project

• The SDAs have been developed within a small project whose aim was the proof of principle

• CMOS particle sensitive (“intelligent”) pixels in 350nm technology• In pixel hit-detection and binary trigger based readout (similar to ATLAS pixels). Pixel

size is 55x55m2 • Noise of 60e • Direct hit signal - 1800e, leading to a seed pixel SNR of 30 • Signal delay time ~ time resolution of the detector ~ 120ns • Part of the signal originates from the un-depleted bulk and is collected by diffusion –

impact on timing will be investigated on a test chip, probably not an issue • 4-transistor pixels (PM Chip) in 350nm technology• Test beam: • Efficiency 97.5%• MIP cluster signal is 2000e and seed pixel signal 1200e• The noise is about 44e that is twice as large as in lab tests – non-ideal setup• Seed pixel SNR is 27, Cluster Signal/Seed Noise = 47• We measure spatial resolution < 3.8μm


„Intelligent“ particle sensitive pixel in 350nm technology

55m

Preamplifier (NMOS part)


RC-CR shaper

NMOS based comparator

4-bit threshold DAC

4-bit SRAM

CM NMOS logic


„Intelligent“ particle sensitive pixel in 350nm technology

55m



RC-CR shaper

NMOS based comparator

4-bit threshold DAC

4-bit SRAM

CM NMOS logic


4T pixel in 65nm technology

2.5m

Metal-metal coupling capacitor

Here only the standard N-Well has been used, only PMOS electronicsLower signals expected (small depleted volume)We hope to compensate this by lower detector capacitance


Radiation tolerance

• In order to test the radiation tolerance we have performed a few irradiations


Proton irradiation

• Proton irradiation of continuous readout pixels up to 1015 neq/cm2, which corresponds to a dose of ~300MRad in SiO2.

• As expected, we measure an increased noise. For example, at 20C we measure 270e. (We had 12e before irradiation.) However, only a light cooling leads to significant noise improvement, a sign that the noise is caused by leakage current. At 10C we have a noise of 77e and at -10 only 40e.

• We have measured the response to 22Na beta particles. SNR at -10C is 93.


Irradiation with protons (1015 neq/cm2, 300 MRad)

0.00 0.02 0.04 0.06 0.08 0.100.0

0.2

0.4

0.6

0.8

1.0

~ n

um

be

r o

f sig

na

ls

signal amplitude [V]

RMS Noise 0.5mv (12e)

55Fe 70mV (1660e)Room temperature

0.00 0.02 0.04 0.06 0.08 0.100.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

lssignal amplitude [V]

RMS Noise, 2.8mv (77e)

55Fe, 60mV (1660e)Temperature 10C

Irradiated with protons to 1015neq

55Fe spectrum and RMS noiseNot irradiatedRoom temperature RMS Noise 12 e

55Fe spectrum, RMS noiseIrradiated10C RMS Noise 77 e



0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80.0

0.2

0.4

0.6

0.8

1.0

~

nu

mb

er

of

sig

na

ls


RMS Noise (40e)

55Fe x-ray spectrum (Peak: 1660e)

22Na beta spectrum (Maximum: 3750e)

SNR = 93

-10C


Particle sensitive pixels with CMOS electronics and continuous readout


Signal detection

ComparatorCR-RC

CSA

N-well

AC coupling

3.3 V

-50 V

P-substrate


Intelligent particle sensitive pixels – possible application

• Vertex detector for the novel experiment. Goal: search for lepton flavor violating decay -> eee

• Four layers of pixels ~ 80x80m2 size

• Continuous muon beam stopped at target – 109 muon stops/s –> requires time stamping with ~ 100ns resolution

• Energy range of interest: 15-50MeV –> multiple scattering dominates momentum measurement –> ~50 m thin detector


Multi-reticle module

Reticle1

Chip1

Pads

Chip to chip connections

Chip to reticle edge distance = 80 um

Chip2

Chip1

Chip2

Reticle2

2.0 cm

Module

Pixel modules with (almost) no insensitive area can be producedReticle-reticle connections can be made easily by wire bondingInstead of wire-bonding, an extra metal layer can be used as well


Low-mass detector

Carrier

Module (length. 12 cm, width 1cm, the figure is not scaled)

Pads for power and IO signals

chip to chip connections

Chip (reticle 3)

Interaction region

Large sensitive area without material

Chip (reticle 2)

Very low-mass only silicon module

Wire as support


Analog Pixel

CSA

Comparator

N-well

P-substrate

ThresholdDAC

Bias Volt.

To digital channel

SRAM


Digital Channel

S

R

LERAM

AddrROM

Time Stamp Data BusPriority Out

Priority In

Read

Hit

From Analog Pixel


Detector with separated analog and digital pixels

1cm

2cm

~125 pixel rows(80 μm pitch)

250 pixel rows(80 μm pitch)

Digital Channels

Analog Pixels – Sensitive Area

Reticle1

Analog Pixels

Digital Channels

~0.75mm

LVDS OutThe figure shows one reticle

~0.7m


Test Chip in 180nm technology

30m

39m

0.7m

2 metal layers

An

alo

g p

ixels

Dig

ital ch

an

ne

ls

1.8mm

42x36 pixels

Analog pixel layout

Pixel is made smaller than neededThis has positive impact on detector capacitance


Analog Pixel

CSA

Buffer

N-well

P-substrate

Bias Volt.

To digital channel

The analog pixel is slightly different than required for the final designComparator, tune DAC and SRAM are missing (placed in the digital channel)


Digital Channel with tune DAC

Comparator

InTrigger

Reset

In

ThresholdDACLatch

ROEn

HitEn

Base line

Global thr.

Hit bus Data out

The digital channel is slightly different than required for the final designSimilar number of transistors


Digital Channel with e-fuse

Comparator

In„1“

Reset

In

ROEn

HitEn

1.8V

3.6V

x

y

Base line

or global thr.

Idea: Strasbourg “MAPS” group (A. Dorokhov)

E-fuse

E-fuse substitutes threshold tune DAC -> smaller layout

E-fuse requires high voltage to be “burned”

This NMOS takes care that the other transistors do not see the high voltage required for “burning” the fuse


Digital Channels

12m

39m DAC

Latches

Fuse

Fuse-“addressing“ transistors


Time walk - simulation

Power in analog pixel ~ only 8W

6 sigma noise

6000e

1200e

7ns!!!


Integrating pixels


Integrating pixels with source follower readout

Out

Res Res Sel

3.3V

2V

-60V

Source followerSensordiode

Only PMOS transistors -> no need for P-Well



Out

Res Res Sel

-60V

3.3V

2V

Reset phase



Out

Sel

-60V

Signal detection phase



Out

Sel

-60V

Q

Q/Cdet

Cdet




Out

Res Res Sel

3.3V

2V

-60V

Source follower

Leakage current -> noise, pedestal dispersion

Threshold dispersion -> pedestal dispersion

The main problems:KTC noise -> requires CDSLeakage current (leakage of PMOS switches probably dominates)Leakage current causes noise and pedestal dispersionThreshold dispersion


Integrating pixels with voltage amplification

Out

VP

Res

Res Sel

VP



Out

VP

Res

Res Sel

VP

Reset phase



OutSel

VP


Charge sensitive amplifier



OutSel

VP

Q

CfQ/Cf




Out

VP

Res

Res Sel

VP

Leakage current -> noise, pedestal dispersionGets worse with higher reverse biasProbably a kind of back gate effectMore pronounced than in source follower pixels

The main problems:KTC noise -> requires CDSPMOS leakage currentThreshold dispersion is not the issue since its effect is reduced by applied gain


Integrating pixels with CDS

Out

VP

Res

Res Sel

VP

Sel

Sample

Sel

~100fF sampling capacitor to store the reset value for duration of one frame

A few NMOS transistors in pixel required -> P-Well is mandatory


Integrating pixels with CDS - simulation

Pixel1 Pixel2

Pre signal reset val.

Signal - reset

Post. signal noisy reset val. Noiseless reset

Signal – reset did not change although the new reset value is different

Transient noise simulation

The reset val. Is stored for the duration of one frame

SelSample

Reset


PM2 chip (known in Eudet community as „Taki“)2

.7 m

m

ADC channel

Pixel matrix

Pixels with voltage amplification (64x128)

Pixels with SF readout (64x128)

LVDS digital I/Os

Analog pads

2-stage switched capacitor difference amplifier

Single ramp ADC

54FEE 2011, Ivan PericADC

Row

-contro

l („Sw

itcher“)

Digital output

10000001000

Pixel size: 21 X 21 m Matrix size: 2.69 X 2.69 mm (128 X 128) Possible readout time/matrix (400MHz clock): ~ 40 s (320ns/row) (tested so far 1.28 s/row (2.56 CDS)) ADC: 8 – Bit Analog power: 43mW/chip, 0.33mW/ADC (90μA+10 μA)Digital power: 538mW/chip at 400MHz clock, 160mA Digital power can be reduced to 40mW (factor 14!) by reducing digital supply and improving flip-flop designIn 180nm technology digital power would be only 12mW

8 LVDS

Counter

Amplifier

Comparator

Latch

Ramp gen.

PM2 chip structure

Pixel matrix


Integrating pixels with SF readout –experimental results


Laboratory measurement with radioactive sources

The spectrum has been measured with 22Na beta source at room temperatureMost probable cluster signal: 2905eMost probable single pixel signal ~1660 eNoise: 31eSNR single pixel = 54SNR cluster signal to single pixel noise = 94Integration time 160 s

0 100 200 300 400 5000.0

0.2

0.4

0.6

0.8

1.0

~ n

umbe

r of

sig

nals

ADC

22Na cluster (2905e) 55Fe single pixel (1660e) 22Na single pixel (~1660e) Noise (31e)


Test beam at CERN (SPS) with Eudet Mimosa 26 telescope

Pixel signals corrected for pedestal distribution (base-line noise)

ADU

num

ber

of s

igna

ls Gaussian fit: sigma = 0.743 (44 e)

Common mode correction(all frames)

ADU

num

ber

of s

igna

ls Gaussian fit: sigma = 0.152 (9 e)

Base line noise – the pixel signals corrected for pedestal distribution, all pixel in one frame are shown

Common mode noise – common mode correction values for all frames and rows

Noise measurement


Test beam: Signal

Seed pixel 2 MSP 3 MSP

7 MSP

ADU

num

ber

of s

igna

ls

Signal spectra in AD units depending on number of pixels in a cluster


Test beam: Signal (2)

1 2 3 4 5 6 70

250

500

750

1000

1250

1500

1750

2000

2250

2500

2750

3000

3250

Mo

st p

rob

ab

le s

ign

al [

e]

Number of pixels

55Na

60Co MIPs

High energy particle signals depending on number of pixels in cluster

Single pixel signal1200 e

Cluster signal2000 e


Test beam: SNR

Seed pixel SNR

SNR

num

ber

of s

igna

ls

Seed pixel SNR = 27


Test beam: SNR

1 2 3 4 5 6 70.0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

20.0

22.5

25.0

27.5

30.0

SN

R

Number of pixels

SNR

Cluster signal to noise ratio (MPX) vs. number of pixels in cluster

Single pixel SNR = 27


Test beam: “fake” SNR

SNR as cluster signal over seed pixel noise

SNR

num

ber

of s

igna

ls

Fake SNR spectrum of the clusters. Fake SNR is here defined as the total cluster charge divided by the seed pixel noise.

Fake SNR = 47


Test Beam: efficiency

Efficiency vs pixel xy-coordinates(Mean value = 0.9761)

X pixel

Y p

ixel

Fig “Efixy”: 2D distribution of the detector efficiency.


Test Beam: Spatial Resolution

Spatial resolution in y-directionGaussian fit: sigma = 4.431 m

Y -Y [ m]DUT TEL

num

ber

of h

its

Distribution of the differences between the measured and the fitted y hit-coordinate.


Test Beam: Spatial Resolution (2)

4.4311

5.36844

4.95608

3.7842

4.84826

4.38728

A B C0

1

2

3

4

5

Sp

atia

l re

solu

tion

in Y

dir

ect

ion

[ m

]

without correction corrected for telescope error

6.31243

7.099016.61151

5.54876

6.42946

5.88677

A B C0

1

2

3

4

5

6

7

Sp

atia

l re

solu

tion

in X

dir

ect

ion

[m

]

without correction corrected for telescope error

Spatial resolution of the DUT in y direction. The black rectangles show the measured and red rectangles the exact spatial resolutions of the DUT corrected for the telescope error. In the cases A and B we used the eta-corrected CoG, and in the case C only the raw CoG corrections. The corrections were calculated only with 3 most significant pixels of a cluster in the case B.

Figure „ResAllx“: Spatial resolution of the DUT in x direction.


Integrating pixels with voltage amplification –experimental results


Noise measurement and 55Fe spectrum

50 60 70 80 90 100 110 120 130 140 150 160 1700.0

0.2

0.4

0.6

0.8

1.0

~

nu

mb

er o

f sig

na

ls

ADU

55Fe, 1 pixel, 76 ADU, (1660e) Noise 1.1 ADU (24e)

Noise: 24eDKS used

55Fe1660e

Sensor has been cooled with a small Peltier cooler: T ~ (?) 10C


High-energy beta spectra

0 1000 2000 3000 4000 5000 6000 7000 80000.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

ls

signal amplitude [e]

Noise, 1 pixel (21e)

60Co, 1 pixel (1700e)

60Co, 2 pixels (1800e)



0 1000 2000 3000 4000 5000 6000 7000 80000.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

lssignal amplitude [e]

Noise, 1 pixel (21e)

22Na, 1 pixels (1900e)




60Co betas (about 10% higher signals than MIPs)Seed signal: 1700eCluster signal: 2250eNoise: 21eSeed SNR: 81Cluster signal/seed noise: 107

55Na betasSeed signal: 1900eCluster signal: 3300eNoise: 21eSeed SNR: 90Cluster signal/seed noise: 157

Estimated MIP seed pixel SNR: 57Cluster signal/seed noise: 95


Long module

6 cm

1 cm

Half module size 1x6cm Pixel size 40x40μm Pixels 250x1500 RO time 80μs/matrix Resolution 7(!) bit/pixel (count up to 125) – if CDS pixels are used, we need probably only 6 bits Power 960mW/module (150mW/cm2 (80 analog + 70 digital)) Data output width 7x12 = 84 bits @ 400Mbit180nm Technology:Power 210mW/module (35mW/cm2 (14 analog + 21 digital))20μs/matrix possible – power 140mW/cm2


Summary

• We have developed a new pixel sensor structure (smart diode array) for high energy physics that can be implemented in a high voltage CMOS technology.

• The sensor has 100% fill-factor and can have in-pixel electronics implemented with p- and n-channel transistors.

• We have tested the sensor structure in various variants:• 1) Sensor with in-pixel hit detection and sparse readout, • 2) Sensor with fast rolling-shutter readout and simple pixel electronics• We have done three test-beam measurements with good results.

– Detection efficiency 98%– Seed Pixel SNR ~ 27– Cluster Signal/Seed Pixel Noise ~ 47– Spatial resolution ~ 3.8 m

• We have irradiated the chips with neutrons, protons and x-rays to test radiation tolerance.

• After irradiation with protons up to very high fluence 1015 neq/cm2 and dose 300MRad, we have still very large SNR (>40) for high energy beta particles at nearly room temperatures (10C).

• We have submitted a new test-chip in 180nm technology• We are planning an engineering run either in 350nm or in 180nm technology,

probably with two detectors, one for muon experiment (CMOS pixels) and one for electron microscopy (integrating pixels)


• Thank you!


• Backup slides


ResetB

ResetNWB SelB

Out

VN

N-Well

P-Substrate

VP

Out

Pixels with SF RO – signal detection phase

VPVNResNWB SelB


ResetB

ResetNWB SelB

Out

VN

Out

Hit

VPVNResNWB SelB

VP


ResetB

ResetNWB SelB

Out

VN

Out

Charge collection

VPVNResNWB SelB

VP


ResetB

ResetNWB SelB

Out

VN

Out

Readout phase

VPVNResNWB SelB

VP


ResetB

ResetNWB SelB

Out

VN

Out

Readout phase

VPVNResNWB SelB

VP Signal


ResetB

ResetNWB SelB

Out

VN

Out

Reset

VPVNResNWB SelB

VP Signal


ResetB

ResetNWB SelB

Out

VN

Out

Reset + offset readout

VPVNResNWB SelB

VP


ResetB

ResetNWB SelB

Out

VN

Out

End of readout

VPVNResNWB SelB

VP


ResetB

ResetNWB

SelB

VP

Pixel with volt. amplification – signal detection phase

VP

VPResNWB SelBVP

Out

Pixel

Out


ResetB

ResetNWB

SelB

VP

Hit

VPOut

VPResNWB SelBVP

Out

Pixel


ResetB

ResetNWB

SelB

VP

Charge collection

VPOut

VPResNWB SelBVP

Out

Pixel


ResetB

ResetNWB

SelB

VP

Readout phase

VPOut

VPResNWB SelBVP

Out

Pixel


ResetB

ResetNWB

SelB

VP

Readout – voltage amplification

VP

Out

VPResNWB SelBVP

Out

Pixel

Amplified Signal


ResetB

ResetNWB

SelB

VP

Readout – voltage amplification

VP

VPResNWB SelBVP

Pixel

Out

Amplified Signal

Out


ResetB

ResetNWB

SelB

VP

Reset

VP

VPResNWB SelBVP

Pixel

Out

Amplified Signal

Out


ResetB

ResetNWB

SelB

VP

Reset + offset readout

VPOut

VPResNWB SelBVP

Out

Pixel

Out


ResetB

ResetNWB

SelB

VP

End of readout

VPOut

VPResNWB SelBVP

Out

Pixel


Pixel Electronics for SLHC

• The pixel electronics could include a charge sensitive amplifier (CSA), leakage current compensation, continuous feedback, comparator and threshold tune DAC.

• The digital circuits inside pixel should be as simple as possible• The idea:• The addresses of all hit pixels are transmitted out of the sensor within next bunch

crossing• No hit buffering• No trigger data reduction• Assumption: occupancy is low enough so that we do not have not more than one hit

per pixel column in one bunch crossing. This holds for R ~ 30 - 50cm


Capacitance of long pixels

N-well

P-substrate

P-well

400um60um

~200fF

~500fF (C_area = 0.014fF/um2)

Total 700fF



CSA

Comparator

N-well

P-substrate

ThresholdDAC

Bias Volt.

ADDRROM

100MHz

In

In

„1“



ADDRROM

In

In

„1“

ADDRROM

In

In

„1“

Hit in Pixel A

Address „A“ on the data line

Time signal 1

Hit in Pixel B

Address „B“ on the data line

Time signal 2


Sensor Chip Architecture for SLHC

2cm



Reticle

1. Sensor reticule

2. Pixel column

Normal pixels

Readout pixel

Signal path

GBit fast shift register

Digital readout chipperforms digital data processing

GBit Pads

Power 30 μW/pixel375mW / reticle94mW / cm2

Current 288mA / reticle

Hit


4-Reticle Module for SLHC

Power lines on the sensor chip

Reticle-reticle connections

Digital readout chip

Signal lines on the sensor chip

4cm

Capton PCB

Signals

Power

Pixel orientation


Double-Layer Modules

Digital readout chips receive the hits from both detector layers Generation of trigger possible?

Pads


Time Resolution

• Time resolution is limited by time walk (can be improved by ToT correction!)• Time resolution is proportional to preamplifier bias current and power consumption• Time resolution is inversely proportional to detector capacitance


Time walk for 24μW pixel amplifier and 700fF detector capacitance - simulation

22ns time walk

6 sigma noise (24mV)

100.0n 150.0n 200.0n 250.0n 300.0n0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

Out

put

Vol

tage

[V

]

Time

1500e 2625e 3750e 4875e 6000e


Time Resolution with HV1

0 10 20 30 40 50 6048

50

52

54

56

58

60

62

Response timeThreshold: 720 eSignal: 1110 e

Noise

DAC setting

No

ise

/e

100

110

120

130

140

150

160

Re

spon

se tim

e/n

s1 2 3 4 5 6 7 8 9

20

40

60

80

100

120 Separated diodeRegular pixel

Inpu

t no

ise/

eAmplifier bias / A

Response time ~ time resolution


Irradiation with neutrons (1014 neq/cm2) – signal

0 1 2 3 4 5 60

200

400

600

800

1000

1200

1400

1600

1800

2000

2200

2400 60Co Irradiated chip (1014 n

eq)

Not irradiated

Sig

nal [

e]

Number of pixels in cluster

IrradiatedNot irradiated

Increase of the detector leakage current from 350fA to 130pA per pixelSeed pixel signal decrease from 1300e to 1000e. The measurement has been performed at 0C

0 1000 2000 3000 4000 5000 60000

50

100

150

200

250

300

350

Num

ber

of h

itsSignal [e]

1 MSP 2 MSP 3 MSP 4 MSP 5 MSP 6 MSP


Irradiation with neutrons (1014 neq/cm2) – noise

0.00 0.05 0.10 0.150.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

ls


noise amplitude 3 = 3mv (3 = 50e)

55Fe 100mv (1660e)

Irradiated with neutrons to 1014 neq

Room temperature

0.00 0.02 0.04 0.06 0.08 0.100.0

0.2

0.4

0.6

0.8

1.0

~ n

um

be

r o

f sig

na

ls





55Fe spectrum and noise amplitudeIrradiated with neutrons (1014 neq)Room temperature Noise amplitude (~3 sigma) ~ 50 e



0.00 0.02 0.04 0.06 0.08 0.100.0

0.2

0.4

0.6

0.8

1.0

~

nu

mb

er

of s

ign

als




0.00 0.02 0.04 0.06 0.08 0.10 0.120.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

ls


RMS Noise, 13mv (270e)



0.00 0.02 0.04 0.06 0.08 0.100.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

ls





0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.160.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

ls



55Fe, 100mV (1660e)Temperature -10C



55Fe spectrum and RMS noiseIrradiated20C RMS Noise 270 e

55Fe spectrum, RMS noiseIrradiated-10C RMS Noise 40 e

55Fe spectrum, RMS noiseIrradiated10C RMS Noise 77 e



0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80.0

0.2

0.4

0.6

0.8

1.0

~

nu

mb

er

of s

ign

als


22Na - 0V bias (0.075V or 1250e)

22Na - 30V bias (0.18V or 3125e)

22Na - 60V bias (0.22V or 3750e)

55Fe - 60V bias (100mV or 1660e) RMS Noise (2.4mV or 40e)

Temperature: - 10C


55Na spectra, -10C



0.0 0.2 0.4 0.6 0.80.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

ls



55Fe, 100mV (1660e)

55Na, 220mV (3750e)Temperature -10C


0.0 0.2 0.4 0.6 0.80.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

ls



55Fe, 60mV (1660e)

55Na, 180mV (4980e)Temperature 10C


0.0 0.2 0.4 0.6 0.80.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

ls


RMS Noise, 13mv (270e)

55Fe, 80mV (1660e)

55Na, 200mV (4150e)Temperature 20C


55Fe and 22Na spectrum, RMS noiseIrradiatedTemperature 20CRMS Noise 270 eSNR = 15

55Fe and 22Na spectrum, RMS noiseIrradiatedTemperature 10CRMS Noise 77 eSNR = 64

55Fe and 22Na spectrum, RMS noiseIrradiatedTemperature -10CRMS Noise 40 eSNR = 93


Irradiation x-rays (50 MRad)

600 700 800 900 1000 11000.0

0.2

0.4

0.6

0.8

1.0

resp

on

se p

rob

ab

ility


Response probabilityfit: sgma = 72e, mean = 750eNot irradiatedRoom temperature

500 600 700 800 900 10000.0

0.2

0.4

0.6

0.8

1.0

resp

on

se p

rob

ab

lility


Response probabilityfit: sgma = 83e, mean = 610eIrradiated with x-rays to 60MRadTemperature 5CNoise

Before irradiationRoom TemperatureNoise 72e

NoiseAfter irradiationTemperature 5CNoise 83e

0 20 40 60 80 100 1200

50

100

150

200

250

300

350

400

NoiseRoom temperature annealiingday 0: irradiation with x-rays to 60MRadday 5: 24 hours at 80C

no

ise

[e]

annealing time [days]

Noise at room TemperatureVs. annealing time


Irradiation x-rays (50 MRad)

0 25 50 750

20

40

60

80

100

120

140

~n

um

be

r o

f sig

na

ls

signal duration [clock periodes]

55Feirradiated with x-rays to 60MRadTemeperature 5C

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 100000

250

500

750

1000

~N

um

be

r o

f hits

Singnal/e

55Na beta signalIrradiated with x-rays to 60MRadTemperature 5C

0 25 50 75 100 125 150 175 200 225 250

0.0

0.2

0.4

0.6

0.8

1.0

~

sig

na

l pro

ba

bili

ty

signal duraion [clock periodes]

Not irradiated (room T) Irradiated with x-rays to 60MRad (5C)

22Na spectrum

22Na spectrum

22Fe spectrum


Project overview

First chip – CMOS pixelsHit detection in pixels

Binary ROPixel size 55x55μm

Noise: 60eMIP seed pixel signal 1800 e

Time resolution 200ns

CCPD1 ChipBumpless hybrid detector

Based on capacitive chip to chipsignal transfer

Pixel size 78x60μmRO type: capacitive

Noise: 80eMIP signal 1800e

CCPD2 ChipEdgeless CCPD

Pixel size 50x50μmNoise: 30-40e

Time resolution 300nsSNR 45-60

PM1 ChipPixel size 21x21μm

Frame mode readout4 PMOS pixel electronics

128 on chip ADCsNoise: 90e

Test-beam: MIP signal 2200e/1300eEfficiency > 85% (timing problem)

Spatial resolution 7μmUniform detection

PM2 ChipNoise: 21e (lab) - 44e (test beam)

Test beam: Detection efficiency 98%Seed Pixel SNR ~ 27

Cluster Signal/Seed Pixel Noise ~ 47Spatial resolution ~ 3.8 m

Irradiations of test pixels60MRad – SNR 22 at 10C (CCPD1)

1015neq SNR 50 at 10C (CCPD2)

Frame readout - monolithicBumpless hybrid detector

1.5 mm

Readout chip (CAPPIX)

Sensor chip (CAPSENSE)

Power supplyand cont. signalsfor the sensor

Power supplyand cont. signalsfor the readout chip

Testbeam DESY

Testbeam CERN

EUDET telescope

DUT

DUT

0 5 10 15 20 25 30 35 40 45 500

100

200

300

400

500

600

700

800

seed p ix e l3 M S P

w h o le c lu s te r

S N R

coun

t

MIP spectrum (CERN SpS - 120GeV protons)

Testchip

PCB

PCB with PPGA and analog supply voltage regulators/DACs

60V bias voltage (3 batteries)

Trigger ID

USB connector

2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5T

T^ 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Efficiency

Purity

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 20 40 60 80 100 1200

10

20

30

40

50

60

effic iencyeffic iency

pixel coordinate x

pix

el

coo

rdin

ate

yEfficiency

Seed and cluster cut [SNR]

2.7

mm

ADC channel

Pixel matrix

ComparatorCR-RC

CSA

N-well

AC coupling

3.3 V

-50 V

P-substrate

0 100 200 300 400 500 600 700 8000

20

40

60

80

100

120

140

160

180

200

220Sr-90, Regular pixel, 55V

Num

ber

of h

its

ToT/Clk

MIP Signal: 2000e/1.17 = 1710 eLow energy peak:1.080 e

a)b)

0 100 200 300 400 500 600 700 8000,0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

1,0

1,1

Regular pixel, 55V

Fe-55 Sr-90

~hi

t pr

obab

ility

ToT/Clk

Sensor pixels

Readout electrodes

Pads for power and signals

monolithic sensors in high-voltage deep-submicron technology

Documents