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18
Sources: TSR, Katz, Boriello & Vahid 1 More ALU Components

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Sources: TSR, Katz, Boriello & Vahid

1

More ALU Components

Sources: TSR, Katz, Boriello & Vahid

Symbol Implementation

A3

B3

A2

B2

A1

B1

A0

B0

Equal=

A B

Equal

44

Comparator: Equality

Sources: TSR, Katz, Boriello & Vahid

A < B

-

BA

[N-1]

N

N N

5-<3>

Comparator: Less Than

Sources: TSR, Katz, Boriello & Vahid

• Logical shifter: shifts value to left or right and fills empty

spaces with 0’s

– Ex: 11001 >> 2 = 00110

– Ex: 11001 << 2 = 00100

• Arithmetic shifter: same as logical shifter, but on right

shift, fills empty spaces with the old most significant bit

– Ex: 11001 >>> 2 = 11110

– Ex: 11001 <<< 2 = 00100

• Rotator: rotates bits in a circle, such that bits shifted off

one end are shifted into the other end

– Ex: 11001 ROR 2 = 01110

– Ex: 11001 ROL 2 = 00111

Shifters

Sources: TSR, Katz, Boriello & Vahid

A3:0

Y3:0

shamt1:0

>>

2

4 4

A3

A2

A1

A0

Y3

Y2

Y1

Y0

shamt1:0

00

01

10

11

S1:0

S1:0

S1:0

S1:0

00

01

10

11

00

01

10

11

00

01

10

11

2

General Shifter Design

Sources: TSR, Katz, Boriello & Vahid

6

Multiplication of positive binary numbers

• Generalized representation of multiplication by hand

For demo see: http://courses.cs.vt.edu/~cs1104/BuildingBlocks/multiply.010.html

Sources: TSR, Katz, Boriello & Vahid

7

Multiplier – Array Style

• Multiplier design – array of

AND gates

A B

P*

Block symbol

+ (5-bit)

+ (6-bit)

+ (7-bit)

0 0

0 0 0

0

a0a1a2a3

b0

b1

b2

b3

0

p7..p0

pp1

pp2

pp3

pp4

Sources: TSR, Katz, Boriello & Vahid

8

Division of positive binary numbers

• Repeated subtraction

– Set quotient to 0

– Repeat while dividend >=

divisor

• Subtract divisor from dividend

• Add 1 to quotient

– When dividend < divisor:

• Remainder = dividend

• Quotient is correct

Dividend Quotient

101 - 0 +

10 1

11 - 1 +

10 1

1 10

Example:

• Dividend: 101; Divisor: 10

For demo see: http://courses.cs.vt.edu/~cs1104/BuildingBlocks/Binary.Divide.html

Sources: TSR, Katz, Boriello & Vahid

10

ALU: Arithmetic Logic Unit

Sources: TSR, Katz, Boriello & Vahid

Designing an Arithmetic Logic Unit

• ALU Control Lines (ALUop) Function

– 000 And

– 001 Or

– 010 Add

– 110 Subtract

– 111 Set-on-less-thanA

LU

N

N

N

A

B

Result

Overflow

Zero

3ALUop

CarryOut

11

Sources: TSR, Katz, Boriello & Vahid

A One Bit ALU

• This 1-bit ALU performs AND, OR, and ADD

1 1 0 0

1 1 1 0+

1 0 1 0

1

- 4

- 2

- 6

1 0 0

12

Sources: TSR, Katz, Boriello & Vahid

A 32-bit ALU1-bit ALU 32-bit ALU

13

Sources: TSR, Katz, Boriello & Vahid

Subtract – We’d like to implement a means of

doing A-B (subtract) but with only minor

changes to our hardware. How?

1. Provide an option to use bitwise NOT A

2. Provide an option to use bitwise NOT B

4. Provide an option to use 0 instead of the first CarryIn

5. Provide an option to use 1 instead of the first CarryIn

3. Provide an option to use bitwise A XOR B

Selection Choices

A 1 alone

B Both 1 and 2

C Both 3 and 4

D Both 2 and 5

E None of the above14

Sources: TSR, Katz, Boriello & Vahid

Full 32-bit ALU

sign bit (adder output from bit 31)

what signals accomplish ADD?

Binvert CIn Oper

A 1 0 2

B 0 1 2

C 1 1 2

D 0 0 2

E NONE OF THE ABOVE

15

Sources: TSR, Katz, Boriello & Vahid

Full 32-bit ALU

sign bit (adder output from bit 31)

what signals accomplish OR?

Binvert CIn Oper

A 1 0 0

B 0 1 1

C 1 1 0

D 1 0 1

E NONE OF THE ABOVE

16

Sources: TSR, Katz, Boriello & Vahid

Full 32-bit ALU

sign bit (adder output from bit 31)

what signals accomplish SUB?

Binvert CIn Oper

A 1 0 2

B 0 1 2

C 1 1 2

D 0 0 2

E NONE OF THE ABOVE

Little more intense –

can you get this?

17

Sources: TSR, Katz, Boriello & Vahid

ALU

N N

N

3

A B

Y

F

F2:0 Function

000 A & B

001 A | B

010 A + B

011 Not used

100 A & ~B

101 A | ~B

110 A - B

111 Not used

Arithmetic Logic Unit – Example 2

+

2 01

A B

Cout

Y

3

01

F2

F1:0

[N-1] S

NN

N

N

N NNN

N

2

Ze

ro

Exte

nd

Sources: TSR, Katz, Boriello & Vahid

19

ALU Design Example 3

S2 S1 S0 Function

0 0 0 0

0 0 1 B-A

0 1 0 A-B

0 1 1 A+B

1 0 0 A xor B

1 0 1 A or B

1 1 0 A and B

1 1 1 1