mosis fabrication report 2008

8/4/2019 MOSIS Fabrication Report 2008

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Fabrication Report

Institution: School of Electrical and Computer Engineering, Purdue University, West LafayetteFaculty members: Byunghoo Jung, Cheng-Kok Koh, Saeed Mohammadi and Kaushik Roy

Design Number: 77783Fab ID: T75T-BC

Design Type: Digital/RF

Number of Parts Received : 40 ( 20 packaged / 20 bare dies)Number of Parts Tested : 40 (20 packaged / 20 bare dies)

Number of Parts Functional : 40

ContentsI. Process Variation Tolerant SRAM Design...................................................................................... 1II. UWB LNA with Active Balun....................................................................................................... 6III. A Reconfigurable MEMS-less CMOS Tuner.................................................................................. 8IV. Improved R2TWO Clock Generation/Distribution Network.............................................................. 9V. Variation Resilient Adaptive Body Biasing System ....................................................................... 11VI. Acknowledgement ..................................................................................................................... 14


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I.Process Variation Tolerant SRAM Design

Student: Jaydeep Kulkarni

Professor: Kaushik Roy

Overview- In this work, we present process variation tolerant SRAM design for low voltage applications. testchip containing SRAM arrays with conventional 6T cell and the proposed technique is fabricated using 0.13m

technology. Built-in test circuits are also implemented to characterize the memory array. Measurement resul

with 10 test-chips show that proposed bitcell gives 62% higher read Static Noise Margin (SNM) and can operat120mV lower supply voltage (20Kbits characterized) compared to the 6T cell. Faster bitline sensing techniqu

shows ~22% improved performance. The SRAM array is found functional at 150mV.

TEST STRATEGY:

(a) SRAM tester block diagram (b) Read failure test: timing diagramFig. 1. SRAM tester architecture

In order to characterize the memory failure statistics, tester circuit is also designed. Fig. 1(a) shows the bloc

diagram of the built-in tester circuit. It has three inputs (Clock, Reset, Feed) and two outputs (Flag, Tout). Th

Reset and Feed are control signals, and Flag and Tout are output signals from failure measurements. The Clocdetermines the operation speed of SRAM during failure measurements. By properly controlling Reset and Fee

signals during read, write, access, and hold test, it is possible to measure SRAM functional failures. The Testeconsists of 2Kb SRAM array (containing 6T cell and proposed cell), shifter, starter, read/write drivers, counte

latch, multiplexer, flag generator, and an XOR gate.

Read failures occur when the voltage at node storing 0 (VREAD) exceed the inverter trip-voltage (VTRIPFig. 1(b) shows the timing diagram for the on-chip tester operation. In order to measure read failure, data (1 o

0) is written into the cell for initialization. During the initialization phase, Feed=1 so that all the word-lineare turned on simultaneously. This gives enough time to ensure a proper write operation (strong write). In th

next step, Reset is set to 0 and the negative edge of Reset generates a Start pulse. This pulse propagates throug

the row driver circuit to turn on one word-line at a time. In order to remove possible access failures during rea


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operation, two consecutive read operations are performed. The first read operation is performed at the desire

clock speed. The second read operation is performed at a slower clock speed to ensure no access failures occurre

at high frequency. To develop a simple failure measurement scheme, we designed the row driver as a 256-bshifter. Each bit of the shifter is used to drive a word-line. If the shifter bit is 1 the word-line is turned on

whereas a bit 0 corresponds to a turned off wordline. The Read/Write drivers read stored data from cell owrite data to cell depending on test mode. For every clock cycle, the read out data is compared with the writte

data through the XOR logic. The counter with latch counts the number of failures and stores it. The high XOR

output indicates a failure and advances the counter state by one. The high output of Flag signal indicates that thtested column has at least one failure during test. The final state of the counter represents the total number o

faulty cells (expressed as 6-bit digital numbers in this study) in a particular column. The faulty cell numbers arstored in the latch and the multiplexer is used to send out these stored numbers serially to external terminal (Tout

CHIP MEASUREMENT RESULTS:

A test-chip with 2Kb SRAM array containing 6T and proposed bitcell is fabricated using 0.13m CMO

technology. For DC SNM measurements, separate isolated memory bitcells with each transistor having 10 fingeare fabricated. Guard rings and dummy fingers (transistors) are used for isolated cell layout in order to minimiz

the effect of process bias on finger structures. This would generate transistors having V T same as that of

transistor used memory cell in the SRAM array. Internal nodes of the isolated bitells are connected to supply padinstead of I/O buffers with several dummy transistors for gate oxide protection.

Fig. 2 Captured read and hold mode characteristics at 300mV

Measurements are done on 10 different testchips to fully characterize the 6T cell as well as proposed memory cel

Fig. 2 shows captured voltage transfer characteristics during read mode as well as hold mode. It is clearly seen ththe proposed bitcell gives better read/hold mode characteristics. This improvement was found to be consistent wit

various supply voltages. Read SNM measurements on 10 testchips show that at 300mV, the proposed bitcell oaverage gives 58% higher read SNM compared to 6T cell as shown in Fig. 3. Similarly for write mode, measure

results show that proposed bitcell gives ~2X higher write-trip-point compared to 6T cell. Thus proposed ce

shows better read stability as well as better write-ability than the 6T cell. Both cells show similar hold SNM.


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Fig. 3 Read SNM measurement with 10 testchips

Using the SRAM tester described earlier, all test-chips have been fully characterized for read/write failur

statistics. Supply voltage is reduced gradually and the read failures are counted using the built-in counter. Thclock frequency is kept low to avoid the failures caused due to insufficient access time. Fig. 4 shows measure

read failures as a function of supply voltage for 6T cell as well as proposed bitcell. Measured read V mindetermined as the highest supply voltage where the first read failure has occurred (for 20Kbits data). It is observethat proposed cell achieves 120mV lower read Vmin compared to 6T cell (Fig. 4).

Fig. 4 Measured read failure statistics with 10 testchips

Bitline sensing scheme is characterized with the help of external reference voltage. A decoupled voltage sensamplifier is implemented for sensing the data. In a decoupled sense amplifier the bitlines are isolated from th

sense amplifier output. In order to measure the internal bitline voltage due to fast bitline differential, fixed dapattern is written into the cell. Hence only one specific bitline would get discharge faster than the other bitlin

The internal bitline detection sequence is shown in Fig. 5. This bitline voltage and the external voltage are give

as inputs to the sense amplifier. When the external reference voltage is higher than the internal bitline voltagesense amplifier output does not change (Fig. 5). When the reference voltage is lowered below than the intern

bitline voltage, the sense amplifier output will flip.


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Fig. 5 Measurement results: Bitline sensing technique characterization

Fig. 6 shows the performance improvement with the faster bitline sensing technique. For iso-bitline differentia

development (VBL = VDD/2), the bitline differential increases with increase in supply voltage. Thus fast bitlinsensing technique becomes more effective with the supply voltage. At 300mV, operating frequency is 270 KH

with leakage power consumption of 0.11W. Supply voltage is reduced gradually to check the correct reafunctionality. It is found that at 500Hz the proposed SRAM is functional at 150mV with clock-to-data_out dela

of 110us.

Fig. 6 Performance improvement and leakage power measurement vs. supply voltage


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Fig. 7 Testchip measurement setup

Fig. 8 test-chip summary

Fig. 7 and Fig. 8 show the measurement setup and the testchip summary. Total silicon area is 1.063mm2

wit

104K transistors. Performance metrics are listed in the table as shown.

SUMMARY

Reducing the supply voltage is an effective way to achieve low power consumption essential for battery operatemobile devices. However, the sensitivity of circuit parameters to process variations increases with the reductio

in supply voltage. On-chip cache memories form a significant portion of a system-on-chip. Hence designinprocess variation tolerant SRAM for ultra-low voltage applications is absolutely essential. In this work, we desig

a process variation tolerant SRAM suitable for low voltage applications. A test-chip containing SRAM arrays wit

conventional 6T cell and proposed techniques is fabricated using 0.13m technology. Built-in test circuits are alsimplemented to fully characterize memory array. Measurement results with 10 test-chips clearly demonstrate th

effectiveness of the proposed techniques for successful low voltage SRAM operation.


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II.UWB LNA with Active Balun

Student: Sang Hoon JooProfessor: Byunghoo Jung

INTRODUCTION

In the RF front-end of a receiver, a low noise amplifier (LNA) and a balanced-unbalanced converter (balun) arethe most critical blocks to fight noise and improve the noise characteristic of the entire receiver. An LNA should

provide appropriate input impedance matching, sufficient gain, low noise figure, and good linearity with relative

small area and low power consumption. A balun should afford very small gain difference and 180 degree of phasdifference at the output with having small area and low noise contribution.

TEST PLAN

Figure 9 shows the test setup to measure all performance parameters in the UWB LNA. S parameters and noisefigure were tested by connecting 50 load at the one of the output since we have to use 2 ports Network Analyze

Spectrum Analyzer, and Noise Figure Analyzer. To measure phase difference of the LNA, we used high speedoscilloscope having two inputs.

Figure 9. Test Setup

SUMMARY

The 2-stage low noise amplifier was designed. This LNA architecture does not deploy any inductor to reducedesign area with sacrificing a small portion of noise figure and power consumption. To drive the differential inpu

of mixer, an active balun also included. The Table I shows the final results.


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Table I - LNA Performance Summary

Simulated Measured

S21 28.44 - 23.93 dB 27.7 - 22.8 dB

S31 28.44 - 23.90 dB 27.70 22.7 dB

Gain difference 0 0.03 dB 0.1 - 0.2 dB

Phase difference 180 179.6 degree 180.5 181.5 degree

S11 -11.4 dB -8 dB

Noise Figure 2.56 3 dB 2.7 3.4 dB

Frequency 3GHz 5GHz

Supply voltage 1.2 V

Power dissipation: Core without

buffer

11.4 mW

Power dissipation: Total 18.6 mW

Technology 0.13 um CMOS


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III.A Reconfigurable MEMS-less CMOS Tuner

Student: Laleh Rabieirad

Professor: Saeed Mohammadi

INTRODUCTION

In this project a fully integrated CMOS programmable tuner that operates from 4 to 11GHz is demonstrated. Timplement the programmable tuner N=44 varactor pairs with distance of s=32m from each other are used acros

a 1.5mm long low loss transmission line. Every two varactor pairs that are facing each other are biased using thsame bias line. Symmetrical design of the structure enhances the coplanar wave propagation mode. The figu

bellow shows the layout of the tuner.

Fig.10 Fully Integrated CMOS Programmable Tuner Fig.11 Smith Chart Representation of Measurement Dat

SUMMARY

There is a tradeoff between the quality factor of the varactor and its capacitance ratio C max/Cmin. High

capacitance ratio results in more smith chart coverage but lower quality factor. We have optimized the number ofingers (nf=26) and finger area (WL= 1m240nm) of each varactors to achieve a reasonably high quality facto

of 100 at 10GHz during simulation and an acceptable maximum to minimum capacitance ratio of 1.5.We have performed 2-port S-parameter measurement of the fabricated tuner using Agilent 8722 Networ

Analyzer and on-wafer probing. Calibration is done using a SOLT standard substrate and de-embedding performed using the open-thru test structures on the chip.Measurement shows that the quality factor of varactors are much less than expected from simulation, at 10GH

the quality factor of varactors is about 10. It is impractical to measure 222

different configurations of the tuner. a

analytical model is created in Matlab based on the measurement results considering the reduction in quality factoof the varactors. This model is used to show the smith chart coverage. The figure bellow shows the actual smit

chart coverage at 5.8GHz . The radius of smith chart coverage would have been doubled if the quality factor of th

varactors was about the same as predicted by cadence model.


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IV.Improved R2TWO Clock Generation/Distribution Network

Student: Ruilin WangProfessor: Cheng-Kok Koh

INTRODUCTION

The R2TWO theory is discussed in detail in our CICC2006 paper, and thus will not be provided here. In this

tapeout, we added varactors at the output of the drivers, reduced the length of the transmission line, and replaced

the NAND gates with inverters. Besides, we add a well-designed skew test circuitry. The purpose of this tapeout

to verify the following:1. With varactor, the frequency is tunable. The effective tuning range.2. With more advanced technology which provides faster devices and copper interconnect, and inverte

replacing NAND gates, the phase noise can be lower.

MEASUREMENT RESULT

1. Phase noise: The phase noise figures corresponding to delta-mode lowest-frequency (upper-left), Y-modlowest-frequency (upper-right), delta-mode highest-frequency (lower-left) and Y-mode highest-frequenc

(lower right) are shown in the following. The figures are quite flat due to the 3 closely coupled OSC. Th

phase noise at 1MHz frequency offsets are always around the range of -117~-119dB. These results are bettthan the result shown in the CICC2006 paper. The corresponding RMS jitters are also much lower.

Fig. 13 Measurement Data

2. Frequency tuning range: The frequency tuning range is from 6.15GHz to 6.89GHz. It achieves the lowefrequency of 6.5GHz when the substrate of the varactor is connected to ground, and the highest frequency o


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6.9GHz when the substrate is connected to VDD.

3. Power consumption: With supply voltage = 1.3V, the supply current is around 12mA (11mA to 13mA for thentire frequency range), which is less than 30% of the power consumption of the traditional ring oscillator.

4. Skew: The tested skews between the clock sink/internal driver outputs is less than 1.5ps for all frequencrange. We believe most of these skew values are contributed by the test circuitry according to simulations.

[CICC2006] Ruilin Wang; Cheng-Kok Koh; Byunghoo Jung; Chappell, W.J., Clock Generation and

Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration, CICC 2006, 781-784.


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V.Variation Resilient Adaptive Body Biasing System

Student: Sang Phill Park, Kunhyuk Kang

Professor: Kaushik Roy

INTRODUCTION

In this project, we have implemented variation resilient circuit design technique for maintaining parametric yie

of design under inherent variation in process parameters. We propose to utilize on-chip phase locked loop (PLLas a sensor to detect process, VDD, and temperature (PVT) variations or even temporal degradation stemmin

from negative bias temperature instability (NBTI). We will show that control voltage (Vcnt) of voltage controlle

oscillator (VCO) in PLL can dynamically capture performance variations in circuit. By utilizing the Vcntsignal oPLL, we propose variation resilient circuit design using adaptive body bias (VR-ABB). Vcntis used to generate a

optimal body bias for various circuit blocks in order to avoid possible timing failures. Correspondingly, circuican be designed with a significantly relaxed timing constraint compared to the conventional approaches, where

large amount of design resources can be wasted to take care of the worst case situations. We have demonstrate

our approach using an 8 bit Ripple Carry Adder (RCA) as an example circuit.

DESIGN

Fig.14 Variation Resilient Adaptive Body Biasing System

Fig. 15 Body Bias Generator


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RESULTS

Fig. 16 Locking Vcnt measurement on 120nm transistor and 140nm transistorwith changing VDD

Fig. 17 Locking Vcnt measurement on 120nm transistor and 140nm transistorwith temperature variation


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PLL

UNLOCKED

PLL

LOCKED

Fig. 18 Oscilloscpe captured the body bias generator output whenthe locking Vcnt is between 800 mV and 865 mV where C1 isNMOS body voltage and C2 is PMOS body voltage

PLL

UNLOCKED

PLL

LOCKED

Fig. 19 Oscilloscpe captured the body bias generator output whenthe locking Vcnt is between 945 mV and 981 mV where C1 isNMOS body voltage and C2 is PMOS body voltage


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SUMMARY

Fig 16 and Fig 17 shows the Vcnt measurement with VDD and temperature variation. The locking Vcont trenshows as we expected for the evidence of the PVT variation. The body bias generator uses Vcont as input an

produces body bias for both PMOS and NMOS. (Fig 18, Fig 19) These output captures show the body bigenerator operates only when the PLL is locked.

VI. Acknowledgement

We would like to thank MOSIS for testchip fabrication.


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mosis fabrication report 2008

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