high yield integrated circuit design using the mosis service
DESCRIPTION
High Yield Integrated Circuit Design using the MOSIS Service. Michael S. McCorquodale Robert M. Senger Eric D. Marsman. Solid State Electronics Laboratory NSF ERC for Wireless Integrated Microsystems (WIMS) Department of Electrical Engineering and Computer Science University of Michigan - PowerPoint PPT PresentationTRANSCRIPT
Michael S. McCorquodaleRobert M. SengerEric D. Marsman
High Yield Integrated Circuit Design using the MOSIS Service
Solid State Electronics LaboratoryNSF ERC for Wireless Integrated Microsystems (WIMS) Department of Electrical Engineering and Computer ScienceUniversity of MichiganAnn Arbor, MI USA 48109-2122
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nOutline• Analog/RF Design Considerations
• Digital Design Considerations
• System Integration
• Pitfalls
• Conclusions
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nOutline• Analog/RF Design Considerations
• Digital Design Considerations
• System Integration
• Pitfalls
• Conclusions
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nAnalog/RF Design Methodology• Top-Down Design
– Begin with a specification– Use AHDL (Verilog-A) to model– Design and iterate
• Bottom-Up Verification– Verify custom cells– Verify blocks composed of custom cells– Verify chip
• Relevant References on Methodology– M. S. McCorquodale, F. H. Gebara, K. L. Kraver, E. D. Marsman, R. M. Senger,
and R. B. Brown, "A Top-Down Microsystems Design Methodology and Associated Challenges," Designer's Forum, Design Automation and Test (DATE) 2003, Munich, Germany, 2002.
– M. S. McCorquodale, E. D. Marsman, R. M. Senger, F. H. Gebara, and R. B. Brown, "Microsystem and SoC Design with UMIPS,“ IFIP VLSI-SoC International Conference 2003, Darmstadt, Germany, 2003.
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nAnalog/RF Design Methodology• Full Custom Design Tools
– Cadence Process Design Kit (PDK) is the officially supported kit for full custom design with MOSIS
– Kits available from website– Installation instructions and documentation included
• Comments on PDKs– Good idea to appoint a manager of a particular PDK
– TSMC18 RF/MM at Michigan managed by M. S. McCorquodale– PDK shared amongst UNIX group members only– Not editable by anyone other than manager– Updates to PDK handled by manager– Multiple copies of PDK are STRONGLY discouraged
– Do NOT forget disclosure agreement with MOSIS– Protect all sensitive information if sharing with UNIX group– Ask system administrator when in doubt about security
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nPractical Side of Analog/RF Design• Design Verification
– Electromigration– LVS/DRC– Tool options
• Backannotation– LPE– Simulating LPE viewpoint
• Chip-Level Verification and Issues– Input/Output– Metal fill– Antenna rules
• Tapeout– Map tables and technology codes– Streaming and log files– Data integrity and transfer– Transfer confirmation
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nDesign Verification• Electromigration
– Related to current density and significant failure mechanism– M1 max density typically 1mA/m, greater for higher level metals
– Must check all interconnect for current density: See design rules for densities
• LVS/DRC (Layout vs. Schematic & Design Rule Check)– Verification decks often contain errors
– RF devices (i.e. MiM, inductor) are often not supported or not supported well – Review the deck when in doubt: Editing is often required
– DRC violations are unacceptable– Purpose of some rules can be unobvious, thus do not ignore violations unless you are certain
that you understand them
• Tool Options– Mentor Calibre vs. Cadence Diva
– Calibre: Official deck, fast, but outside icfb framework (use RVE)– Diva: Unofficial deck, simple, LPE, within icfb framework, but very slow
– Design Size– Large: Use Calibre and RVE for icfb due to CPU time– Small: Diva OK for quick and easy verification, but verify again with Calibre
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nBackannotation with Cadence PDK• LPE (Layout Parasitic Extraction)
– Use Diva deck for extraction– Set switches to include “PARASITIC_RC”
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Design by M. S. McCorquodale, University of Michigan
Analog/RF Chip DesignExtracted Viewpoint
Sample Backannotated Viewpoint
RC parasitics
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nSimulating the Backannotated Viewpoint
Chip-level simulation viewpoint(top-level schematic)
Chip design to besimulated with parasitics
Simulationstimulus
50 load andparasitic capacitancemodel for instrumentation
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nCadence Hierarchy Editor
Parasitic device models
Design device models
Stimulus model
Top-levelschematic
Extractedviewpoint
Allspectreviewpoints
Extractedviewpoint
Thisviewpoint
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nSimulating the Backannotated Viewpoint
Chip-level simulation viewpoint(top-level schematic)
Design by M. S. McCorquodale, University of Michigan
Extracted viewpointsimulated
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nChip-Level Verification and Issues• Input/Output
– Poor I/O = Dead chip– Design for test equipment (for RF this means 50)– Ensure that the I/O can drive the load at the design frequency– Include ESD for I/O that connects directly to gates
• Metal Fill– Each layer defined by CMP & must cover percentage of total chip
– TSMC18 MM/RF: Poly 15%, M1- M6 30%, CTM 3%– Perform fill yourself and verify with PDK rule file
– Do NOT let MOSIS do this for analog/RF designs. Why? Consider inductors.– Use a DRC-clean fill cell that is tied to a known potential
– Do NOT submit under filled designs
• Antenna Rules– Long interconnect lines charge during plasma etching and can discharge into
gates if no alternate discharge path exists– Fix with shorter traces, diodes, “cut and link,” and/or “jumping up”
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n“Cut and Link” and “Jumping Up”
Cut and Link
Jumping Up
A B
A B
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nTapeout• Map Tables and Technology Codes
– Know and understand supported layers for given technology– TSMC18 MM/RF (CM018) supports MiM, thick LM, deep NWELL, etc. – TSMC18 Logic (CL018) does NOT support these layers– Understand that some layers are for verification purposes only (i.e. IND, CAP)
– Always refer to official map file posted on MOSIS website– Good idea to generate new map file containing only supported layers– PDKs contain complete map tables with all layers
• Streaming and Log Files– Check for invalid layers prior to streaming
– It is easy to draw on “nt” layer instead of “dg” layer accidentally– Turn off all valid layers and select all to check for invalid polygons
– Always inspect log file after streaming for warnings– Verify that all warnings are do not pertain to fabricated layers– Many warnings will be due to verification layers and can be ignored
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nTapeout• Data Integrity and Transfer
– Compile MOSIS checksum utility and run– Security on some machines may complicate transfer to MOSIS– The sooner the design is transferred, the better– Do NOT submit “placeholder” designs
• Transfer Confirmation– Verify pad count after submission
– Be aware that openings inside die are not counted
– Verify that metal fill requirements are met– Review all warnings – Review submission status
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nSample Final Analog/RF Design
Design by M. S. McCorquodale, University of Michigan
MonolithicClock Synthesizer
with MicromachinedRF Reference
Metal fill
Bond pads
Active devices
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nThe Importance of Design Reuse
• Founded in 2003 by graduate students and faculty
• Founded to promote design reuse within the research community
• Accepting contributions from all research institutions
• Includes analog, RF, digital, MEMS, synthesis, and design IP
• Publications available
• Design methodologies to be posted soon
www.eecs.umich.edu/umips
University of Michigan Intellectual Property Source (UMIPS)
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nOutline• Analog/RF Design Considerations
• Digital Design Considerations
• System Integration
• Pitfalls
• Conclusions
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nPhysical Design Methodology
CellLibrary
Verilog
Synthesis
Netlist
Floorplan
Routing
CellLayout
Extraction
Timing
RC
Placement
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nDesign Verification and Testing
Testprogram
Random Test Generator
PowerPCcompiler
RTL modelPowerPCinstructionsimulator
Checkerreg mem
Error
Debug
NoYes
TDS
Conversionscript
HP82000
VCD output
Test Vectors
Standard Vectors
• Verify throughout project
• Run hundreds of millions of test vectors
Focused Tests
Random Tests
Application Code
• Design review with peers
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nBlock Synthesis & Simulation• Synthesis with Synopsys Design Compiler
– See UMIPS for sample scripts, constraints, etc.– Partition large designs & perform hierarchical synthesis– No clock tree generation, done in APR (Auto-Place & Route)– Don’t worry too much about timing paths that are close.
RC extraction will change it a lot
• Simulate synthesized design– Back-annotate with SDF (Standard Delay File)– Simulate back-annotated gate level netlist with ideal clock net
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nBlock APR & Simulation• APR with Cadence Silicon Ensemble
– See UMIPS for sample scripts– Partition large designs into sub-blocks. Doesn’t have to be same
hierarchy as synthesis– Floorplan, power rings, place cells, clock buffers/trees, power
routing, signal routing, antenna fixes
• Simulate APR’ed design– Write out gate level netlist from APR tool– Back-annotate with SDF from APR tool– Simulate back-annotated APR netlist with clock tree delays
• Static timing with Synopsys Primetime– Back-annotate (D)SPF ((Detailed) Standard Parasitics File)
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nOutline• Analog/RF Design Considerations
• Digital Design Considerations
• System Integration
• Pitfalls
• Conclusions
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• Synthesis with Synopsys Design Compiler– See UMIPS for sample scripts, constraints, etc.– set_dont_touch on all lower level blocks– Full custom blocks require Verilog stubs with port lists only– No clock tree generation, done in APR– Don’t worry too much about timing paths that are close. RC
extraction will change it a lot
• Simulate synthesized design– Back-annotate SDF– Simulate back-annotated gate level netlist with ideal clock net
Top Level Synthesis & Simulation
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nTop Level APR & Simulation• APR with Cadence Silicon Ensemble
– See UMIPS for sample scripts– Include all sub-blocks, memories, pads– Create LEF (Library Exchange Format) for full custom blocks to
define block size, port locations, and routing blockages– Floorplan, insert pad frame, power rings, place cells, clock
buffers/trees, power routing, signal routing, antenna fixes– Floorplanning at top level is difficult
– Manual floorplanning is necessary for tight designs– Iterative, can require re-APR of lower level blocks– Bad floorplans waste silicon and can be unroutable
• Simulate APR’ed design– Write out gate level netlist from APR tool– Back-annotate with SDF from APR tool– Simulate back-annotated APR netlist with clock tree delays
• Static timing with Synopsys Primetime– Back-annotate (D)SPF
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nLVS• Mentor Graphics Calibre LVS
– See UMIPS for scripts– Generate source netlist from APR gate-level verilog using
Mentor Graphics ‘v2lvs’ tool– Multiple power domains are tricky because ground nets
shorted through substrate– Rename non-global power nets in source netlist
– Temporarily short all ground nodes in layout
– Run LVS, should be clean
– Remove ground shorts in layout and re-run LVS to verify that you have new nets for each ground node
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nDRC• Mentor Graphics Calibre DRC, antenna checks,
metal density fill– See UMIPS for scripts– TSMC 0.18m - be aware of standard versus thick top metal
option in mixed-mode process– Follow metal slot rules– Can use MOSIS for metal fill, or do it yourself
• Mentor Graphics Calibre Results Viewing Environment (RVE)
– View Calibre LVS & DRC results in Cadence Virtuoso– Zoom to violation
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nOutline• Analog/RF Design Considerations
• Digital Design Considerations
• System Integration
• Pitfalls
• Conclusions
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nPitfalls• Empty layout views (Ghost views)
– MOSIS requires earlier submission for instantiation– Not recommended - difficult to verify DRC/LVS
• Multiple power domains– Can break core power nets in pad ring– Need core power pad for each segment of pad ring– Break only VDD net for VDD pad and similarly for VSS
• Must verify APR results, especially at top level– Gaps in pad ring– Min width power routes to block with 20m power ring– Lots of (few hundred) open and/or shorts on signal routes– Some inefficient routes - check parasitics for large values or inspect critical
signals– Some antennas remain - manually insert diodes or layer-hop to higher metal layers
• Think about packaging early
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nOutline• Analog/RF Design Considerations
• Digital Design Considerations
• System Integration
• Pitfalls
• Conclusions
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nConclusions• Start early
– Allow time for top-level floorplanning and design iteration– Large designs require 2-3 weeks for APR fixes due to tool issues. Even
longer the first time through the design flow.
• Verify, verify, verify!– Don’t blindly trust the tools, they make mistakes– ALWAYS run DRC & LVS, no exceptions!– An extra week verifying, even if you miss a tapeout deadline, will save
time in the long run– Conduct design reviews
• Don’t rush tapeouts or you’ll make a mistake!
– If you feel rushed, wait for the next tapeout
• Submit proposal, bonding diagrams, and designs to MOSIS early
• Pay careful attention to MOSIS reports & project status
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nConclusions• Good Luck!
WIMS Microcontroller Designed in TSMC 0.18m MM/RF CMOS with Thick Top Metal
16KB SRAM
16KB SRAM
16KB SRAM
16KB SRAM
I/O
CLK
PIPELINE
CACHE
DIFFPOT
ADC
3.6m
m
Design by R. M. Senger, E. D. Marsman, M. S. McCorquodale, F. H. Gebara, K. L. Kraver, S. M. Martin and R. B. Brown, University of Michigan
Artisan SRAM
Synthesized Digital I/O
and Pipeline
Full Custom CMOS-MEMS Clock Reference
Full Custom -ADC
Full Custom Differential
Potentiometer