mosis tsmc 0.35um hi-esd pad - auburn universitynelson/courses/elec5250_6250... · non-disclosure...

Consulting & Engineering Serviceswww.tanner.com/ces

CE-LI-CC-IOmosis35

2650 East Foothill Blvd.Pasadena, CA 91107 USATel: (626) 792-3000Fax: (626) [email protected]

The MOSIS Service

Hi-ESD Pad Library

TSMC CMOS (0.35µµ) ProcessJune 1999

Tanner Consulting & Engineering Servicesdevelops and delivers advanced ASIC and VLSI solutions for customers.

We accomplish this through training programs, consulting services,field engineering and contracted design/development efforts.

Copyright © 1999 by Tanner Research, Inc. All rights reserved

Consulting & Engineering Serviceswww.tanner.com/ces

CE-LI-PR-CE

TANNER CES GENERAL TERMS & CONDITIONSLiability

All designs will be implemented under the Client’s front-end specification. Our contracted engineering services are accomplished for theClient on a best effort basis. Quality assurance is achieved by arriving at a common understanding of the nature of the Project among the

engineers and managers at the Client operation and at Tanner CES. Tanner Research is not liable for the functionality, quality, orperformance of the Client’s future Projects using components produced as part of the contracted work. Tanner Research is not liable if

the Client chooses to use our recommended design or application methodologies. If prototype chips are delivered, the process vendors donot generally guarantee yield, quality, or performance of their products. Neither does Tanner Research extend any warrantee to the

contracted design and its fabricated results.

Non-Disclosure Agreement

Non-disclosure agreements (NDAs) serve the following purposes.

oo Signed between the Client and Tanner Research, the NDA protects Client’s original concept, status, and intentions in currentand future product development and manufacturing.

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Ownership of Work Results

The Client owns the delivered version and the fabricated version of the work results from a contracted Client Project. Theseresults are subject to the following re-distribution conditions:

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ooþþ

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

LOGIC

NMOS

PMOS

ESD

ESD

A

A B

B C

C D

D E

E F

F

1 1

22

3 3

44

5 5

G

G

Size: 5x7

Rev A

Path:O:\ces_prjct\mosis\Pad025-035U\work_dir\layout_TSMC035\mlou\databook\HiESD_Pad2

Module:Pad_Frame Page:Page0

Designer:Victor Dinh

Info:MOSIS TSMC/HP 0.35um Hi-ESD IO Pad Set

Modified:Jun 15, 1999 13:36:11Created:Nov 9, 1998 15:15:18

Tel: (626)792-3000

2650 East Foothill Blvd, Pasadena, CA 91107Fax: (626)792-0300

0.9 mm

(4500 lambda)

0.9 mm(4500 lambda)

(450 lambda)pitch = 0.09 mm

1.5 mm(7500 lambda)

1.5 mm

(7500 lambda)

MOSIS TSMC/HP 0.35umHi-ESD Minimum Pad Frame

(1) lambda = 0.20um

Size: 5x7Created:Nov 9, 1998 15:15:18Modified:Jun 15, 1999 13:36:11



Page:Page0Module:Pad_Frame


Rev A

Fax: (626)792-03002650 East Foothill Blvd, Pasadena, CA 91107

Tel: (626)792-3000

Tel: (626)792-3000

2650 East Foothill Blvd, Pasadena, CA 91107Fax: (626)792-0300

Rev A


Module:Pad_Dimension Page:Page0



Modified:Jun 15, 1999 13:34:21Created:Nov 9, 1998 13:20:00

A

A B

B C

C D

D E

E F

F

1 1

22

3 3

44

5 5

G

G

Size: 5x7

231 micron

46 micron

90 micron

(450 lambda)300 micron

78 micron

(390 lambda)

78 micron

60 micron

(300 lambda)

(1) lambda = 0.20um

Hi-ESD Pad DimensionsMOSIS TSMC/HP 0.35um

(230 lambda)

(1155 lambda)

(1500 lambda)

(390 lambda)

BONDINGPAD

ESD TRANSISTORPMOS

PADLOGIC

ESD TRANSISTORNMOS

60 micron

LOGICPAD

NMOSESD TRANSISTOR

ESD TRANSISTORPMOS

pitch = 90 micron

(300 lambda)

PADBONDING

(300 lambda)

Fax: (626)792-03002650 East Foothill Blvd, Pasadena, CA 91107

Tel: (626)792-3000

Created:Nov 9, 1998 13:20:00Modified:Jun 15, 1999 13:34:21



Page:Page0Module:Pad_Dimension


Rev A

Size: 5x7

mTSMs035P – MOSIS TSMC 0.35µµmHi-ESD Pad Cell Library

Rev. APADLIB

Page1 of 4

Copyright 1999 by Tanner Research, Inc. All rights reserved.

Pad Library PADLIB

Description: Pad Library

Library: MOSIS TSMC 035P Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples

Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdbModule: Library

Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdbCell: Lib_Pads

Mapping Macros: GateSim: TannerLb\nettran\scmos\scms2sim.mac L-Edit/SPR: TannerLb\nettran\scmos\scms2tpr.mac

Logic Symbol Truth Table Capacitance

N/A N/A N/A

Height Width Area Equivalent Gate DriveN/A N/A N/A N/A N/A

Logic Equation

N/A

Delay Characteristics: N/A


Rev. APADLIB

Page2 of 4


Pad Library PADLIB

This page is intentionally left blank.


Rev. APADLIB

Page3 of 4


Pad Library Schematic PADLIB

Hi-ESD IO PAD SET

Inpu

t Pa

d wi

th B

uffe

r

Outp

ut P

ad w

ith

Buff

er

Vdd

Pad

with

ESD

Gnd

Pad

with

ESD

Anal

og R

efer

ence

Pad

wit

h ES

DAn

alog

IO

Pad

with

ESD

MOSIS TSMC 0.35um - Submicron Rules

PadOut_SCMOS

PadInC_SCMOS

PadVdd

PadGnd

PadIO

PadARef

DIB

DIDI_UNBUF

IPadC

PAD

DO

OPad

PAD


Rev. APADLIB

Page4 of 4


Pad Library Layout PADLIB


Rev. APADFRAME

Page1 of 4


Pad Frame PADFRAME

Description: Pad Frame


Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdbModule: N/A

Mask layout: L-Edit File: TannerLb\scmos\mTSMs035.tdbCell: FRAME



N/A N/A N/A

Height Width Area Equivalent Gate Drive1.5 mm 1.5 mm 2.25 mm2 N/A N/A

Logic Equation

N/A



Rev. APADFRAME

Page2 of 4


Pad Frame PADFRAME



Rev. APADFRAME

Page3 of 4


Pad Frame Schematic PADFRAME

N/A


Rev. APADFRAME

Page4 of 4


Pad Frame Layout PADFRAME


Rev. APADAREF

Page1 of 4


Analog Ref Pad PADAREF

Description: Analog Reference Pad


Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdbModule: PADAREF

Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdbCell: PADAREF



N/A N/A

Height Width Area Equivalent Gate Drive300 µ 90 µ 27000 µ2 N/A N/A

Logic Equation

N/A


PadARef


Rev. APADAREF

Page2 of 4


Analog Ref Pad PADAREF



Rev. APADAREF

Page3 of 4


Analog Ref Pad Schematic PADAREF

SIGNALSIGNAL

PadARef

L='3*l'M=16

TESDP W='175*l'

BONDING

PAD

L='3*l'M=16

TESDN W='175*l'


Rev. APADAREF

Page4 of 4


Analog Ref Pad Layout PADAREF


Rev. APADBIDIR

Page1 of 4


Bi-Directional Pad PADBIDIR

Description: Bi-Directional Pad with Buffer


Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdbModule: PADBIDIR

Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdbCell: PADBIDIR



N/A


Logic Equation

See truth table


PAD OE DI DOX 1 X In1 0 1 X0 0 0 X

PadBidirHE_SCMOS


Rev. APADBIDIR

Page2 of 4


Bi-Directional Pad PADBIDIR



Rev. APADBIDIR

Page3 of 4


Bi-Directional Pad Schematic PADBIDIR

EN

Data

Out

Pad

DataInB

DataIn

OEOE OEB

OEB

OEB

OEL=

'3*l

'T1

3bW=

'35*

l'

L='3

*l'

M=5

T3W=

'35*

l'

L='2

*l'

M=4

T5W=

'35*

l'

L='3

*l'

M=5

T6W=

'35*

l'L=

'3*l

'M=

14

TESD

N2W=

'175

*l'

L='3

*l'

M=6

T10

W='3

5*l'

L='3

*l'

M=6

T12

W='3

5*l'

L='2

*l'

T14b

W='3

5*l'

L='3

*l'

M=2

TESD

N1W=

'175

*l'

BOND

ING PAD

L='3

*l'

T13a

W='5

2*l'

L='3

*l'

M=5

T1W=

'52*

l'

L='3

*l'

M=4

T2W=

'52*

l'

L='3

*l'

M=5

T4W=

'52*

l'L=

'3*l

'M=

12

TESD

P2W=

'175

*l'

L='3

*l'

M=6

T9W=

'52*

l'L=

'3*l

'M=

6

T11

W='5

2*l'

L='3

*l'

T14a

W='5

2*l'

L='3

*l'

M=4

TESD

P1W=

'175

*l'

R1100


Rev. APADBIDIR

Page4 of 4


Bi-Directional Pad Layout PADBIDIR


Rev. APADFC

Page1 of 4


Pad Frame Corner PADFC

Description: Pad Frame Corner



Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdbCell: PADFC



N/A N/A N/A


Logic Equation

N/A



Rev. APADFC

Page2 of 4


Pad Frame Corner PADFC



Rev. APADFC

Page3 of 4


Pad Frame Corner Schematic PADFC

N/A


Rev. APADFC

Page4 of 4


Pad Frame Corner Layout PADFC


Rev. APADGND

Page1 of 4


Ground Pad PADGND

Description: Ground Pad


Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdbModule: PADGND

Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdbCell: PADGND



N/A N/A


Logic Equation

N/A


PadGnd


Rev. APADGND

Page2 of 4


Ground Pad PADGND



Rev. APADGND

Page3 of 4


Ground Pad Schematic PADGND

PadGnd

Pad

L='3*l'M=16

TESDP W='175*l'

BONDING

PAD


Rev. APADGND

Page4 of 4


Ground Pad Layout PADGND


Rev. APADINC

Page1 of 4


Input Pad PADINC

Description: Buffered Input Pad with Complementary Signals


Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdbModule: PADINC

Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdbCell: PADINC



N/A


Logic Equation

See truth table

Delay Characteristics:

PAD DI DIB0 0 11 1 0

Pad

DataInBPadInC_SCMOS

DataInPad

0.28nsTpd =

0.24nsTr =

0.18nsTf =


Rev. APADINC

Page2 of 4


Input Pad PADINC



Rev. APADINC

Page3 of 4


Input Pad Schematic PADINC

PadInC

DataInB

DataIn

Pad

Pad

PadBidirHE_SCMOS


Rev. APADINC

Page4 of 4


Input Pad Layout PADINC


Rev. APADIO

Page1 of 4


Input/Output Pad PADIO

Description: Input/Output Pad


Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdbModule: PADIO

Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdbCell: PADIO



N/A N/A


Logic Equation

N/A


PadIO


Rev. APADIO

Page2 of 4


Input/Output Pad PADIO



Rev. APADIO

Page3 of 4


Input/Output Pad Schematic PADIO

DATASIGNAL

PadIO

R1 100

L='3*l'M=16

TESDP W='175*l'

BONDING

PAD

L='3*l'M=16

TESDN W='175*l'


Rev. APADIO

Page4 of 4


Input/Output Pad Layout PADIO


Rev. APADSPACE

Page1 of 4


Padless Spacer PADSPACE

Description: Padless Spacer without Bonding Pad



Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdbCell: PADSPACE



N/A N/A N/A


Logic Equation

N/A



Rev. APADSPACE

Page2 of 4


Padless Spacer PADSPACE



Rev. APADSPACE

Page3 of 4


Padless Spacer Schematic PADSPACE

N/A


Rev. APADSPACE

Page4 of 4


Padless Spacer Layout PADSPACE


Rev. APADNC

Page1 of 4

Copyright

Pad NoConnect PADNC

Description: Pad Spacer with No Connection to Bonding Pad



Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdbCell: PADNC



N/A N/A N/A


Logic Equation

N/A



Rev. APADNC

Page2 of 4


Pad NoConnect PADNC



Rev. APADNC

Page3 of 4


Pad NoConnect Schematic PADNC

N/A


Rev. APADNC

Page4 of 4


Pad NoConnect Layout PADNC


Rev. APADOUT

Page1 of 4


Output Pad PADOUT

Description: Output Pad with Buffer


Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdbModule: PADOUT

Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdbCell: PADOUT



N/A


Logic Equation

Delay Characteristics:

PAD D00 01 1

DataOut Pad

PadOut_SCMOS

DataOutPad =

1.92nsTpd =

1.48nsTr =

1.23nsTf =


Rev. APADOUT

Page2 of 4


Output Pad PADOUT



Rev. APADOUT

Page3 of 4


Output Pad Schematic PADOUT

PadOut

DataOut

Pad

PadBidirHE_SCMOS


Rev. APADOUT

Page4 of 4


Output Pad Layout PADOUT


Rev. APADVDD

Page1 of 4


Power Pad PADVDD

Description: Power Pad


Schematic: S-Edit File: TannerLb\scmos\mTSMs035P.sdbModule: PADVDD

Mask layout: L-Edit File: TannerLb\scmos\mTSMs035P.tdbCell: PADVDD



N/A N/A


Logic Equation

N/A


PadVdd


Rev. APADVDD

Page2 of 4


Power Pad PADVDD



Rev. APADVDD

Page3 of 4


Power Pad Schematic PADVDD

PadVdd

PadBONDING

PAD

L='3*l'M=16

TESDN W='175*l'


Rev. APADVDD

Page4 of 4


Power Pad Layout PADVDD

mosis tsmc 0.35um hi-esd pad - auburn universitynelson/courses/elec5250_6250... · non-disclosure...

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