multi-generational test plan generation and execution in

Multi-generational Test Plan Generation and Execution in Advanced Mixed-

Signal Controllers

by

Shruti Eravelli, B.Tech.

A Thesis

In

ELECTRICAL ENGINEERING

Submitted to the Graduate Faculty

of Texas Tech University in

Partial Fulfillment of

the Requirements for

the Degree of

MASTER OF SCIENCE

IN

ELECTRICAL ENGINEERING

Approved

Dr. Richard Gale

Chairperson of the committee

Dr. Stephen Bayne

Peggy Gordon Miller

Dean of the Graduate School

May, 2011

Texas Tech University, Shruti Eravelli, May 2011

ii

Acknowledgements

I would like to first thank my advisor Dr. Richard Gale for his guidance and motivation

all through my coursework and professional career. He constantly monitored my progress

in this project and provided good suggestions which helped me refine my work. My

sincere thanks to Dr. Stephen Bayne for his readiness to serve as an important member in

my thesis committee.

I would like to express my sincere gratitude to Daniel Kimmitt at Texas Instruments,

Tucson, AZ, for being the manager he was. He gave me clear directions and checkpoints

to keep me on track and on time. Many thanks to Mickey and Jeff for patiently helping

me break down the big problems into manageable and solvable tasks and guiding me

throughout the project. I also thank Ben for his help anytime I needed it. I extend my

gratitude to all my team members at TI for their invaluable assistance throughout the

project.

Last but definitely not the least, many thanks to my parents for their encouragement and

support without which this would not have been possible.


iii

Table of Contents

Acknowledgements ............................................................................................................. ii

Abstract .............................................................................................................................. vi

List of Tables .................................................................................................................... vii

List of Figures .................................................................................................................. viii

I.Analog Monitoring and Control ....................................................................................... 1

1.1 AMC Applications .................................................................................................... 1

1.2 AMC Family Comparison ......................................................................................... 1

1.3 Test/Characterization Boards .................................................................................... 4

II.Integrated Circuit Packaging ........................................................................................... 7

2.1 IC Package Types ...................................................................................................... 7

2.1.1 Through-Hole Packages ..................................................................................... 7

2.1.2 Surface Mount Packages .................................................................................... 8

2.1.3 Contactless Packages .......................................................................................... 8

2.2 Quad Flat No Leads (QFN) ..................................................................................... 12

2.3 Quad Flat Package (QFP) ........................................................................................ 13

III.Hardware Interface – Board Design ............................................................................ 15

3.1 Printed Circuit Board .............................................................................................. 15

3.2 PCB Design Workflow............................................................................................ 17

3.3 AMC 7891 Daughter Board Design ........................................................................ 19

3.4 PCB Layout ............................................................................................................. 22

3.4.1 Trace Parasitics ................................................................................................. 23

3.4.2 Grounding ......................................................................................................... 24

3.4.3 Bypass Capacitors............................................................................................. 25


iv

3.5 PCB Materials ......................................................................................................... 25

IV.Software Interface – Labview ...................................................................................... 28

4.1 Introduction ............................................................................................................. 28

4.2 Advantages .............................................................................................................. 29

4.3 Front Panels ............................................................................................................. 30

4.4 Code Debug ............................................................................................................. 32

V.Digital To Analog Converter Characterization ............................................................. 34

5.1 DAC Architectures .................................................................................................. 35

5.1.1 String Architecture ........................................................................................... 36

5.1.2 String DAC Advantages ................................................................................... 37

5.2 DAC Testing ........................................................................................................... 37

5.2.1 Offset Error ....................................................................................................... 38

5.2.2 Offset Error Drift .............................................................................................. 38

5.2.3 Integral Non-Linearity ...................................................................................... 38

5.2.4 Differential Non-Linearity ................................................................................ 39

5.2.5 Gain Error ......................................................................................................... 40

5.2.6 Gain Error Drift ................................................................................................ 41

5.2.7 Full Scale Error ................................................................................................. 41

5.2.8 Digital Feedthrough .......................................................................................... 41

5.2.9 Glitch Impulse .................................................................................................. 42

5.2.10 Settling Time .................................................................................................. 42

5.2.11 Slew Rate ........................................................................................................ 43

VI.Analog To Digital Converter and GPIO Characterization .......................................... 45

6.1 ADC Architectures .................................................................................................. 45


v

6.1.1 Successive-Approximation Register ADC ....................................................... 45

6.2 ADC Testing ........................................................................................................... 46

6.2.1 Offset Error ....................................................................................................... 47

6.2.2 Integral Non-Linearity ...................................................................................... 48

6.2.3 Differential Non-Linearity ................................................................................ 48

6.2.4 Gain Error ......................................................................................................... 49

6.3 General Purpose Input/Output ................................................................................. 50

6.4 GPIO Results ........................................................................................................... 51

VII.Conclusion and Future Work ..................................................................................... 52

7.1 Conclusion ............................................................................................................... 52

7.2 Future Work ............................................................................................................ 52

Bibliography ..................................................................................................................... 54


vi

Abstract

Most integrated circuits are evolutionary. This is especially true in the realm of system-

on-a-chip (SoC) devices that combine multiple functions monolithically. Electronic

systems that begin life as an entire printed circuit board often see smaller and smaller

chip counts as designs mature. In some cases, functions will be combined into multichip

modules that co-locate separate integrated circuits in a single package to provide

additional levels of signal integrity and achieve cost reductions. This process continues

through stages that culminate in the monolithic integration of these separate chips. The

requirement to differentiate similar functions for different customers and applications

results in families of SOC’s with similar but not identical capabilities. As parametric and

functional testing become larger and larger contributors to total cost, avoiding duplication

of effort is a key factor maintaining competitive position and market share. The strategies

involved in achieving economies of scale that can be realized by recognizing the

similarities between family members while still providing for differentiation where

required is a subject of great interest currently. This work traces the development of test

capability in such a family through several generations. An approach that utilizes a

motherboard to take advantage of the similarities between family members and is

combined with specialized hardware realized in a series of daughter boards, and

differentiated software as well is described through several design iterations. Debugging

both hardware and software while looking for ways to streamline testing and further

reduce test time and cost is detailed. The result is a cost effective approach to advanced

device testing that does not compromise performance and provides for acceptable levels

of fault coverage.


vii

List of Tables

1.1 AMC family comparison .............................................................................................. 2

3.1 AMC 7891 mother board netlist mapping .................................................................. 20

6.1 GPIO results ................................................................................................................ 51


viii

List of Figures

1.1 AMC 7891 schematic ................................................................................................... 2

1.2 AMC 7824 schematic ................................................................................................... 3

1.3 AMC 7812 schematic ................................................................................................... 3

1.4 Board hierarchy ............................................................................................................. 4

1.5 AMC 7824 setup ........................................................................................................... 5

1.6 AMC 7812 setup ........................................................................................................... 5

2.1 IC package classifications ............................................................................................. 9

2.2 Through-hole mount package ..................................................................................... 10

2.3 Surface mount package ............................................................................................... 11

2.4 QFN cross-section ....................................................................................................... 13

2.5 QFP cross-section ....................................................................................................... 14

3.1 CAD-based PCB design and fabrication process........................................................ 18

3.2 AMC family mother board.......................................................................................... 19

3.3 AMC 7891 daughter board schematic capture............................................................ 22

3.4 AMC 7891 daughter board ground plane ................................................................... 24

3.5 AMC 7891 daughter board layout (layer 4 and all layers visible) .............................. 25

3.6 AMC 7891 daughter board (front and back View) ..................................................... 26

3.7 AMC 7891 setup ......................................................................................................... 26


ix

4.1 Example labview code ................................................................................................ 28

4.2 AMC characterization setup ....................................................................................... 29

4.3 AMC characterization labview panels ........................................................................ 31

4.4 Individual labview panels ........................................................................................... 32

5.1 Piecewise constant output of a conventional practical DAC ...................................... 34

5.2 Principal string architecture with voltage output ........................................................ 36

5.3 DAC offset error ......................................................................................................... 38

5.4 DAC integral non-linearity ......................................................................................... 39

5.5 DAC differential non-linearity .................................................................................... 40

5.6 DAC gain error ........................................................................................................... 40

5.7 DAC full scale error .................................................................................................... 41

5.8 Digital feedthrough in a DAC ..................................................................................... 42

5.9 DAC settling time measurement. ................................................................................ 43

5.10 Settling time and glitch energy ................................................................................. 43

6.1 Successive Approximation ADC Block Diagram ....................................................... 46

6.2 ADC offset error ......................................................................................................... 47

6.3 ADC integral non-linearity ......................................................................................... 48

6.4 ADC differential non-linearity .................................................................................... 49

6.5 ADC gain error ........................................................................................................... 49


1

Chapter I

Analog Monitoring and Control

System-on-a-chip (SOC) refers to integrating all components of a computer or other

electronic system into a single integrated circuit (IC). It may contain digital, analog,

mixed-signal, and often radio-frequency functions – all on a single chip substrate. An

Analog Monitoring and Control or AMC also falls under the same category, with

multiple functionality combined into multichip modules that co-locate separate integrated

circuits in a single package to provide additional levels of signal integrity.

1.1 AMC Applications

AMC typically has, like the name suggests, functional blocks of data converters, both

analog to digital (ADC) and digital to analog (DAC), general purpose input/output

(GPIO), temperature sensors etc. Their system and signal integrity makes them ideal for

applications such as RF power transistor gate bias control, industrial control, data

acquisition systems, communication equipment, optical networks, automatic test

equipment and other general analog monitoring and control systems. Depending on the

needs of the circuitry, different combinations of the functional blocks of AMC can be put

together to make a custom chip for a particular application or a particular customer.

Texas Instruments’ AMC 7824, 7812 and 7891 are such examples of functionally similar

but technically different analog monitoring and control integrated circuits.

1.2 AMC Family Comparison

As clearly seen in the block diagrams, all the three AMCs are functionally very similar

with similar modules put together on a single chip. It is the combination of blocks that

differentiates one from the other. The electrical characteristics and maximum ratings also

vary based on the design. In case of a custom chip, the customer/application where the

AMC is to be used decides a lot of these factors including the kind of packaging used.

Table 1.1 describes the differences and similarities briefly.


2

Table 1.1 AMC family comparison

AMC 7891 AMC 7824 AMC 7812

# of Pins 36 48 64

GPIO 12 X 8

ADC channels 8 8 16

# of DAC 4 4(5) 12

SPI 4 X 4

I2C X 2 2

Remote T Sensor X 2 2

DGND 1 3 2

AGND 2 2 4

Packaging QFN QFN, TQFP QFN

Supply AVdd, DVdd, IOVdd AVdd1. AVdd2,

AVcc, DVdd, IOVdd

AVdd1. AVdd2,

AVcc1, AVcc2,

DVdd, IOVdd

Figure 1.1 AMC 7891 schematic


3




4

1.3 Test/Characterization Boards

Every AMC is unique and each unique IC needs a unique custom board to

characterize/test it because of the difference in, for example, pin count, number of power

supplies, number of ADC and DAC channels, GPIO and temperature sensor count, etc. In

any case, creating one for each family eventually becomes a very inefficient way of

dealing with the testing process of the ICs. This is because, although the three AMC

family ICs are physically different from one another, they share a lot of common blocks,

to which level a common (mother) board can be used. The dissimilarities in the AMC

family can be taken care of by a custom (daughter) board which houses circuitry specific

to the IC. This approach saves the designers from designing the entire huge complex

circuitry again and again. Instead very limited time goes into designing the small custom

daughter board with limited circuitry, essentially only the pin connections to the

resources on the mother board. The motherboard can thus house circuitry which is

common to all the AMCs like power supplies and meter connections. All the common

switches, amplifiers and multiplexers that normally go into typical test boards for ICs can

now once and for all be placed on the motherboard and forgotten about even when a

completely new IC, AMC or not, is conceived. If in any case, there is a need for circuitry

which is not available on the motherboard, the designers always have the flexibility to

add it on the daughter board.

Figure 1.4 Board hierarchy

DUTDaughter

BoardMother Board


5

Figure 1.5 AMC 7824 setup


Some examples of the resources available on the motherboard are:

4 analog outputs of +/- 20 V

4 analog outputs of +/- 12.5 V

+/- 15 V and 5 V

12 lines for analog measurement (netlist: ANALOG_OUT1 to ANALOG_OUT12)

8 lines for analog measurement (netlist: MONITOR1 to MONITOR8)


6

Temperature sensor circuit

AMC 7891 can also share the same mother board that AMC 7824 and AMC 7812 use. Its

custom daughter board is designed using Mentor Graphics Design Capture. The kind of

socket used for housing the IC depends on the pin count, size of the IC and the kind of

packaging used. As IC speeds have increased and power supply voltages have decreased,

the function of the IC package has transitioned from that of a mechanical interconnect

which provides protection for the die from the outside environment to that of an electrical

interconnect that affects IC performance and which must be properly understood in an

electrical context. The same is discussed in chapter II.


7

Chapter II

Integrated Circuit Packaging

Integrated circuit packaging is the final stage of semiconductor device fabrication per se,

followed by IC testing. In the integrated circuit industry it is called simply packaging and

sometimes semiconductor device assembly, or simply assembly. Also, sometimes it is

called encapsulation or seal. The term packaging generally comprises the steps or the

technology of mounting and interconnecting of devices (1). Although it is possible to

attach chips directly to boards, placing chips in packages enables independent testing of

packaged parts, and eases requirements on board pitch and P&P (pick-and-place)

equipment. Package attributes that are taken into consideration when choosing a package

type for a particular semiconductor device include: size, weight, lead count, power

dissipation, field operating conditions, and of course, cost.

2.1 IC Package Types

Packages can be categorized as Through Hole, Surface Mount and Contactless packages.

2.1.1 Through-Hole Packages

Through-hole packages are perhaps the most common type of IC package. Their defining

quality is one or more rows of leads (short metallic posts that conduct signals to and from

the device) designed to pass through holes on a circuit board for soldering or into an

optional socket designed to receive them. The number of leads on a through-hole package

can vary from 3 to 64 and their bodies are made from either plastics or ceramics.

Common versions of these packages have one row of leads called a "single inline

package" (SIP), two rows of leads called a "dual inline package" (DIP) or a grid

arrangement of leads called a “pin grid array” (PGA).


8

2.1.2 Surface Mount Packages

Like through-hole packages, most surface mount packages have leads provided to solder

the package to a circuit board. They do not pass through holes or fit into a socket,

however. Instead, they are bent at an angle near the end to form a foot to facilitate

soldering to the surface of a circuit board; however, ball grid arrays (BGA) are the

exception to this rule. The number of leads on surface mount packages can range from 4

to 1,312 and their bodies can be constructed from ceramics, plastics, metals or a

combination of the three. Common types of surface mount packages include small outline

(SO) packages, with a single row of leads and flat packs (FP), which have leads on two or

four sides of the package.

Technically, ball grid array packages are surface mount packages; however, unlike all

other surface mounts, they do not have solderable leads in a few straight rows. Instead,

their leads are ball shaped and arranged in a grid pattern on the underside of the package.

The BGA IC is positioned on a circuit board and held against contacts on the board with

pressure from a clip or other spring mechanism. BGA packages can have from 56 to

1,312 leads and their bodies are constructed from either plastics or ceramics.

2.1.3 Contactless Packages

Contactless packages are the newest type of IC to enter widespread use. Unlike most ICs,

contactless ICs do not come into direct physical contact with a circuit board. Instead, they

are scanned to provide information to other devices wirelessly. Contactless packages

have no leads and are made only with plastic bodies. They are used heavily in

identification applications, such as those used to identify shipping units, in scannable

identification cards or surgically implanted into pets to identify them to their owners

should they be lost (2).


9

Figure 2.1 IC package classifications


10

Figure 2.2 Through-hole mount package


11

Figure 2.3 Surface mout package


12

2.2 Quad Flat No Leads (QFN)

The QFN package is a lead-less, near Chip Scale Package (CSP) with low profile (1.0mm

and less), moderate thermal dissipation and good electrical performance. It is a surface

mount plastic package with leads located at the bottom of the package. It includes an

exposed thermal pad to improve heat transfer out of the IC (into the PCB). Heat transfer

can be further facilitated by metal vias in the thermal pad. As the package size shrinks

and the lead count increases, the dimensional tolerance and positioning accuracy affects

subsequent processes. Special care must be taken when preparing for test, especially in

the test contactor cavity design and contactor pin location. Further down the process, the

PCB layout and stencil designs are critical to ensure sufficient solder coverage between

the package and the Printed Circuit Board (PCB). The small size of the exposed contacts

and the large area of exposed thermal pad make it easy for small parts to float on the pool

of molten solder under the thermal pad during assembly. This causes the parts to make no

contact to the printed circuit board pads in some instances. Due to the excellent thermal

characteristics of this mounting package, it is very hard to rework the device, as hot air

reflow typically does not offer enough heat to the thermal pad without damage to

surrounding board material or parts. Oxidation of the exposed chip contact pads after

being exposed to a reflow oven during initial assembly makes solder wetting to them

during rework quite difficult. Additionally there is no clearance for a soldering pencil to

reflow pads under the chip if touch up is desired. Sometimes contact can be made up the

sides of the QFN package contact pads, but this does not work well in practice. However,

Low standoff heights, reduced lead inductance, small size and weight coupled with

excellent thermal and electrical properties make the QFN an ideal choice for a wide range

of applications. Cell phones, PDAs, portable music and video players can significantly

benefit from this package (3).


13

Figure 2.4 QFN cross-section

2.3 Quad Flat Package (QFP)

The Quad Flat Package (QFP) is a high lead count and four-sided package with lead

extending from the component body on all four sides, predominantly used to house

ASIC, logic, and processor devices. QFP components packaged in trays or on tape and

reel to protect the component lead that can be easily damaged. It is ideal for

semiconductor technologies such as ASIC, SDP, controllers, processors, gate arrays

(FPGA/PLD), SRAMS and PC chip sets. It is also particularly suitable for light-weight

portable electronics requiring broad performance, such as laptop PCs, video/audio,

telecom, cordless/RF, data transmission, office automation, disc drives and

communication boards (Ethernet, ISDN). TQFP family is a reduced body thickness

plastic package. This package type is constructed using the latest wire bonding and

molding technology to provide surface mount with a nominal body thickness of 1.0mm.

It is suitable for applications where height and weight are a critical factor. TQFP give

designers the needed low profile margin in designing and producing high performing

products such as disk drives, pagers, wireless, CATV/RF modules, radio and other

similar applications.


14

Figure 2.5 QFP cross-section

Based on the type of packaging used, the IC size and pin count, the sockets are decided

for use on a printed circuit board. The procedure and workflow of PCB design is

discussed in chapter III.


15

Chapter III

Hardware Interface – Board Design

3.1 Printed Circuit Board

One of the common debates in test engineering is the choice between hand-wired

prototype boards versus printed circuit boards (PCB). Hand-wired boards can be quickly

constructed from prefabricated blank prototype boards. The alternate approach is to

produce a production-worthy custom PCB version of the same board without first

building a hand-wired prototype. PCB is a component made of one or more layers of

insulating material with electrical conductors. The insulator is typically made on the base

fiber reinforced resins, ceramics, plastics, or some other dielectric materials. During

manufacturing, the portions of conductors that are not needed are etched off, leaving

printed circuits that connect electronic components. Weather a PCB is single-sided,

double-sided or multi-layered; there is a standard that provides rules for

manufacturability and quality such as requirements for material properties, criteria for

surface plating, conductor thickness, component placement, dimensioning and tolerance

rules and more. For example, the width of the circuit conductors should be chosen based

on the maximum temperature rise at the rated current and the acceptable impedance. The

spacing between the PC traces is determined by peak working voltage, the coating and

the product application. The minimum possible widths of traces and of spacing between

them are both limited by the manufacturing capabilities. The effects of non-zero trace

impedance and the coupling of signals from one circuit to another through parasitic

capacitance and radio transmission should also be considered. Thus, good PCB design

and layout techniques require a basic understanding of circuit operation.

Although the hand-wired approach results in rapid turn-around at relatively low

production cost, the resulting board is typically not very production worthy, since the

loose wires are easily broken. Also, hand-wired boards may not give the same high-

quality electrical performance that can be achieved using PCBs. When multiple boards


16

are required, then the PCB approach is usually the superior solution. PCBs are easily

manufactured in quantity, they are mechanically robust during debug and production,

they provide superior electrical performance, and they provide good consistency (i.e.,

correlation) from one board to another. Correlation between hand-wired DIBs can be

very problematic, since each is electrically unique depending on the exact length and

physical layout of the wires on each board. At very high frequencies, hand-wired boards

are often useless, since they can produce incorrect readings due to their inferior electrical

characteristics. PCBs can be designed, laid out, and fabricated in a matter of a week or

two with the use of computer-aided design (CAD) tools.

To achieve a rapid turn-around with minimal errors, a netlist-based CAD tool for design

and layout should be employed. A netlist is a database describing each interconnection in

the circuit. In addition to the point-to-point interconnection information, the netlist also

includes such information as the footprint, or shape, of each component in the circuit. A

footprint represents the mechanical specification of the component's package.

Information such as pin locations, pad sizes, hole sizes, and package outline shapes to be

printed on the finished PCB are included in the footprint description for each type of

component. Using a netlist-compatible schematic capture tool, the circuit schematic is

drawn on a computer workstation or PC. Then the schematic database (including the

netlist) is used in the board layout process. Once the netlist has been extracted from the

database, laying out the board from a standard template begins. The board template

database represents a head start board design, which includes the shape of the board and

its standard mechanical mounting holes as well as many preplaced standard components,

such as tester connectors. The netlist directs the PCB layout software to import all the

required DlB components from a standard parts library. These components are then

placed and connected as shown in the schematic. The netlist prevents errors in point-to-

point interconnections by refusing to place traces in the layout where they do not belong.

The netlist also guarantees that none of the desired connections are mistakenly omitted.

Once the board layout is completed, each layer of the design is plotted onto transparent


17

film for use in PCB fabrication. These plots are commonly known as Gerbers, or Gerber

plots (4).

3.2 PCB Design Workflow

Step 1: Finalize Circuit Design – The Process of PCB design starts with the circuit

design. Circuits can either be hand drawn and later captured electronically, or the circuit

design can be captured directly into a schematic.

Step 2: Choose PCB Design Software – It is important to choose a package that is first

and foremost easy to use, but also capable of completing the PCB design as some

packages won’t be able to handle the complexity. Also, PCB designing to a great extent

needs details of the circuit operation and critically of the components location. Hence,

professional schematic capture software should have the flexibility to set various

constraints for specific nets or groups of components.

Step 3: Capture The Schematic – The circuit design can also be captured electronically

from the start. In general “capturing the schematic” is the process by which each

component is drawn electronically and are interconnected with each other.

Step 4: Design Component Footprints – Once the schematic is complete, the physical

outline of each of the components is drawn. These outlines are what are placed on the

PCB in Copper to allow the components to be soldered to the printed wiring board.

Step 5: Establish PCB Outline – Each project has restrictions related to the board

outline. This should be determined in this step since an idea of component count and area

should be known.

Step 6: Setup Design Rules – With the PCB outline and footprints complete, the

placement should start. Before placement though, the design rules should be setup to

ensure, for example, that components or traces aren’t too close together.


18

Step 7: Place Components – Move each component onto the PCB and make all those

components fit together.

Step 8: Manually Route Traces – It’s necessary to manually route critical traces

(clocks, power sensitive analog traces). Once that is complete, the auto router can be

used.

Step 9: Using the Auto Router – There are a handful of rules that will need to be

applied for using an auto router as well, but doing so will save manual trace routing time.

Step 10: Run Design Rule Checker – PCB design software packages have a very good

setup of design rule checkers. It is easy to accidentally violate PCB spacing rules and this

will pinpoint the error saving the designer from having to respin the PCB.

Step 11: Output Gerber Files – Once the board is error free, the gerber files can be

released. A gerber file is a file format used by PCB manufacturing machines to lay out

electrical connections such as traces, vias, and pads (the component footprints on the

PCB). A Gerber file can also contain information for drilling and milling the circuit board

(5).

Figure 3.1 CAD-based PCB design and fabrication process


19

3.3 AMC 7891 Daughter Board Design

AMC 7891 needed a custom daughter board to interface to the Mother board which had

all the major resources required to characterize it. The interface is through 4 connectors

on the daughter board which had 40 pins each. Each pin is connected to a corresponding

pin on the mother board which is in turn connected to a resource (supplies, meters,

ground etc.). The resources were thus extended to the custom daughter board and in turn

to the DUT. The DUT is contained in a custom socket with as many pins as the DUT.

Figure 3.2 AMC family mother board

AMC 7891’s 8 channel ADC input pins are connected to supply lines for analog inputs to

the converter. The 4 DAC channels are connected to 4 lines to meter to measure the

output. The 12 GPIO pins are connected to switch between digital input lines and meters

depending on their configuration. The 3 ground pins, 3 power lines, and the 4 pins for

I2C communication are connected to the corresponding lines. Mentor Graphics Design

Capture is used because of the flexibility it offers and also primarily because its library

had all the components needed. Table 3.1 shows the list of net names on AMC 7891

daughter board design.


20

Table 3.1 AMC 7891 mother board netlist mapping

Pin # Pin Name Motherboard Net Name Description

1 AVDD DAC2B Supply +/- 20V

2 AGND1 DMM_LO3 Meter ground

3 DGND DGND1 Ground

4 DVDD DAC4_A Supply +/-12.5V

5 IOVDD DAC4_B Supply +/-12.5V

6 SYNC DIG/DRV_IN11 Digital line

7 SCLK SCLK_SCL Clock

8 DIN SDI_SDA SPI/I2C Communication

9 DOUT DIG/DRV_OUT3 Digital line

10 A_OUT4 ANALOG_OUT4 To meter

11 A_OUT3 ANALOG_OUT5 To Meter



14 AGND2 DMM_LO3 Meter Ground

15 GPIO-C4 MONITOR4/DAC3A To Meter/Supply



21

Table 3.1 Continued




19 DAV DIG/DRV_OUT2 Digital line

20 GPIO-B4 ANALOG_OUT10/DAC2A To Meter/Supply




24 GPIO-A4 ANALOG_OUT6/DAC5B To Meter/Supply


26 GPIO-A2 ANALOG_OUT2DAC5B To Meter/Supply


28 A_IN1 ADC_DIF2B ADC Diff i/p

29 A_IN2 ADC_DIF2A ADC Diff i/p

30 A_IN3 ADC_DIF1B ADC Diff i/p

31 A_IN4 ADC_DIF1A ADC Diff i/p

32 A_IN5 ADC/DIG3 ADC SE i/p


22





36 REF_IN/REF_CMP DAC3B/MONITOR7 Supply+/-20V/To Meter

Figure 3.3 AMC 7891 daughter board schematic capture

3.4 PCB Layout

The connections on the PCB should be identical to the circuit diagram, but while the

circuit diagram is arranged to be readable, the PCB layout is arranged to be functional, so

there is rarely any visible correlation between the circuit diagram and the layout. PCB

layout can be performed manually (using CAD) or in combination with an Auto router.

The best results are usually still achieved using atleast some manual routing - simply

because the engineer has a far better judgment of how to arrange circuitry. The details of


23

the circuit operation and critically of components location are very important while

laying out the board. Schematic capture tools allow us to set various constraints for

specific nets or groups of components. Particularly, one can specify minimum line width,

net spacing type, and even maximum and relative signal propagation delays.

3.4.1 Trace Parasitics

One of the most important components on a PCB is the trace. It is easy to think that wires

and traces are not components at all, but are instead represented by the connecting lines

that appear in a schematic. However, PCB traces (and wires in general) are slightly

resistive, slightly inductive, and slightly capacitive in nature. These non ideal circuit

characteristics are known as parasitics. Often, trace parasitics can be ignored, especially

when working with low frequencies and low to moderate current levels. Other times, the

parasitics will have a significant effect on a circuit's behavior. The test engineer should

always be aware of the potential problems that trace parasitics might pose.

The parasitic resistance of a PCB trace is directly proportional to the length of the trace,

and inversely proportional to the height and width of the trace. The equation for

resistance in a uniform conductive material with a rectangular cross section is

R= Ltrace/σWT

where R = trace resistance, Ltrace = trace length, W= trace width, T = trace thickness,

and σ is the conductivity of the trace material.

The inductance of a trace depends on the shape and size of the trace, as well as the

geometry of the signal path through which the currents flow to and from the load

impedance. The inductance of a trace over a ground plane (a configuration known as a

stripline) is dominated by the ratio of the trace-to-ground spacing, D, divided by the trace

width, W. The parasitic inductance of a wide trace routed over a ground or power plane

can be estimated using the equation


24

L = µoµrD/W

where L = Inductance per unit length (henrys per meter), µo = magnetic permeability of

free space (400π nH per meter), µr = magnetic permeability of the PCB material divided

by µo, W = trace width, and D = separation between trace and ground plane.

The capacitance between two parallel traces can be estimated using the standard parallel

plate capacitance equation. The parasitic capacitance between two metal plates of area A

is given by the equation

C=εoεrA/D

3.4.2 Grounding

High frequency circuit design requires careful grounding. The “ground” in a circuit is

supposed to be at one potential, but in reality it is not. When ground currents flow

through traces which have non-zero impedance, voltage differences will occur at different

points along the ground path. To minimize these voltages, “ground plane” is used for

control circuit. Most of the signal ground connections are made through vias to this

ground plane rather than through PC traces. For each power supply stage, power ground

and control ground are kept separately.

Figure 3.4 AMC 7891 daughter board ground plane


25

3.4.3 Bypass Capacitors

A bypass or decoupling capacitor is a capacitor used to decouple one part of an electrical

network (circuit) from another. Noise caused by other circuit elements is shunted through

the capacitor, reducing the effect they have on the rest of the circuit. The capacitor is used

to bypass the power supply or other high impedance component of a circuit, Hence the

name Bypass Capacitor. A transient load decoupling capacitor and power supply

decoupling bypass capacitor should usually be placed as close as possible to the device

requiring the decoupled signal and the voltage/current respectively. The goal is to

minimize the amount of line inductance and series resistance between the decoupling

capacitor and the supplied device, and the longer the conductor between the capacitor and

the device, the more inductance there is. AMC 7891 daughter board has bypass

capacitors for the input pins of the 8 channel ADC, the 3 power supplies and the external

reference pin.

Figure 3.5 AMC 7891 daughter board layout (layer 4 and all layers visible)

3.5 PCB Materials

Printed circuit boards can be constructed using a variety of materials. The most common

trace material is copper, due to its excellent electrical conductivity. Insulating layers

dielectric are typically laminated together with epoxy resin prepreg. The board is

typically coated with a solder mask that is green in color. The most common insulator


26

material is FR4 (fire retardant, type 4) fiberglass. Fiberglass is an inexpensive material

that exhibits good electrical properties up to several hundred megahertz. Thermal

expansion is an important consideration and glass fiber offers the best dimensional

stability. As frequencies approach 1 GHz, more exotic materials such as Teflon or cynate

ester may be needed. Teflon exhibits excellent microwave characteristics including low

signal loss and a low dielectric constant. However, it suffers from poor mechanical

stiffness. Cynate ester is a material with reasonably good high frequency properties and

yet it is stiff enough to withstand the mechanical stress involved in the process of

(production) testing (4).

Figure 3.6 AMC 7891 daughter board (front and back View)



27

The progress of very large scale integration (VLS1) technology has brought tremendous

improvement in chip performance as well as gate density. The increasing complexity,

however, renders the testing of a chip much more difficult. For large circuits, manual

testing is quite time consuming and prone to faults. Test time reduction is thus a major

concern in the semiconductor industry today. The remedy is naturally to take into account

automation of characterization and test process. For characterization on bench equipment,

Labview offers a dynamic platform to automate the procedure. More on Labview in

chapter IV.


28

Chapter IV

Software Interface – Labview

4.1 Introduction

Labview (short for Laboratory Virtual Instrumentation Engineering Workbench) is a

platform and development environment for a visual programming language from

National Instruments. The purpose of such programming is automating the usage of

processing and measuring equipment in any laboratory setup. Labview ties the creation of

user interfaces (called front panels) into the development cycle. Labview

programs/subroutines are called virtual instruments (VIs). Each VI has three components:

a block diagram, a front panel and a connector panel. The last is used to represent the VI

in the block diagrams of other, calling VIs. Controls and indicators on the front panel

allow an operator to input data into or extract data from a running virtual instrument.

However, the front panel can also serve as a programmatic interface. Thus a virtual

instrument can either be run as a program, with the front panel serving as a user interface,

or, when dropped as a node onto the block diagram, the front panel defines the inputs and

outputs for the given node through the connector pane. This implies each VI can be easily

tested before being embedded as a subroutine into a larger program.

Figure 4.1 Example labview code


29

Labview codes can be written just like any other programming language like C. The only

difference is the graphical interface. The example code in figure 4.1 generates a random

number, multiplies it with 10 and displays it continuously, until it is stopped. The

rectangular box is a while loop which executes the code inside it until its “stop” condition

is met, which in this code is done by clicking the stop button. After each iteration, the

while loop waits for 800ms before executing the next one. The number of iterations “i” is

displayed on the front panel using an indicator.

4.2 Advantages

Labview is used in the setup for AMC characterization as well.

Figure 4.2 AMC characterization setup

It offers the benefit of extensive support for accessing instrumentation hardware. The

fully modular character of Labview code allows code reuse without modifications; many

libraries with a large number of functions for data acquisition, signal generation,

mathematics, statistics, signal conditioning, analysis, etc., along with numerous graphical

interface elements make labview a very convenient and desirable tool.

Labview


30

4.3 Front Panels

The electrical characteristics of AMC modules are all characterized using labview

interfaces. The complete front panel is built/divided into separate panels for each set of

electrical characteristics. There is a separate front panel for each of the following:

Power switches and power levels

IC communication

IC Registers

Temperature sensors

ADC Linearity

DAC Linearity

Other switches and relays

Thus many electrical characteristics of the functional blocks of all AMCs are

characterized/tested using different combinations of these panels under desirable

conditions by changing the variables on the panels. Power levels are set to the desired

number using controls. Registers are set to default values or are changed on the

register panel based on our desired conditions. “Globals” are used to define variables

that are present in all the three AMCs. (ex.: DAC resolution, ADC resolution, GPIO

count, DAC channel count, ADC channel count). Based on the AMC selected at the

beginning of the test process, these global variables assume values related to that

particular AMC. All in all, the programming method is like that of “if-else” statement

in programming language C.

if(AMC=7824)

............

……….

else if(AMC=7812)


31

............

……….

else if(AMC=7891)

............

……….

Labview thus provides huge flexibility to the user to create different working

conditions for the IC under test. As need arises, more functionality can be added to

the same labview program. For example, although initially the labview program was

meant for characterizing AMC 7824, AMC 7812 and AMC 7891 were also made.

Both the new AMCs had GPIOs which were absent in AMC 7824. Hence, initially

there was no VI built for testing the GPIOs. But a separate panel could be added to

the same labview program keeping the already existing functionality intact.

Additional panels thus added are:

GPIO load/short circuit current

DAC load/short circuit current

DAC cross talk

Code versus supply current

Figure 4.3 AMC characterization labview panels


32

Figure 4.4 Individual labview panels

4.4 Code Debug

Writing (read: drawing) code for a particular function and making a VI out of it to use it

as a sub-VI in a parent VI is always recommended. A top-down approach while writing

the labview code is always better than putting all the code on one single VI. Nested VIs

make debugging easier. Each VI can be isolated from the other and tested by individually

running it. Thus bad code can easily be quarantined from the good. Also this approach

makes it possible for using Vis individually or as a part of a bigger structure. Individual

VIs can also be borrowed for use in other codes, saving the engineer time and effort it

would take to duplicate them.

Some code for often used functions like data collection and storing in a spreadsheet can

be written as a separate generic VI. This allows for simply dropping in this VI wherever

there is a need for collecting data. Ofcourse the labels and format for the spreadsheet may

differ and can be taken care of with external coding.


33

Event driven coding is also a recommended approach. Event cases are triggered by

respective events, say clicking a button. This helps isolate each event and see the results

individually. Also, in case there is error in a particular event, it is easier to debug the code

because of code isolation.

Once the bench setup is ready, the characterization process can begin. More number of

electrical characteristics and parameters can be tested in relatively less time due to

automation using Labview. The electrical characteristics of digital to analog converters of

the AMCs are discussed in chapter V.


34

Chapter V

Digital To Analog Converter Characterization

A digital-to-analog converter (DAC or D-to-A) is a device that converts a digital (usually

binary) code to an analog signal (current, voltage, or electric charge). A typical DAC

converts abstract finite precision numbers into a concrete sequence of impulses that are

then processed by a reconstruction filter using some form of interpolation to fill in data

between the impulses. Other DAC methods produce a pulse-density modulated signal that

can then be filtered in a similar way to produce a smoothly varying signal. However,

even with an ideal reconstruction filter, digital sampling introduces quantization error that

makes perfect reconstruction practically impossible. Increasing the digital resolution (i.e.,

increasing the number of bits used in each sample) or introducing sampling dither can

reduce this error. Instead of impulses, usually the sequence of numbers updates the

analog voltage at uniform sampling intervals. These numbers are written to the DAC,

typically with a clock signal that causes each number to be latched in sequence, at which

time the DAC output voltage changes rapidly from the previous value to the value

represented by the currently latched number. The effect of this is that the output voltage

is held in time at the current value until the next input number is latched resulting in a

piecewise constant or 'staircase' shaped output.

Figure 5.1 Piecewise constant output of a conventional practical DAC


35

5.1 DAC Architectures

Although the DAC is seen mainly as a black box where digital data goes in and a

representative analog signal comes out, there is much more to it. The digital data can be

either in a serial or parallel data format. Interfaces such as SPI or I2C, which transmit the

digital data stream serially, are like a necklace or chain into the "black box," whereas the

parallel interface loads all necessary bits in one clock cycle into the device. On the other

side of the device, the analog output signal is either a voltage or a current. The different

input interfaces offer variation in the form of the data format and, therefore, in speed, pin

count, chip area, device size, and flexibility. However, both serial and parallel interfaces

will get the digital data into the device. Once the digital data is within the black box, an

input register takes care of operations such as the serial-to-parallel conversion, or in

multi-channel devices stores the data until it is transferred to the individual DAC

registers. The DAC register, which is the connection between the input register and the

DAC architecture, acts like a memory and stores the digital data. In the first days of DAC

design, this DAC register was an external memory block which held the digital data.

Without the DAC register, the output of the DAC would change immediately with any

changes on the external input bus, due to the real-time feeding of the analog circuitry.

The data stays in the DAC register until the user decides to update the DAC register with

new code. The DAC register essentially acts like a flip-flop.

The most common types of electronic DACs are pulse width modulator, over-sampling,

binary weighted, R-2R ladder, string and hybrid DACs, which use a combination of these

techniques in a single converter. There are two principle architectures used in today's

precision DACs, the R2R and string. AMCs use string architecture DACs. Both

architectures are analog circuits with some digital control logic. With a basic R2R

architecture, it is possible to either generate a current output or a voltage output. String

architectures can only generate voltage outputs by using an output buffer. There is no

output buffer implemented in the case of a current output (6).


36

5.1.1 String Architecture

The string architecture is as the name implies, a series of resistors placed in series to

build a string. In theory, one would need 256 resistors to build an 8-bit DAC (28 = 256).

Figure 5.2 shows string architecture, including the internal output buffer generating a

voltage output which is equivalent to the digital input code.

Figure 5.2 Principal string architecture with voltage output

Increasing the resolution means also increasing the number of resistors needed to build a

string DAC. For a 16-bit DAC, one would need a total of 65,536 resistors to generate all

the possible voltages/digital steps. However, in the real world of design it is impractical

to implement nearly 66 thousand resistors on a single chip, especially with today's

requirements of small packages, low power dissipation, and low cost. Hence, designers

came up with additional smaller circuitry such as interpolating amplifiers that reduce the

necessary amount of resistors, and tapping points on the resistor string, allowing a more

power-efficient and less space-consuming design. The interpolating amplifier is used as

an output buffer (7).


37

5.1.2 String DAC Advantages

Advantages of string DACs are low cost and guaranteed monotonicity. Also important, it

offers low power and small die area, which allow for small packages, making them

desirable in portable applications. Another advantage is that the output buffer is already

included, which eliminates the need for an additional external component on the board.

Secondly, the output buffer isolates internal resistors and analog circuitry from the

outside world. This is quite helpful in low-impedance circuitry. Many applications

require low-glitch energy, which is another benefit of string architecture. However, due

to the higher impedance of the string design, the noise is generally higher than in R2R

architectures.

5.2 DAC Testing

There are a number of parameters that define an IC. These parameters have to meet the

specifications in order for the IC to function desirably. It’s the responsibility of the

characterization engineer to set the specifications right and responsibility of the test

engineer to make sure those are met. There are a number of such defining parameters for

a DAC too. In AMC 7891, the DACs are tested under the following conditions:

AVdd=5 V

Vref=2.5 V

Gain=2

Range=5-0=5 V (unipolar)

Resolution=10 bits

Least Significant Bit (LSB) voltage=5/(2^10)=4.88 mV

Temperature=room(25°C), hot(110°C) and cold(-45°C)


38

5.2.1 Offset Error

Offset error, often called 'zero-scale' error, indicates how well the actual transfer function

matches the ideal transfer function at a single point. For an ideal data converter, the first

transition occurs at 0.5 LSB above zero. For a DAC, offset error is the analog output

response to an input code of all zeros.

Figure 5.3 DAC offset error

At room temperature (25°C), the DAC has a maximum offset error of ±10 mV.

5.2.2 Offset Error Drift

Offset-error drift is the variation in offset error due a change in ambient temperature,

typically expressed in ppm/°C. The offset error temperature coefficient is found to be

typically ±1 ppm/°C.

5.2.3 Integral Non-Linearity

Integral nonlinearity (INL) is a term describing the maximum deviation between the ideal

output of a DAC and the actual output level (after offset and gain errors have been

removed). INL is often called 'relative accuracy.' The maximum INL of DAC under all

possible conditions is ±1 LSB.


39

Figure 5.4 DAC integral non-linearity

5.2.4 Differential Non-Linearity

For a DAC, DNL error is the difference between the ideal and the measured output

responses for successive DAC codes. An ideal DAC response would have analog output

values exactly one code (LSB) apart (DNL = 0). (A DNL specification of greater than or

equal to 1LSB guarantees monotonicity).


40

Figure 5.5 DAC differential non-linearity

Typically the DNL is measured around ±0.3 LSB, but will not exceed a maximum of ±1

LSB under all possible working conditions.

5.2.5 Gain Error

The gain error of a DAC indicates how well the slope of an actual transfer function

matches the slope of the ideal transfer function. Gain error is usually expressed in LSB or

as a percent of full-scale range (%FSR), and it can be calibrated out with hardware or in

software. Gain error is the full-scale error minus the offset error. Typically gain error for

this DAC is around ±0.025 %FSR. Under any condition it will not go beyond ±0.15

%FSR.

Figure 5.6 DAC gain error


41

5.2.6 Gain Error Drift

Gain-error drift is the variation in gain error due to a change in ambient temperature,

typically expressed in ppm/°C and it is typically found to be ±1 ppm/°C.

5.2.7 Full Scale Error

Full-scale error equals offset error + gain error, as shown in the figure. At room

temperature and a full scale range of 5V this error is a maximum of ± 10 mV.

Figure 5.7 DAC full scale error

5.2.8 Digital Feedthrough

Digital feedthrough is the noise that appears on a DAC output when the digital control

lines are toggled. In the figure, feedthrough on the DAC output is the result of noise from

the serial clock signal. When /CS is high, digital feedthrough is typically found to be 0.15

nV-S (8).


42

Figure 5.8 Digital feedthrough in a DAC

5.2.9 Glitch Impulse

Glitch impulse is the voltage transient that appears at the DAC output when a major-carry

transition occurs. Typically measured as nV•s, it equals the area under the curve on a

voltage-vs-time graph. At the major-carry transition (around mid-scale), either the MSB

changes from low to high and all other bits change from high to low, or the MSB changes

from high to low and all other bits change from low to high. For example, 01111111 to

10000000 is a major-carry transition. Major-carry transitions often produce the worst

switching noise. Here, digital to analog glitch energy is measured when code changes

from 0x7FFh to 0x800h and from 0x800h to 0x7FFh and is found that it is typically

around 0.15 nV-S.

5.2.10 Settling Time

For a DAC, settling time is the interval between a command to update (change) its output

value and the instant it reaches its final value, within a specified percentage. Settling time

is affected by the slew rate of an output amplifier and by the amount of amplifier ringing

and signal overshoot. Output range is set to 0 to 5 V. When code is changed from 0020h

to FD0h, time it takes to reach 0.5LSB is measured under load conditions of RL= 2kΩ

and CL =200 pF, and is found to not exceed 5µs.


43

Figure 5.9 DAC settling time measurement (a) referenced to a digital signal; (b)

reference to the DAC output 50% point.

5.2.11 Slew Rate

Slew rate is the maximum rate at which a DAC output can change. For a DAC with

output amplifier, the specified slew rate is typically that of the amplifier. The output

voltage of AMC DAC changes at a maximum rate of 2.2 V/µs.

Figure 5.10 Settling time and glitch energy


44

Just like DACs, the ADCs, either independently or along with other functional blocks of

AMC, have to be characterized and tested for their parameters. The same is discussed in

the following chapter.


45

Chapter VI

Analog To Digital Converter and GPIO Characterization

An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device which

converts a continuous quantity to a discrete time digital representation. The digital output

may use different coding schemes. An ADC may also provide an isolated measurement.

It performs the reverse operation of a digital-to-analog converter (DAC).

6.1 ADC Architectures

The most common ways of implementing an electronic ADC are direct conversion or

flash ADC, ramp-compare, Wilkinson, integrating (also dual-slope or multi-slope ADC),

delta-encoded or Counter-ramp, pipeline (also called sub-ranging quantizer), Sigma-Delta

(also known as a Delta-Sigma), Time-interleaved, ADC with intermediate FM stage, and

successive-approximation ADC. The AMC family uses successive-approximation

register or SAR ADCs in their architecture.

6.1.1 Successive-Approximation Register ADC

A SAR ADC uses a comparator to reject ranges of voltages, eventually settling on a final

voltage range. Successive approximation works by constantly comparing the input

voltage to the output of an internal digital to analog converter (DAC, fed by the current

value of the approximation) until the best approximation is achieved. At each step in this

process, a binary value of the approximation is stored in a successive approximation

register (SAR). The SAR uses a reference voltage (which is the largest signal the ADC is

to convert) for comparisons. For example if the input voltage is 60 V and the reference

voltage is 100 V, in the 1st clock cycle, 60 V is compared to 50 V (the reference, divided

by two. This is the voltage at the output of the internal DAC when the input is a '1'

followed by zeros), and the voltage from the comparator is positive (or '1') (because 60 V

is greater than 50 V). At this point the first binary digit (MSB) is set to a '1'. In the 2nd

clock cycle the input voltage is compared to 75 V (being halfway between 100 and 50 V:


46

This is the output of the internal DAC when its input is '11' followed by zeros) because

60 V is less than 75 V, the comparator output is now negative (or '0'). The second binary

digit is therefore set to a '0'. In the 3rd clock cycle, the input voltage is compared with

62.5 V (halfway between 50 V and 75 V: This is the output of the internal DAC when its

input is '101' followed by zeros). The output of the comparator is negative or '0' (because

60 V is less than 62.5 V) so the third binary digit is set to a 0. The fourth clock cycle

similarly results in the fourth digit being a '1' (60 V is greater than 56.25 V, the DAC

output for '1001' followed by zeros). The result of this would be in the binary form 1001.

This is also called bit-weighting conversion, and is similar to a binary search. Because the

approximations are successive (not simultaneous), the conversion takes one clock-cycle

for each bit of resolution desired. The clock frequency must be equal to the sampling

frequency multiplied by the number of bits of resolution desired. For example, to sample

audio at 44.1 kHz with 32 bit resolution, a clock frequency of over 1.4 MHz would be

required. ADCs of this type have good resolutions and quite wide ranges. They are more

complex than some other designs (9).

Figure 6.1 Successive Approximation ADC Block Diagram

6.2 ADC Testing

In AMC 7891, the ADCs are tested under the following conditions:

AVdd=5 V


47

Vref=2.5 V

Gain=2

Code Range=0 to 1023

Resolution=10 bits

Least Significant Bit (LSB) voltage=5/(2^10)=4.88 mV

Temperature=room(25°C), hot(110°C) and cold(-45°C)

6.2.1 Offset Error

Offset error, often called 'zero-scale' error, indicates how well the actual transfer function

matches the ideal transfer function at a single point. For an ideal data converter, the first

transition occurs at 0.5LSB above zero. In an ideal A/D converter, an input voltage of

quanta / 2 will just barely cause an output code transition from zero to a count of one.

Any deviation from this is called Zero Scale Error, Zero Scale Offset Error, or Offset

Error. This error is positive or negative when the first transition point is higher or lower

than ideal, respectively. Offset error is a constant and can easily be factored or calibrated

out. Offset error may be expressed in percent of full scale voltage, Volts or in LSB. AMC

7891 ADC typically has offset error of ±1 LSB and offset error match of ±0.4 LSB.

Figure 6.2 ADC offset error


48

6.2.2 Integral Non-Linearity

INL describes the bow in the transfer function. INL is the maximum deviation of the

transfer function from a straight line between two points along the input-output transfer

curve. The maximum INL of ADC under all possible conditions is ±1 LSB, but typically

its around ±0.5 LSB.

INL = | [(VD - VZERO)/VLSB-IDEAL] - D | , where 0 < D < 2N-1.

Figure 6.3 ADC integral non-linearity

6.2.3 Differential Non-Linearity

DNL is the difference between the ideal and the actual input code width. The input code

width is the range of input values that produces the same digital output code. For an

ADC, the analog-input levels that trigger any two successive output codes should differ

by one LSB (DNL

= 0). Any deviation from one LSB is defined as DNL. For positive DNL we look at the

widest input code range. For negative DNL we look at the narrowest code range.

Typically the DNL is measured around ±0.5 LSB, but will not exceed a maximum of ±1

LSB under all possible working conditions.

DNL = |[(VD+1- VD)/VLSB-IDEAL - 1] | , where 0 < D < 2N

- 2.


49

Figure 6.4 ADC differential non-linearity

6.2.4 Gain Error

Gain Error, or Full-Scale Gain Error, is a deviation from the ideal slope of the transfer

function. It is the same as full-scale error with the offset error subtracted. If we shift the

actual transfer curve so that zero scale offset error becomes zero, the difference between

the actual and ideal transitions to full scale is the Gain Error. Typically gain error for this

ADC is around ±0.5 LSB and gain error match between the channels is typically ±0.4

LSB. Gain matching indicates how well the gains of all channels in a multichannel ADC

are matched to each other. To calculate gain matching, apply the same input signal to all

channels, and report the maximum deviation in gain (8).

Figure 6.5 ADC gain error


50

6.3 General Purpose Input/Output

GPIO is a generic pin on a chip whose behavior (including whether it is an input or

output pin) can be controlled (programmed) through software. GPIO pins have no special

purposes on themselves, and go unused by default. The idea is that sometimes the system

integrator building a full system that uses the chip might find useful to have a handful of

additional digital control lines, and having these available from the chip can save the

hassle of having to arrange additional circuitry to provide them. GPIO lines can thus

provide additional control and monitoring when the microcontroller or chipset has

insufficient I/O ports, or in systems where serial communication and control from a

remote location is advantageous.

GPIO capabilities include:

direction: GPIO pins can be configured to be input or output

enable mask (aka GPIO mask): GPIO pins can be enabled/disabled

input values are readable (typically high=1, low=0)

output values are writable/readable

GPIO peripherals vary quite widely. In some cases, they are very simple, a group of pins

that can be switched as a group to either input or output. In others, each pin can be set up

flexibly to accept or source different logic voltages, with configurable drive strengths and

pull up/downs. The input and output voltages are typically limited to the supply voltage

of the device with the GPIOs on, and may be damaged by greater voltages.

AMC 7891 has 12 GPIOs powered by DVdd supply of the chip. Vih,Vil and Voh, Vol

are the characteristics mentioned in the specification sheet for these digital GPIO lines.

They are defined as follows:

Vih : The minimum voltage applied to the input which will be accepted by the device as

logic high.


51

Vil : The maximum voltage applied to the input which will be accepted by the device as

logic low.

Voh : The minimum voltage level for logic high, at the output of the gate, under load.

Vol : The maximum voltage level for logic low, at the output of the gate, under load.

6.4 GPIO Results

Table 6.1 shows the measurements that are recorded after testing various chips:

Table 6.1 GPIO results

DVdd (volts) Min (v) Max

(v)

Vih

1.8 0.7*DVdd

3.3 2.1

5.5 2.1

Vil

1.8 0.3

3.3 0.8

5.5 0.8

Voh

1.8, Sourcing 1.6mA DVdd-0.2



Vol

1.8, Sinking 1.6mA 0.4




52

Chapter VII

Conclusion and Future Work

7.1 Conclusion

The test solution described combines both hardware and software to test SOCs like

Analog Monitoring and Control family of chips, showing the design process flow with all

the steps followed. By using a modular approach, the solution becomes generic, such that

it can be employed in testing many generations of AMCs with very few changes in the

software, and a series of daughter boards with no changes in the mother board, hence

saving time and revenue. The test solution developed produces results as expected and as

well provides an expandable platform to accommodate future testing of AMCs. Multiple

testing and statistical analysis confirms the repeatability and accuracy of the test solution,

leading to the characterization of the device and determination of the datasheet limits for

the new device. The aim of capturing markets is partially fulfilled by shipping the

samples to the respective customers within the specified deadlines. Full characterization

of the parts continues, bench to ATE correlation and qualification test are performed

before releasing the product to the markets.

7.2 Future Work

The skeletal framework for testing any type of AMC has now been developed, and

implementing this system for other devices is as easy as developing new daughter boards

with change only in the socket footprints and mapping to the motherboard. Since the

motherboard has all the test circuitry required, daughterboard can be fitted on it and the

design will then be complete. The software can be made compatible with the new

products with minimal changes to it. As far as the software is concerned, there is hardly

any limitation to the functionality that could be tested using this setup. The only limiting

factor could be the resources available on the hardware front: the motherboard.

Nevertheless there is still some room for future products with some excess resources


53

already available anticipating future growth. The setup can be used not only for future

AMCs but for other types of ICs as well, like independent DACs and ADCs for example.


54

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