multivariable dynamic model and robust control of a ... · control model which in turn adds to the...

Multivariable Dynamic Model and Robust Control of a Voltage-Source Converter for Power System Applications

Ahmadreza Tabesh and Reza Iravani

Affine Controller Parameterization for Decentralized Control Over Banach Spaces

Michael Rotkowitz and Sanjay Lall

Student: Yi HanSupervisor: Peter YoungCommittee: Edwin Chong

Ali PezeshkiCharles Anderson

1

Paper 1: Multivariable Dynamic Model & Robust Control of a Voltage-Source Converter for Power System Applications

Introduction and motivationVSC dynamic model

VSC State Space model in qd reference frameVSC instantaneous reactive powerDevelopment of a multivariable dynamic model for VSC

Multivariable Controller Design for VSCReal and reactive power controllerDC side voltage controller designDynamic power limiter

Application ExampleConclusion

Ahmadreza Tabesh and Reza Iravani

2

Paper 1: Intro and motivationMotivation

The conventional VSC (voltage source converter) model using qdcurrent components as dynamic variables, resulting a nonlinear VSC-control model which in turn adds to the complexity of the control designAmong linear control methods, state feedback based methods do not necessarily provide robust controller since control provisions are not readily formulated in these methodsAmong nonlinear control methods, feedback linearization method is not robust since its requires precise cancellation of VSC model nonlinearization

Proposed solutionA linear model using instantaneous real and reactive power components p(t) and q(t) as dynamic variablesRobust controller design procedures can deployed since the model dynamic variables are independent of the reference frame 3

Paper 1: Intro and motivationApplications: electrical power generation, transmission and distributionWidely used as building block of: [1]

Shunt connected controllerstatic synchronous compensator (STATCOM); Unified power flow controller (UPFC);

Series connected controllerStatic Synchronous series compensator (SSSC); Interline power flow controller (IPFC)

Advantages:self-communicatingControllabilityCompact modular designEasy of system interfaceLow environment compactDecoupled instantaneous real and reactive power components

DisadvantagesMore expensive than the thyristorHigher losses than the thyristor

4

Paper 1: Intro and motivation (conti)A change of variables that formulates a transformation of the 3-phase variables of stationary circuit elements to the arbitrary reference frame may be expressed as [2]: where: ;

abcsqd fKf =0

][)( 00 sdsqsT

sqd ffff =][)( csbsas

Tabcs ffff =

( ) ( )( ) ( )

+−+−

=

21

21

21

sinsinsincoscoscos

32

32

32

32

32

πθπθθπθπθθ

sK

dtdθω =

( ) ( )( ) ( )

++−−=−

1sincos1sincos1sincos

32

32

32

32

321

πθπθπθπθ

θθ

sK

It can be shown that for the inverse transformation we have:

The angular velocity ω and the angular displacement θ of the arbitrary

reference frame are related by: . Thus, or in definite

integral form: ∫ dtωθ＝

( ) ( )0＝0

θξξωθ +∫ dt

e

where ξ is a dummy variable of integration. ωe is the power system frequency.5

Paper 1: Outline

Introduction and BackgroundVSC dynamic model




6

Paper 1: VSC dynamic model

−−−−−

=)cos()cos(

)cos(

2)(

3432

πδωπδω

δω

tt

ttmVv dc

tabc

where[ ]Ttttt cbaabc

vvvv =

m is the converter modulation index;δ is the phase angle or the VSC terminal voltage with respect to the point of common coupling voltage[2]

abcabc

abc

abc ttt

s vRidt

diLv ++=A dynamic model of the VSC in the abc reference frame is:

Fig. VSC power system schematic diagram

where: [ ]Tssss cbaabcvvvv = [ ]Tssss cbaabc

iiii =

R and L are the equivalent series resistance and inductance of the filter and transformer, between the VSC terminal and the PCC.

)()()()( tPtptItV Ldcdc −=The dc side voltage dynamic expression is deduced as:where: p(t) is the instantaneous real power at PCC; PL(t) is the total power loss.

VSC SS in qd0

Fig. 1

7

Paper 1: VSC dynamic modelThe instantaneous real power at PCC is:

abcabcccbbaa tTstststs ivivivivtp =++=)(

In qd reference frame, the p(t) in terms of voltage and current can be obtained by substi:

0

1

qdabc sss vKv −= and in (4)0

1

qdabc tst iKi −=

( ) ( )0000 2

3)( 11

tststsssT

sTs iviviviKKvtp

ddqqqdqd++== −−

Since: then:0=++cba ttt iii ( )

ddqq tsts ivivtp +=2

3)(

Transfer the system dynamic to the qd reference frame, then

( )qqdq

qtstet

t vvL

iiLR

dtdi

L −+−−=1ω ( )

dddd

dtstet

t vvL

iiLR

dtdi

L −++−=1ω

( ) ( ) ( )

−+= tPiviv

tCVdtdV

Ltstsdc

dcddqq2

31

These three equations describe nonlinear and coupled dynamic model of the VSC

Instantaneous reactive power dynamic developmentThe instantaneous voltage and current space vectors are defined as:

( ) ( ) ( )tjsdsq etvj vvv θ＝

2

3+= ( ) ( ) ( ) ( )( )ttj

sdsq etij iii φθ −+= ＝2

3

where ( ) ( )22

2

3dq ss vvtv += ( ) ( )22

2

3dq ss iiti +=

(7) (8)

(9)

(4)

VSC instantaneous power Fig. 2a

8


( ) ( ) ( )ttitip φcos= ( ) ( ) ( )ttiti q φsin=

The instantaneous active current and instantaneous reactive current are defined as:

Then, the instantaneous active power and reactive are defined as:

( ) ( ) ( ) ( )ttitvtp φcos= ( ) ( ) ( ) ( )ttitvtq φsin=Instantaneous active and reactive power are expressed as:( ) ( ) ( ) ( ) ( ) ( ) ( )[ ]

qddqddqq tstststs ivivjivivtj qtptitvts ++++==2

3＝

*

( ) ( ) ( )ddqq tsts ivivtstp +==

2

3Re ( ) ( ) ( )

qddq tsts ivivtstq +==2

3Im

Since power waveform is independent from a frame of reference, p(t) and q(t) can be calculated based on voltage and current components in a stationary reference frame:

( )cbaq ssss vvvv +−=

3

1

3

2

( )cbaq tttt iiii +−=

3

1

3

2

( )cbd sss vvv −=

3

1

( )cbd ttt iii －

3

1=

By substituting ( ) ( ) ( ) ( )( )bacacbcba ttsttstts iiviiviivtq −+−+−=

3

1

Till now p(t) and q(t) are obtained by meaning of they are represented by ,abcsv

abcti9


Deploy the p(t) and q(t) as the dynamic variables: (From Eq. 17,18)( ) ( ) ( )tqKtpKti dqt q

−= ( ) ( ) ( )tqKtpKti qdt d−=

where223

2＝

dq

q

ss

sq vv

vK

+ 223

2＝

dq

d

ss

sd vv

vK

+Kq and Kd are only functions of the PCC voltage components.

(21) (22)

Substitute equations (21) and (22) into (7) and (8), then

)()()()( tutqtp

LR

dttdp

qe +−−= ω )()()()( tutptq

LR

dttdq

pe +−−= ω

where ( ) ( )( )ddqqdq tstsssq vvvvvv

Ltu −++ 22

2

3＝)( ( )( )

dqqd tstsp vvvvL

tu −2

3＝)(

Using p(t) and q(t) as state variables, then

qe uqpLRs =+

+ ω pe upq

LRs =+

+ ω

Solving p and q, in Laplace domain we get:

=

p

q

uu

gggg

qp

2221

1211 where( )

( ) 222211

easasgg

ω++

+==

( ) 222112

e

e

asgg

ω

ω

++=−=

LRa /=

( )( ) 22

easas

ω++

+

( )( ) 22

easas

ω++

+

( )( ) 22

easas

ω++

+

( )( ) 22

easas

ω++

+pu

qu p

q

+

+

-

+

(26)

(29)

(30)(31)

(27) (28)

(24) (25)

VSC instantaneous power

Fig. 3

10

Paper 1: Outline





11

Paper 1: Multivariable controller designReal and reactive power controller

The sequential loop closing (SLC) method is used to design the controllers for the multivariable model. The SLC is a generalization of the classical controller design approach for multivariable systems. This design method ensures that the overall system remain stable provided that the system retains stability at each step of controller design. The SLC employs well established controller design techniques, such as: bode plot and root locus, to design the robust controller.

Real power controller designSet uq=0 that is let up and p be the first pair input output variables, the SISO system is:

pugtp 12)( = where ( )pPGu r efcp p−=

The controller is designed such that the first SISO loop is a stable loop with the required specifications. The closed loop equation of the first loop in Laplace domain is:

r efc

c PGg

Ggp

p

p

12

12

1＝

+

For a stable loop, the controller is designed to have all roots of located in the left half plane (LHP).

0＝1 12 pcGg+

(33)

12

Paper 1: Multivariable controller designReactive power controller design

The second loop controller is for the uq and q SISO input, output variables. The first loop now is considered as part of the system. Since that:

pq ugugp 1211 += pq ugugq 2221 +=Substituting equation (33) into (36) , then:

(35) (36)( )pPGgugq r efcq p

−+= 2221

Replacing p from (35) into (37), then r efPqQ PGuGq +=

where

+−=

12

1122

211 gG

GgggG

p

p

c

cQ

p

p

c

cP Gg

GgG

12

22

1 +=

Control input uq is: ( )qQGu r efcq p−=

where is the second loop compensator corresponding to (uq,q). Substituting uq from (39) into (38) then:

qcG(39)

( ) r efcQ

Pr ef

cQ

cQ PGGg

GgQGG

GGq

qq

q

++

+=

11 12

22

Similarly, is designed to have all roots of located in LHP. The controller is also designed based on the SISO design techniques.

qcGqcQGG+1

13

Paper 1: Multivariable controller designDC side controller design

( ) ( ) ( )

−+= tPiviv

tCVdt

dVLtsts

dc

dcddqq2

31The VSC dc side dynamic equations is given as:The instantaneous dc side voltage Vdc can be considered as an average value Vdc0 and a ripple term ∆Vdc, Vdc=Vdc0+ ∆Vdc. Considering that ( )

ddqq tsts ivivtp +=2

3)(

by substituting Vdc≈Vdc0 in (9) then:

( ) ( ) ( )( )tPtptCVdt

dVL

dc

dc −=0

1 in Laplace domain ( ) ( )Ldc

dc PptsCV

V −=0

1

r efQr efP QGPGp ˆˆ +=

where

( )( )

++−=

1212

2211

111ˆ

gGGGgGgg

GGpq

q

cQc

cPP

( )( )pq

q

ccQ

cQ GgGG

GgG

12

11

11＝ˆ

++

(43)

Substituting p from (43) in (42)dr efdcdc VPGV += where

0

ˆ

dc

Pdc sCV

GG =

Vd represents a disturbance term and is given by: Lr efdcd PQGV −=

( )dcdccr ef VVGP −= 0

From the Fig. 4(a), the controller is designed to maintain Vdc at Vdc0. By substituting , the closed loop TF of the outer control loop is: ( )L

dccdc Pp

GGV −

+=

1

1

The controller is designed to have all roots of are in LHP.01 =+ dccGG

(41) & (42)

Fig. 4a

14

Paper 1: Multivariable controller designDynamic Power Limiter

VSC ac side subsystem can subject the VSC to overcurrent under the control schemeA current limit strategy is required to protect the VSC switches against overcurrentThe VSC instantaneous current and voltage are monitored at PCCDesired limits are imposed by two coefficients: for real/reactive rsp1≤Pα 1≤QαandThe calculation block calculate real and reactive current components of the VSC are given by:

( ) ( )( )tvtPti P = ( ) ( )

( )tvtQti Q =

abcabcccbbaa tTstststs ivivivivtp =++=)(

( ) ( ) ( ) ( )( )bacacbcba ttsttstts iiviiviivtq −+−+−=

3

1

( ) ( )22

2

3dq ss vvtv +=

Qi ( )tv( )ti

Pi q

p

φPer unit values of iP and iQ are utilized to generate coefficients

Pα Qαand as defined by: ( )

=

−− 1PiesatP τα ( )

=

−− 1QiesatQ τα

where

where τ is a parameter that assigns the slops of the limiter function and sat is defined as: ( )

>

≤=

1,1

1,

ααα

αsat

References are continuously multiplied by two coefficients to dynamically deduce the limits

Fig. 4b

15

Paper 1: Outline





16

Paper 1: Application exampleVSC controllers are designed based on multivariable model

( )( ) 222211

easasgg

ω++

+==

( ) 222112

e

e

asgg

ω

ω

++=−=

Tracking, disturbance rejection & robustness of the designed controller are examined based on time domain simulation of the exact switching model of the systemSystem studyRs, Ls – source internal per phase parametersRL, LL – load per phase parametersR, L – filter and transformer parameters btw VSC and PCCRp, Sp – in series is used to examine the performance of the real power controller of VSCAll results are studied in per unit based on

, and

Resistance Inductance

Rs=25mΩ Ls=0.145mH

RL=4.16Ω LL=4.093mH

R=150mΩ L=0.637mH

Rp=10.58Ω C=4820µF

Es=115V Vdc=230V

kVApb 10= VVbac 115= VV

bdc 230=

57.19757295761.470

47881.23522211 ++

+==

sssgg

57.19757295761.470

99112.37622112 ++

−=−=

ssgg

sGC

05.0

110 +=

sG

qC 5105.1

1200

−×+=

×

++−=− s

sGpC 4104

11005.0

VSC model and controller

Fig. 5

17

Paper 1: Application exampleTracking capability

Tracking capability of the designed controllers is examined by applying a step function to Qref

to the closed-loop system.

Fig shows the VSC reactive power and the dc-side voltage responses to the step in Qref.

Tracking time less than 10% Settling time less than 3 cycles

Max of 0.05p.u voltage drop in the dc-side voltage is recovered in less than 3 cycles

Steady state errors in both reactive power and dc side voltage are 0

The obtained results do agree with the corresponding responses obtained based on conventional control

Fig. 618

Paper 1: Application exampleThe rms and instantaneous (phase a) PCC voltage and VSC (phase a) current in response to the step change in Qref are shownVoltage and current rms values are calculated from the instantaneous qd components as:

( )225.0dqrms sss vvv +=

( )225.0dqr ms ttt iii +=

( )cbaq ssss vvvv +−=

3

1

3

2

( )cbaq tttt iiii +−=

3

1

3

2

( )cbd sss vvv −=

3

1

( )cbd ttt iii －

3

1=

where

In steady state (five cycles after the disturbance), (53) and (54) provide the same rms values as deduced based on the conventional definition of root mean square over 1 signal period Fig. 7a shows vsrms almost remain unchanged Fig. 7b shows the rms current increases to about 1 p.u. without any significan overshoot Fig.6 and 7 validate the model assumptions and the inner control loop design based on:

(53)

(54)

r efc

c PGg

Ggp

p

p

12

12

1＝

+ ( ) r efcQ

Pr ef

cQ

cQ PGGg

GgQGG

GGq

qq

q

++

+=

11 12

22 ( )Ldcc

dc PpGG

V −+

=1

1

Fig. 7

19

Paper 1: Application exampleDisturbance rejection capability1) DC side load energizationThe ability of the control system to reject a dc side disturbance is verified by connecting Rp in parallel to the dc capacitorRp dissipates 5kW which is half of the VSC rated power

Fig.8 shows variations of the dc side voltage and the corresponding reactive power flow, subsequent to the dc side disturbance

Fig.8a shows that the VSC control system reverts the capacitor voltage to its reference value in less than 3cycles and maintain the dc side voltage within 7% of the rated value

Fig.8b shows that q(t) deviates 0.1p.u. and the reactive power controller regulates q(t) to its reference value in less than 3 cycles

Fig.8 confirm viability of the design of the out loop controller based on the linear model in (41)

This setup represent variations in power exchange due to a disturbance in a back-to-back VSC configuration Fig. 8

20

Paper 1: Application example2) AC side load change:

VSC controllers’ performance is investigated in response to a disturbance due to a load change, load is divided into 2 equal sections

Initially, switch SL is closed and the load is changed by opening the switch

Fig.10 depicts the effect of the load change on reactive power at PCC and the dc side voltage

Fig.10a shows 0.03 p.u. deviation in reactive power which reverts to its steady state value in three cycles

Fig.10b shows that Vdc(t) deviates 0.007 p.u. that is regulated to its steady state value via the control system in 3 cycle

Fig.10 shows the ability of the designed controllers to reject an ac side distrubance

Fig. 10

Fig. 9

21

Paper 1: Application exampleDynamic power limiter capability

( )

=

−− 1PiesatP τα ( )

=

−− 1QiesatQ τα

The proposed current limiter capability is studied

To have a steep slop of limiter function, τ=5 Two temporary three-cycle faults; a three-phase

and a single phase are studied PCC faults are imposed at t=0 and removed at t=3 The per phase fault impedance for the three and

single phase faults are 0.1Ω and 0.04Ω which result in fault currents of up to 10 p.u.

1) Three phase fault: Solid lines in Fig.11 depict the system behavior when the limiter is in service Fig.11a shows when the limiter is in service, the peak value of the fault current in the

first cycle is about 2.5 p.u. and the peak value of the dc side voltage is less than 1.15 p.u. Fig.11a shows when the fault is cleared, the rms current is limited to 1.5 p.u. Fig.11b shows when the fault is cleared, the dc side voltage remains less than 1.1 p.u. After fault is cleared, the current and dc side voltage return to their steady state in less

than 3 cycles

Prior to each fault, the rms current and the dc side voltage are at 1 p.u.Fig. 11

22

Paper 1: Application example Dashed line show the system response to the same fault when the limiter is not in service Fig.11a,11b show the VSC current and dc side voltage subsequent to the fault increase to

3.5 p.u. and 1.2 p.u., respectivily When the limiter is not in service, VSC current and dc side voltage experience higher peak

values since the controller still employs prefault values of Pref and Qref during the fault Fig.11 shows the effectiveness of the dynamic current limiter in reducing the VSC current

and the dc side voltage deviations following the three phase fault2) Single phase fault: Fig.12 shows system response to the SP fault Fig.12 indicates that the peak encountered

values are less than those of the three phase fault for the same fault rms current

Fig.12a shows the VSC current is limited to 2.5 p.u. without the limiter and 1.5 p.u. when the limiter is in service

The dc side max overvoltage in Fig.12b is about 0.15 p.u. without the limiter and 0.1 p.u. when the limiter is employed

Fig.12 reveals that after the fault clearancethe VSC current and dc side voltage return to steady state conditions in less than 2 cycles

Fig. 1223

Paper 1: Application exampleController Robustness1) Robustness of controllers to system parameters: From (26) and (29), series ind L mainly influences

the reactive power controller Eq (41) conveys that the dc side capacitance C

dominantly impacts the dc side voltage regulator C and L are varied to investigate the robustness of

the system Fig.13a shows the response of the system to a Qref

step from 0 to 1 p.u. , crspding to 0.9L, L and 1.1L

For these 3 ind values, overshoot is less than 10%; the rise time is less than one cycle; settling time is less than three cycles

Fig.13a verifies the robustness of the control system to variations in L Fig.13b shows the robustness of the controller to variation of C Fig.13b shows for all three values of C, voltage deviations are less than 0.1 p.u. and the

dc side voltage revert to the steady state value within three cycles

Fig. 13

24

Paper 1: Application exampleController Robustness2) Robustness of controller to PLL dynamics: A bias angle θb=45° is applied to the PLL Fig.15a shows reactive power component time

response to a step change in reactive power command corresponding to θb=0° and θb=45°

Fig.15a indicates that time response properties for both waveforms are practically the same

Fig.15b shows the dc voltage time response properties are identical

Fig.15 shows the robustness of the proposed controller to the PLL dynamics

3) Robustness of controller to change of operating point and short circuit ration (SCR): Fig.16a shows that for SCR=15,10,and 5, the VSC tracks

0.5 p.u. step change command in reactive power with a zero steady state error

Fig.16b shows that for SCR=15,10,and 5, the dc side voltage reverts to its steady state value with a zero steady state error in 3 cycles

Fig.16 shows the VSC controllers provide robustness wrt a wide range of SCR values

Fig. 15

Fig. 1625

Paper 1: Application exampleController Robustness Fig.17a shows the system responses to a 1 p.u.

reactive power step command for three Vdcvoltage levels

Fig.17b shows the voltage waveforms of dc link cap following the dc side load ergization

Fig.17a,b demonstrates that the control system is able to track a reactive power command and to revert a disturbed dc side voltage to its norminal value at different operating points Fig. 17

26

Paper 1: Outline





27

Paper 1: Conclusion A new multivariable model and controller design approach for a VSC are presented Instantaneous real and reactive power components are used as dynamic variables VSC control system consists of an inner feedback loop to control real and reactive power;

an outer loop to control dc side voltage via real power control A mechanism to dynamically limit overcurrent subsequent to a fault The inner control loop is designed based on sequential loop closing method The outer control loop is designed based on an SISO control method The current limiting scheme reduces power exchange between the VSC and power system

during fault conditions The salient feature

o The model dynamic variables are independent from the frame of referenceo Well established robust multivariable control techniques can be adopted based on the proposed

model A study system is used to demonstrate, the results indicate that

o VSC controllers designed based on the multivariable model to fulfill the desired tracking and disturbance rejection specifications

o The control system is robust to the system parameter variations and frame of referenceo The proposed protection scheme successfully limits switch overcurrent during and subsequent

to fault Accuracy of the developed model and effectiveness of the proposed controller are

validated based on time domain simulation studies of test system in software enviromnet28

Paper 2: Affine Controller Parameterization for Decentralized Control Over Banach Spaces

Michael Rotkowitz and Sanjay Lall

Introduction and motivationPreliminariesBounded linear operatorsProblems formulationChange of variables

Quadratic invarianceInvariance under feedback

EquivalentViolation

Conclusion29

Paper 2: Intro and motivationMotivation

To solve a canonical problem in decentralized control is to minimize a norm of the closed-loop map subject to a subspace constraint as:

But for a general linear operator P and subspace S, there is no known tractable algorithm for computing the optimal K

Proposed solutionIf the controller’s constraint satisfy a condition called quadratic invariance, with respect to(wrt) the system being controlledThe optimal decentralized control problem may be reduced to a convex optimization problem

Decentralized controlInstead of a single controller connected to a physical systems, one has separate controllers, each with access to different information and with authority over different decision or actuation variables

( )SK

KPf

∈ to subject

,min

30

Paper 2: Intro and motivation

=

2221

1211

PP

PPP

31

Paper 2: Intro and motivationBounded linear operators

Suppose that U, W, Y, Z are all Banach spaces, P is a bounded linear operatorFor S⊆X and T⊆X* (X* is the dual space to X) define:

Given G∈ℒ(U,Y), define M⊆ℒ(Y,U) of controllers K such that f(P, K) is well defined by:

For any Banach space X and bounded linear operator A∈ℒ(X), the resolvent set is:

And the resolvent by for all λ∈ .

Define to be the unbounded connected component of

Note 1∈ for all K∈M, and define the subset N⊆M by:

SxxxXxS ∈>=<∈=⊥ all for ,0,| **

TxxxXxT ∈>=<∈=⊥ ** all for ,0,|

( ) invertible is |),( GKIUYLKM −∈=

( ) ( ) invertible is |C AIA −∈= λλρ

( ) ( )XLARA →ρ: ( ) ( ) 1−−= AIRA λλ ( )Aρ

( )Aucρ ( )Aρ

( )GKρ

( ) ( ) GKUYLKN ucρ∈∈= 1|,

32

Paper 2: Intro and motivationProblem formulation

Given Banach spaces U, W, Y, Z, generalized plant P∈ℒ(W×U, Z×Y), and a subspace of admissible controller S⊆ℒ(Y, U), solve problem:

(1)

S is chosen to represent the desired decentralization of the controller, S is called the information constraint

The problem is very general: Signal space U, W, Y, Z may be continuous or discrete Signal and system may evolve over infinite time, over finite time interval The norm may represent a deterministic measure or stochastic measure

of performance The plant and system are assumed to be linear, continuous, causal and LTI The problem is made more difficult by the constraint K in the subspace S is non-convex function of K, no computationally tractable

approach is known for solving this problem for arbitrary P and S

( )

SK

MK

KPf

∈∈

to subject

,min

( )KPf ,

33



EquivalentViolation

Conclusion

Paper 2: Outline

34

Paper 2: Intro and motivation

( ) ( ) 1,

−−−= GKIKKGh

GKI −( ) ( )KGhKhG ,=

( ) SQhMQ

QPPP

G ∈∈

−

to subject

min 211211

35

Paper 2: Quadratic invariance

36



EquivalentViolation

Conclusion

Paper 2: Outline

37

Paper 2: Invariance under feedback

38


39


40


SQ

MQ

QPPP

∈∈

−

to subject

min 211211

SQ

QPPP

∈

−

to subject

min 211211

41


42



EquivalentViolation

Conclusion

Paper 2: Outline

43

Paper 2: ConclusionQuadratic invariance is necessary and sufficient condition for the affine constraints on the controller to be preserved under the feedback map

44

Thanks!

questions?

45

multivariable dynamic model and robust control of a ... · control model which in turn adds to the...

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