NA62 straw tracker readout status

Georgios Konstantinou23.05.2012

NA62 straw tracker data flow –Electronics overview

Front end boards Straw readout board TEL62

TEL62 mezzaninne board--Under Construction

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Front End and SRB

• Front End (cover):– Carioca chips– In-FPGA TDC with 0.74 ns resolution– FIFOs, serial link

• Straw Readout Board– Back-end FPGA

• Data formation• FIFOs

– VME bus manager• VME communication• Memory interface

Front end boards SRB

Front End (Cover)

• Noise scan • TDC scan

Though most of the functionality seems ok, certain phenomena such as oscillations have been noticed and are under further research. A final version of the hardware is needed.

Cover to SRB• Several Problems occurred, related to firmware bugs.• Current (final?) version:

– Total link speed: 1.2 Gbps (0.8 FEBE, 0.4 BEFE)– 15m Ethernet Cables CAT6– 8b/10b protocol– Chain of reset propagation from VME to FE– Reset loop over the Ethernet cable– Reset concerning: not receiving data, receiving erratic data– Communication clock phase scan, front-end phase monitoring– Non blocking arbitration between covers

Front end boards SRB

SRB to TEL62

• Mezzanine card:– Reading out from the SRB (Ethernet)– Reorganization of the data received by timestamp– TEL62 firmware interface– Upstream communication– Communication not possible with currentversion

TEL62TEL62 mezzaninne board--Under Construction

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SRB

SRB to TEL62

• Mezzanine card:– Decision on dimensions and data manipulation– Decision on functionality– Decision on logic unit– Decision on chipset

Straw readout board TEL62

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SRB to TEL62

• Mezzanine card:– Size:

• Standard TEL62 daughter card (TDCB) size against one big per TEL62.• 4 mezzanine cards per TEL62.• 3 SRBs per mezzanine card.• Data received not organized by source, but by timestamp.

Straw readout board TEL62

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SRB to TEL62

• Mezzanine card:– Functionality:

• Data received will be organized according to coarse timestamp• Data to be manipulated as similarly as in TDCB.• Effort to conform with TEL62 TDCB layout, for maximum possible data

compatibility.

Straw readout board TEL62

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SRB to TEL62

• Mezzanine card:– Logic unit:

• FPGA, most likely the same like TDCB (ALTERA Cyclone III family)• Logic and pin out to TEL62 exactly the same like TDCB for conformity.• VHDL code to be built.

Straw readout board TEL62

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SRB to TEL62

• Mezzanine card:– Chipset:

• Different possibilities investigated• Evaluation boards search• Total bandwidth calculated is ~1 Gbps per SRB on average, more than 2

Gbps to be safe.

Straw readout board TEL62

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Dry Run-Technical Run Plans

• July-August– We will participate as observers, to get used to the TEL62 functionality, learn

and avoid possible problems.

• Mezzanine board test– When the mezzanine board is ready, we will proceed with checking the

functionality by sending in data (perhaps from Monte Carlo simulation?) in a special test.

• Technical Run– Focus on front end issues and final version production.– Given the timescale, design and debugging of new SRB with TEL62 connection

too optimistic. Without the new SRB, the mezzanine can’t be used.• Scenario A (optimistic): Run with new FE, new SRB, new SBC, TEL62.• Scenario B (realistic): Run with current SRB, new SBC and VME readout.

The End

Thank you,Questions?