188 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 2, FEBRUARY 2015

Experimental Investigation of Program Voltage(20 V) Generation With Boost Converter

for 3-D-Stacked NAND Flash SSDTeruyoshi Hatanaka, Koh Johguchi, Member, IEEE, and Ken Takeuchi, Member, IEEE

Abstract This paper experimentally demonstrates programvoltage (20 V) generation under emulated condition of a 3-Dsolid-state drive (3-D-SSD) which vertically integrates boostconverter on an flame retardant type 4-interposer and Si-chips.The proposed program voltage generator is a boost converterusing a coil on the interposer. A measured peak magnetic fieldpower is approximately 49 dBm above the coil, which satisfiesthe international regulation. The magnetic field induces the eddycurrent in a conductor material. The eddy current degradesthe boost converter performance due to the lowered effectiveinductance of the coil. The effects on the performance of theboost converter as a function of the distance from the coil to theconductor are experimentally investigated. A 3-D-SSD requires a>0.84-mm space between the coil and conductor to generate theprogram voltage. By inserting NAND flash memory chips betweenthe coil and the conductor, a 3-D-SSD can be successfully realizedwithout the output voltage degradation.

Index Terms Boost converter, electromagnetic interfer-ence (EMI), magnetic field, NAND flash memory, solid-statedrive (SSD).

I. INTRODUCTION

RECENTLY, a solid-state drive (SSD) has been widelyused for various applications. A NAND flash memory-based SSD has a speed advantage over a hard-disc drive.To increase the capacity of an SSD, multiple NAND flashmemory chips are stacked into a package. However, one of theSSD design issues is increasing power consumption. There-fore, the low-power 3-D-integrated SSD (3-D-SSD) methodsare proposed [1][3]. Fig. 1 shows the concept of the proposed3-D-SSD [1]. NAND flash memory chips, dynamic RAMs(DRAMs), NAND controller, and boost converter are integratedas a system in a package. The typical die sizes of NAND

Manuscript received December 3, 2013; revised May 28, 2014 andSeptember 7, 2014; accepted November 24, 2014. Date of publicationJanuary 18, 2015; date of current version February 3, 2015. This work wassupported in part by the Japan Science and Technology Agency/Core Researchfor Evolutionary Science and Technology, in part by the VLSI Design andEducation Center, and in part by the University of Tokyo in collaboration withSynopsys, Inc., Mountain View, CA, USA. Recommended for publication byAssociate Editor E.-P. Li upon evaluation of reviewers comments.

T. Hatanaka is with the Department of Electrical, Electronic and Commu-nication Engineering, Chuo University, Tokyo 192-0393, Japan, and also withthe Department of Electrical Engineering and Information Systems, Universityof Tokyo, Tokyo 113-8654, Japan (e-mail: hatanaka@lsi.t.u-tokyo.ac.jp).

K. Johguchi and K. Takeuchi are with the Department of Electrical,Electronic and Communication Engineering, Chuo University, Tokyo192-0393, Japan (e-mail: johguchi@ieee.org; johguchi@takeuchi-lab.org).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2014.2381267

Fig. 1. Concept of the 3-D-SSD.

flash memories and DRAMs are 100175 mm2 [4], [5] and50100 mm2 [6], [7], respectively. The NAND controller chipand boost converter are mounted on an interposer. In thispaper, a double-side flame retardant type 4 (FR-4)-basedorganic interposer is used. The boost converter is used insteadof a charge pump as a generator for program voltage, VPGM.In the conventional SSD, each NAND flash memory chip has acharge pump. Thus, large Si-area is consumed in each NANDflash memories. Therefore, to reduce the Si-area, a single boostconverter is shared for multiple NAND flash memory chips. Theboost converter consists of a coil, HV-MOS transistors, and theboost converter controller, as shown in Fig. 1. All componentsfor the proposed boost converter are located on the FR-4-basedorganic interposer. A NAND controller, NAND flash memories,and DRAMs are connected with through-silicon-vias (TSVs).

The previous 3-D-SSD works focus on the control techniquefor the rising time and power reductions. To realize themultiple NAND flash memory chip interleave operation, theVPGM generator with a load detector is proposed in [2].The boost converter for the wide output voltage range from10 V (VPASS) to 20 V (VPGM) is described in [3]. In [8] and [9],the 3-D-integration techniques with a TSV technology are dis-cussed and the parasitic effects of a TSV are also investigated.

This paper discusses the performance degradation ofthe boost converter due to the 3-D-integration. Thereare analyses of the on-chip coil for the radio frequencyapplications [10][16]. The inductance of an on-chip coil islimited below a few tens of nanohenry, because a larger induc-tance requires a larger area. However, a large coil also has

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HATANAKA et al.: EXPERIMENTAL INVESTIGATION OF PROGRAM VOLTAGE (20 V) GENERATION 189

Fig. 2. Measurement setup and chip photographs.

a large parasitic capacitance, which induces a lowself-resonance frequency. Electromagnetic interference (EMI)noise reduction techniques are also necessary for 3-D-stackingand dc-dc converters [17][21]. One of the critical issuesinvolved in 3-D-stacking is the eddy current in the conductorlocated near the coil [22]. Because of the eddy current,there is a possibility that the output voltage does not reach aprogram voltage of 20 V.

This paper is organized as follows. Section II shows themeasured magnetic field near the coil of the boost converter.The performance of the boost converter in the stacked situationis demonstrated in Section III. Finally, Section IV gives aguideline for a 3-D packaged SSD with stacked NAND flashmemory chips as a conclusion.

II. MAGNETIC FIELD GENERATED BY BOOST CONVERTERFig. 2 shows chip photographs and the measurement setup

to evaluate the magnetic field on the boost converter. The high-voltage MOS chip of the NAND flash process is fabricated andmounted on an FR-4-based interposer. The inductance of thecoil is calculated by the following [23]:

L 0n2dAVGc1

2

[ln

(c2

)+ c3 + c42

](1)

dAVG = dOUT + dIN2 (2)

dOUT dINdOUT + dIN (3)

c1 = 1.27, c2 = 2.07, c3 = 0.18, c4 = 0.13 (4)where L represents the inductance, 0 is the vacuum perme-ability, n is the number of turns, dOUT is the outer diameter,dIN is the inner diameter, and c1c4 are the constants. Thedesigned inductance, area and the number of turns are 270 nH,5 5 mm2, and seven-turn, respectively [1]. The generatedmagnetic fields are monitored by a magnetic field probe(CP-1S, made by NEC Engineering,Ltd.) and a spectrumanalyzer (N9020A, Agilent Technologies), as shown in Fig. 2.

Fig. 3(a) and (b) shows the schematic and the simulatedwaveforms of the boost converter, respectively. The load ofthe boost converter is the wordline of NAND the flash memoryand thus the capacitive load. The target output voltage, VOUT,is program voltage, VPGM (20 V). The coil radiates an elec-tromagnetic field during the boosting due to the current in

Fig. 3. (a) Schematic and (b) simulated waveforms of the boost converter.

the coil, IL . Fig. 4 shows the waveform of the magneticfield. The boost converter operates with the clock frequency,15 MHz, and the clock duty cycle, 88.9%, and outputs 18 Vin the simulation and magnetic field measurement. Fig. 4(b)shows the measured magnetic field power as a function of thex and z-positions. The x- and z-axes are defined, as shownin the inset of Fig. 4(b). The origin is defined as the cen-ter of the coil. The magnetic field depends on the x- andz-positions. The peak of the magnetic field is detected inthe middle between the inner and outer perimeters of thecoil (P). The magnetic field becomes sufficiently small outsidethe coil compared with the background noise, as shown inFig. 4(a). Moreover, in case of z = 3 mm, the magneticfield decreases to 75 dBm, which is the same level of thebackground noise. Fig. 5 shows the measured magnetic fieldpower as a function of clock frequency. The duty ratio of theinput clock is set to 60%, 70%, and 80%. The magnetic fieldpower gradually increases as the clock frequency becomeshigh because the average coil current increases. However, themeasured magnetic field does not show the duty ratio depen-dence. In the operation range of the boost converter [1][3],the peak magnetic field power is not changed. Fig. 6 plots thez-position dependency at x = P. The magnetic field powerdecreases linearly related to the z-position.

The EMI noise is regulated as radio disturbance charac-teristics by international commission such as InternationalElectrotechnical Commission (IEC) [24]. The detected peak

190 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 2, FEBRUARY 2015

Fig. 4. (a) Measured waveform of the magnetic field generated by thecoil of the boost converter. (b) Measured magnetic field as a function of thex- and z-positions.

Fig. 5. Measured magnetic field power as a function of the clock frequency.

magnetic field power is 49 dBm (=60 dBV), as shown inFig. 4(a). On the other hand, the regulation limit is 60 dBVat a distance of 10 m. Therefore, the measurement results aremuch lower than the regulation limit, because the measuredmagnetic field power decreases to 75 dBm at a distanceof 3 mm. Note that a NAND flash memory chip designguarantees the correct operation under the IEC regulation.

Fig. 6. Measured magnetic field power as a function of the z-position.

Fig. 7. (a) Schematic of the stacked structure of the coil and the conductor(Al film). (b) Measured waveform of the boost converter at d = 0.16 mm.

As a result, the proposed voltage generator does not affectother electric devices.

III. MEASUREMENT RESULTS OF BOOST CONVERTERSTACKED WITH Si-CHIP AND CONDUCTOR

A. Stacked With ConductorFrom the experimental results in Section II, if the conductor

is put in the magnetic field (0 < z < 3 mm), the eddycurrent may be induced in the conductor. Thus in this section,to investigate the output voltage degradation, the maximumoutput voltage of the boost converter, VOUT, is measured underthe stacked die condition, as shown in Fig. 7(a). The conductor(Al film) is stacked on the coil at a certain distance, d .Fig. 7(b) shows the measured waveform of VOUT under stackedcondition. The maximum VOUT is reduced to 16 V althoughthe boost converter can generate over 20 V, as shown in Fig. 3.

There are two possible reasons for the VOUT degradationof the boost converter. The first reason is the parasitic capac-itance between the coil and conductor. As mentioned before,

HATANAKA et al.: EXPERIMENTAL INVESTIGATION OF PROGRAM VOLTAGE (20 V) GENERATION 191

Fig. 8. Measured dependence of the output voltage on the applied voltageof the conductor.

Fig. 9. Measured output voltage of the boost converter with (a) plane and(b) slit Al film.

parasitic capacitance induces a self-resonance problem.Another possibility is the eddy current on the conductor.Eddy currents degrade the inductance of a coil. Fig. 8shows the dependency of VOUT on the applied voltage ofthe conductor, VCOND. Due to the measurement environment,the distance between the coil and the conductor, d shouldbe more than 140 m, since a double-stick tape is usedfor bonding. From Fig. 8, the output voltage shows theconstant low voltage regardless of VCOND. Therefore, thepotential of the conductor does not affect the output volt-age, VOUT, even if d is the minimum value of 140 m.In Fig. 9, if the conductor has the slits, the output voltagerecovers, as shown in Fig. 9. In this measurement, the outputnode is clamped to 18 V using the electric loads. These resultsshow that the dominant reason for the VOUT degradation is notthe parasitic capacitance but the eddy current on the conductor.The magnetically induced eddy current generates the magneticfield in the opposite direction and cancels the magnetic fields.Then, the equivalent inductance value of the coil becomeslower and VOUT becomes lower.

The magnetic field power strongly depends on thez-position, as shown in Fig. 6. If the distance between thecoil and conductor is enlarged, the VOUT becomes large, asshown in Fig. 10. Fig. 11 shows the measured VOUT asa function of the distance from the coil to the conductor(Al film), d . In Fig. 11, the TON/TOFF of the clock is optimized

Fig. 10. Measured dependency of the output voltage on the TON of the clockand the distance between the coil and the Al film.

Fig. 11. Measured maximum VOUT versus distance from the coil to theconductor, d.

for each condition. In the light load condition, only one NANDchip is activated (CLOAD 100 pF) and the boost converteroperates in the energy-saving mode [2]. Meanwhile, in theheavy load condition, the boost converter generates the pro-gram voltage for 24 parallel NAND chips (CLOAD 2400 pF)in the high-speed mode [2]. As d increases, VOUT reaches thetarget value, 20 V. Therefore, from the measurement results,the space between the Al film and the coil should be largerthan 0.84 mm.

B. Stacked With Si-Chip and ConductorTo emulate the stacked NAND flash chips under the real

condition, Si-chips are inserted between the boost converterand the Al film, as shown in Fig. 12. The optimized TONand TOFF are also used, as shown in Fig. 10. Here, the totaldistance between the conductor and the coil is the sum of theSi-thickness (dSi) and 2 0.1 mm. Note that there are two0.1-mm gaps of Si-chip/coil and Si-chip/conductor. Only fordSi = 0, which is the same situation as d = 0.1 mm in Fig. 11,the total distance is 0.1 mm because only one gap is necessarybetween the coil and the conductor. In case the total thicknessof Si-chip, dSi is larger than 1.02 mm, the boost convertercan generate 20 V because the Si-chip has low conductivityand the eddy current should be suppressed compared with theAl film.

192 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 2, FEBRUARY 2015

Fig. 12. Measured maximum VOUT of the boost converter stacked withSi-chips and conductor. In case the total thickness of Si-chip, dSi is largerthan 1.02 mm, the boost converter can generate 20 V.

Fig. 13. Measured VOUT of the boost converter on the stacked Si-chips. Theprogram voltage (20 V) is successfully generated with the boost converter onstacked Si-chips. (a) Light load case. (b) Heavy load case.

Assuming that 12 NAND flash memory chips and singleDRAM chip are stacked with a 100-m pitch, the distancebetween the coil and the conductor becomes 1.3 mm. There-fore, in a real-world 3-D-integrated SSD, the boost convertercan generate 20 V.

Fig. 13 finally demonstrates 20 V VPGM generations withthe measured VOUT waveform. In this measurement, the boostconverter is stacked with 1.02-m-thick Si-chips. In case of

the light load case where only one NAND flash memory isactivated, VOUT reaches a target voltage of 20 V. Even if24 NAND flash memory chips are programmed in parallel(heavy load case), VOUT = 20 V is successfully generatedfor the program voltage of VPGM.

IV. CONCLUSIONThis paper demonstrates the boosting program voltage, 20 V,

using a boost converter stacked with Si-chips for the first time.Since the output voltage of the boost converter becomes smalldue to the magnetic field emitted by the coil, the 3-D-SSDrequires a >0.84-mm space between the coil and the conductorto generate the program voltage of 20 V. In addition, thepotential of the conductor does not affect the output voltageof the boost converter. By inserting NAND flash memory chipsbetween the coil and the conductor, the 3-D-SSD can besuccessfully realized as a compact package without outputvoltage degradation. Therefore, these investigations providethe feasibility of the 3-D-integrated SSD.

ACKNOWLEDGMENTThe authors would like thank S. Hachiya for his fruitful

discussions.

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Teruyoshi Hatanaka received the B.S. degree in electronics engineering fromthe Tokyo Institute of Technology, Tokyo, Japan, in 2008, and the M.S. degreein electronics engineering from the University of Tokyo, Tokyo, in 2010,where he is currently pursuing the Ph.D. degree.

His current research interests include emerging nonvolatile memories anddc-dc converter circuit design for low-power 3-D integrated solid-state drive.

Koh Johguchi (S06M07) received the B.E., M.E., and Ph.D. degrees inelectrical engineering from Hiroshima University, Higashihiroshima, Japan, in2002, 2004, and 2007, respectively.

He joined the Interdisciplinary research project on integration of semicon-ductor and biotechnology from 2007 to 2009. He was an Assistant Professorwith the HiSIM Research Center, Hiroshima University, from 2009 to 2010.He was a Ph.D. Researcher with the School of Electrical Engineering,University of Tokyo, Tokyo, Japan, from 2010 to 2012, and joined ChuoUniversity, Tokyo, as an Assistant Professor, in 2012, where he has been anAssociate Professor since 2014. His current research interests include low-power memory design and process variation analysis.

Ken Takeuchi (M00) received the B.S. and M.S. degrees in applied physicsand the Ph.D. degree in electric engineering from the University of Tokyo,Tokyo, Japan, in 1991, 1993, and 2006, respectively, and the M.B.A. degreefrom Stanford University, Stanford, CA, USA, in 2003.

He joined Toshiba, Tokyo, in 1993, where he led Toshibas NANDflash memory circuit design for 14 years. He was an Associate Professorwith the Department of Electrical Engineering and Information Systems,Graduate School of Engineering, University of Tokyo, from 2007 to 2012.In 2012, he joined Chuo University, Tokyo. He designed six worldshighest density NAND flash memory products, such as 0.7-m 16-Mb,0.4-um 64-Mb, 0.25-m 256-Mb, 0.16-m 1-Gb, 0.13-m 2-Gb, and 56-nm8-Gb NAND flash memories. He is currently a Professor with the Departmentof Electrical, Electronic, and Communication Engineering, Faculty of Scienceand Engineering, Chuo University. He is involved in the very large scaleintegration circuit (VLSI) design, signal processing and device, and in partic-ular, in the emerging nonvolatile memories, 3-D integrated solid-state drives(SSDs), low-power 3-D large-scale integration (LSI) circuits, and ultralow-voltage SRAMs for Green-IT. He holds 210 patents worldwide, including109 U.S. patents.

Prof. Takeuchi has authored numerous technical papers, one of whichreceived the Takuo Sugano Award for Outstanding Paper at the IEEE Interna-tional Solid-State Circuits Conference (ISSCC) in 2007. In particular, with hisinvention multipage cell architecture, at the Symposium on VLSI Circuits in1997, he successfully commercialized the worlds first multilevel cell NANDflash memory in 2001. He has served as a Program Committee Member ofISSCC, the Asian Solid-State Circuits Conference, the International MemoryWorkshop, and the Non-Volatile Memory Technology Symposium. He servedas a Tutorial Speaker at ISSCC in 2008, an SSD Forum Organizer at ISSCCin 2009, a 3-D LSI Forum Organizer at ISSCC in 2010, an Ultralow-voltageLSI Forum Organizer at ISSCC in 2011, and a Robust VLSI System ForumOrganizer at ISSCC in 2012.

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