Nanoelectronics

Laboratory exercise

An introduction to Cadence and Verilog-A

Mats Ärlelid, Mikael Egard and Lars-Erik Wernersson

Introduction The purpose of the exercise is to give a brief introduction to Cadence and Verilog-A, in order to establish acquaintance with the software before doing the project. The exercise is divided into four parts, where each part deals with different simulation tools. To pass the exercise, the empty fields in the manual should be filled out and one should be able to answer adequate questions concerning the lab. Getting started!! After succeeding login, start a terminal window and write the following lines. > mkdir nanoel > cd nanoel > inittde ams370 Part I To begin with, the DC-simulation will be examined by extracting the IV-characteristics for a 0.35 μm NMOS. Start with creating a new library called nanoel and attach it to the techfile > ‘TECH_C35B4’. The bold text line describes how to create a new library, the syntax is [window > roller bar menu > action (> subaction)]. Library Manager > File > New > Library…

Create a schematic cell view called part1. Library Manager > File > New > Cell View…

Draw the circuit shown in figure 1 by adding instances.

Voltage source vdc analogLib Ground gnd analogLib Resistor res analogLib NMOS nmos4 PRIMLIB Virtuoso Schematic Editing > Add > Instance… The wire is added in the same manner. Virtuoso Schematic Editing > Add > Wire (narrow)

Figure 1: Test bench for the DC properties of a NMOS.

If a property of a component is wrong, select the component and press ‘q’. After every change to the schematic has been done, either wiring or properties, one should always check and save. Virtuoso Schematic Editing > Design > Check and Save Start the analog environment, which is the simulator tool. Virtuoso Schematic Editing > Tools > Analog Environment Choose analyses – select dc and fill out the form. Analog Design Environment > Analyses > Choose…

This analysis will sweep the voltage on the drain of the FET from 0 to 5 volts, the next step is to apply discrete levels of gate voltage and to do that a variable, Vg, has to be launched. Open the properties of the voltage source connected to the gate, the value of the parameter DC voltage is set to Vg. Don’t forget to check and save. Copy the variable into the analog environment. Analog Design Environment > Variables > Copy From Cellview To be able to change the value of Vg for each drain voltage sweep, a parametric analysis is used. Analog Design Environment > Tools > Parametric Analysis …

Start the analysis! Parametric Analysis > Analysis > Start To plot the results of the simulation, start the calculator tool. Analog Design Environment > Tools > Calculator… Since the simulator doesn’t save current, the Id has to be calculated as the voltage drop over the resistor divided by the resistance. To get the voltage on a node, select Vs (voltage sweep) in the calculator and mark the desired wire in the schematic window. The result should resemble figure 2. Extract the following parameters from the CMOS transistor, change the simulation settings if needed. gm gd λ VT Try to extract the maximum gm/Id, and why is this number interesting? When you’re finished with this part, close down all windows except the Library Manager and icfb-window.

Figure 2: IV-characteristics of a 0.35 μm NMOS.

Part II The AC simulation is next up, and is examined using an open loop cascode amplifier once again using 0.35 μm NMOS transistors. Follow the procedure in part I, create a new cell view called part2 and build the circuit in figure 3. Voltage reference vdd analogLib Capacitor cap analogLib Signal generator vsin analogLib

Figure 3: Open loop cascode amplifier.

The cascode amplifier is a basic open loop voltage amplifier, where the cascode transistor increases the bandwidth of the amplifier due to elimination of the Miller effect of the amplifying transistor. The voltage source V2 is the input to the amplifier and the output voltage is over the capacitor C0. Give the voltage source the

following properties: AC magnitude 1 V and DC voltage 1 V. Start the analog environment and choose ac analysis, fill out the form according to the one given below.

This time, we’re not interested in a parametric sweep. The simulation can be started from the Analog Design Environment window by clicking on the green traffic light or by doing the following. Don’t forget to check and save! Analog Design Environment > Simulation > Netlist and Run The ac simulation transforms the transistors to linear models depending on the bias condition, therefore the value set in AC magnitude can be any real number and still the amplifier does not clip the output signal. This also means that the amplifiers linearity can not be examined with this tool. However, the ac simulation is an

excellent tool when checking if an analog circuit is working as it should. Plot the gain of the amplifier. Analog Design Environment > Results > Direct Plot > AC dB20 Select the output node of the amplifier, and press esc. Since the AC magnitude is set to 1, the relative gain of the amplifier is correct. The gain should look something like figure 4.

Figure 4: Voltage gain of an open loop cascode amplifier.

Extract the following parameters of the amplifier. Voltage gain (low frequencies) Bandwidth (-3 dB) Unity gain frequency Part III Another useful tool is the transient analysis, the evaluation of a CMOS inverter will be used as an example for this tool. Start with creating a new schematic cell view called inverter and build the circuit in figure 5. Add the input and output pins. Virtouso Schematic Editing > Add > Pin…

Figure 5: CMOS inverter.

PMOS pmos4 PRIMLIB Now, a symbol cell view should be made of the inverter. Virtouso Schematic Editing > Design > Create Cellview > From Cellview… Click on OK, and set the in and out pins as you wish. After some graphical work (not necessary) you should have a symbol cell view of the inverter according to figure 6.

Figure 6: Symbol cell view of the inverter.

Save the symbol and schematic cell views and close down all windows except for the Library manager window and the icfb-window. Create a new schematic cell view called part3 and build up the circuit in figure 7, which is the inverter test bench. Inverter inverter nanoel Square wave generator vpulse analogLib

Figure 7: Inverter test bench, the inverter load is another identical inverter.

Set the properties of the square wave generator according to the list below.

Start the analog environment and choose the transient analysis, abbreviated as tran. Set the stop time to 12 ns, in order to see a couple periods of the signal. Run the simulation and plot the input and output voltage of the first inverter, by using either the calculator where transient voltage is vt or by using direct plot. Analog Design Environment > Results > Direct Plot > Transient Signal Fill out the table tpHL tpLH

Increase the number of inverters loading the first inverter i.e. increase the fan-out to 3 and redo the simulation. Fill out the table again. tpHL tpLH What has happened and why? Finally, let’s investigate the drive current for the inverter. Set fan-out to 1 again and select the drive current to be saved (no currents are saved unless you define it). Analog Design Environment > Outputs > To be Saved > Select on Schematic Click on the red square on either side of the supply voltage source, V0. Run the simulation and plot the current by using for instance the calculator. Draw an outline of the current below, what is happening?

Part IV The concluding task is to examine the s-parameter tool, which basically is a network analyzer simulator. The arrangement to study this tool is to first make a basic Verilog-A model of a MOSFET. Create a new cell view, this time change the tool to VerilogA-Editor.

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Choose cancel in the Invoke Modelwriter window. A text editor is started, add the text shown below to the editor.

Make a schematic of what you think this model is describing. Try to add the functions needed for Cgs and Id, when the transistor is in cut-off, linear, and saturation region. When the compiler agrees with the code, you will be asked to create a symbol view, do this and save it. Create a schematic cell view called part4 and build the circuit shown in figure 8. “Network Analyzer Port” Port AnalogLib MOSFET Verilog-A model Basic_fet nanoel

Figure 8: Test bench for MOSFET Verilog-A model.

Start the Analog Environment and initiate the Verilog-A compiler. Analog Design Environment > Setup > Environment … Add veriloga to the switch view list. Set the DC voltage of the gate port to 0.5 V and the other port to 1 V, in order to operate the transistor in saturation. Select sp analysis and fill out the form according to the one below.

Run the simulation and plot the current gain in order to extract fT. Analog Design Environment > Results > Direct Plot > Main form Select HP, which stands for h-parameters and plot H21 as dB20. fT Open the properties for the model, select veriloga in the CDF Parameter of view. Here are all the parameters from the model, which can be set as variables. Choose a parameter you are interested in and investigate what happens to the cut-off frequency. Try to use the parametric analysis.