nanomechanical switches for ultra low power and memory · 2014-07-08 · nanomechanical switches...

Nanomechanical Switches for Ultra‐Low‐Power

Computation and Memory

Tsu‐Jae King LiuDepartment of Electrical Engineering and Computer Sciences

University of California, Berkeley, CA 94720‐1770 USA

June 22, 2014“Beyond CMOS Devices” Short Course, st Annual Device Research Conference

A Vision of the Future

• Emergence of Ambient Intelligence:Sense/monitor, communicate and react to the environment Ultra‐low‐power, robust computing technology required!

Smart Grid

Traffic management

Smart Buildings Infrastructure

maintenanceJan Rabaey, ASPDAC 2008

2

Outline• Introduction

– CMOS energy efficiency– Why mechanical switches?

• Nanomechanical switches for computing

• Nanomechanical memory

• Summary

Improving CMOS Energy Efficiency• Parallelism is the main technique to improve system performance

under a power density constraint.

100 101 102 103 1040

20

40

60

80

100N

orm

aliz

ed E

nerg

y/op

1/throughput (ps/op)

Operate at a lower energy

point

Run in parallel to recoup performance

singlecore

dualcore

4

CMOS Energy vs. Delay

4

CMOS Energy Efficient Limit

0.1 0.2 0.3 0.4 0.5

5

10

15

20

25

VDD (V)N

orm

aliz

ed E

nerg

y/op

EtotalIOFF

GATE VOLTAGE

log (CURRENT)

0Edynamic

Dynamic Energy

Eleakage

Leakage Energy

Etotal = αLdfCVDD2 + LdfIOFFVDDtdelay

tdelay = LdfCVDD / (2ION)

α: Activity Factor Ld: Logic Depth f: Fanout C: Capacitance per Stage

VTH VDD

• Leakage & sub‐threshold slope define minimum Energy/op

5

ION

Future Logic Switch Requirements

• Zero leakage

• Simple design

• Robust

• Reconfigurable

• Low operating voltage

Zero standby power

Low active power

Low cost

Wide applicability

Versatility

6

Micro‐Electro‐Mechanical Switch

• Zero OFF‐state current (IOFF); abrupt switching− Turns on by electrostatic force when |VGS| ≥ VPI

− Turns off by spring restoring force when |VGS| ≤ VRL

Source Drain

Measured I‐VCharacteristic

gactuation gcontact

Gate

ON State:

Felec

Fspring

OFF State (as fabricated): NORMALLY OFF

Fadhesion

7

Surface Micromachining Process

sacrificial layerstructural film

Cross‐sectional View

Si wafer substrate • Structures are freed by selective removal of sacrificial layer(s)

• Mechanical structures can be made using conventional microfabrication techniques

8

Three‐Dimensional (3‐D) Integration

9

• The semiconductor industry has developed air‐gap back‐end‐of‐line (BEOL) processes which can be leveraged to make MEM switches.

Time

D. C. Edelstein, 214th ECS Meeting, Abstract #2073, 2008


• Nanomechanical switches for computing– Logic switch designs– Relay‐based integrated circuit design– Relay scaling limit


• Summary

First Micro‐Relay• 4‐terminal (4‐T) micro‐electro‐mechanical switch demonstrated

0.35 m thick 76 m long SiO2 membrane; 7 m actuation gap60 V switching voltage; 40 s switching delay

K. E. Petersen, IEEE Trans. Electron Devices, Vol. 25, pp. 1241‐1250, 1978

11

Structure:

Device Operation:

Scaled 4‐T Electro‐Mechanical Relay• Voltage applied between the gate and movable body brings the channel into contact with source & drain‒ Oxide layer insulates body

Gate

Drain

Source

Gate

Body

A

A’

Isometric View

AA’ Cross-section

Insulator(Al2O3 )

BODY(p+ poly-Si0.4Ge0.6)

Body Dielectric(Al2O3)

channel (W)

DRAIN (W)SOURCE (W) GATE (W)

R. Nathanael et al., IEDM 2009

12

4‐T MEM Relay Process Flow

100nm SiO2

80 nm Al2O3

50 nm W

Si substrate

200nm100nm

Deposit Al2O3 substrate insulator• ALD at 300oC

Deposit & pattern W electrodes• DC magnetron sputtering

Deposit 1st sacrificial LTO• LPCVD at 400oC

Define contact regions

Deposit 2nd sacrificial LTO• tdimple = tgap / 2

Deposit & pattern W channel

Deposit Al2O3 gate oxide

50 nm W

40 nm Al2O3

SiO2


13

TiO2

HFvapor

p+ poly‐Si0.4Ge0.6

SiO2

1m

Deposit p+ poly‐Si0.4Ge0.6 gate• LPCVD at 410oC

Coat with ultra‐thin (~0.3nm) TiO2

• ALD at 300oC

Pattern gate & gate oxide layers using LTO as a hard mask

Release in HF vapor

Process Flow (cont’d)

14


ID‐VG Characteristics• NMOS‐ or PMOS‐like operation is achieved by applying an

appropriate body bias voltage:

R. Nathanael et al., IEDM 2009 15

Zero off‐state leakage; abrupt switching (SS < 0.1 mV/dec)15


1/VDD [V-1]

Num

ber o

f Cyc

les

to F

ail

16

Contact Endurance

complementary inverter

resistive‐load inverter

Y. Chen et al., to be published

• Endurance increases exponentially with decreasing VDD

– projected to reach 1015 cycles at 1 Volt, for W contacts

Cyc

les

to F

ailu

re

1/VDD

Switching Delay

• Turn‐on delay improves with gate overdrive, saturates at ~200 ns for VB = 0V.

Turn‐ON Time vs. Gate Voltage Turn‐ON Time vs. Body Bias

• Turn‐on delay improves w/ body biasing to reduce VPI

100 ns turn‐ON delay

17R. Nathanael et al., IEDM 2009


17

Relay Scaling• Scaling has similar benefits for relays as for MOSFETs:

Scaled Relay DesignSpring constant, keff 1 /

Mass 1 / 3

Pull‐in voltage, VPI 1 / Pull‐in delay, tPI 1 / Switching energy 1 / 3

Device density 2

Power density 1

Relay Parameter Scaling Factor

Pull‐inVoltage:

Pull‐inDelay:

Parameter ValueActuation Area, A 1 m2

Actuation Gap, tgap 4.3 nmDimple Gap, tdimple 3 nmPull‐in voltage, VPI 9.4 mVRelease voltage, VRL 6 mV*^Pull‐in delay, tPI 25 ns

AgkV

0

3actuationeff

PI

DD

PI

actuationeff

contactPI V

Vgk

mgt

Beam length = 3.5 m, thickness = 40 nm, width = 83 nm^ VDD/VPI = 3 *Assumes negligible contact adhesion 18

3

3

eff lEWtk

4 gate delays 1 mechanical delay

• CMOS: delay is set by electrical time constant– Quadratic delay penalty for stacking devices Buffer & distribute logical/electrical effort over many stages

• Relays: delay is dominated by mechanical movement– Can stack ~100 devices before td,elec ≈ td,mech

Implement relay logic as a single complex gate

Digital Circuit Design with RelaysF. Chen et al., ICCAD 2008

19

0 100 2000

2

4

6

8

10

T [C]

VPI

/ V

RL

[V]

VPIVRL

Single‐Gate, Dual‐Source/Drain RelayI‐R. Chen et al., ECS Spring Meeting 2012 and Transducers 2013

Plan‐View SEM

Temperature Dependence:

Channel

Gate

BodySource 1

Drain 1

Source 2

Drain 2

Anchor

5 µm0 5 10

10-12

10-9

10-6

10-3

VG [V]

Cur

rent

[A]

IDS1IDS2IG

Measured I‐V Characteristics

0 2 4 6 8 10

10-12

10-9

10-6

10-3

VG [V]

I DS [A

]

VB = 0VVB = ‐7.1V

with body bias

20

Relay Multiplier Sub‐Ckt: (7:3) Compressor

0 1 2 3 4 5 6 7 8 90246

Y1 o

utpu

t (V)

0 1 2 3 4 5 6 7 8 90246

Y2 o

utpu

t (V)

0 1 2 3 4 5 6 7 8 90

50

100

150

Inpu

t cod

e

Time(S)

0 1 2 3 4 5 6 7 8 90246

Y0 o

utpu

t (V)

• Most complexscaled MEM‐relay integrated circuit reported to date (46 relays)

21

Fariborzi et al., ASSCC 2011

Energy‐Delay Comparison with CMOS• 90nm relay vs. CMOS adders and multipliers:

>2‐100× energy savings @ 3‐100× higher delay

M. Spencer et al., JSSC 2011; H. Fariborzi et al., ESSCIRC 2011

Ener

gy (f

J)

Delay (ns)

22

Adder Comparison Multiplier Comparison

VB_HIGH

VB_LOW

VOUTVINVOUT

VDD

GND

=1V

=13V

=‐12V

=0V

(INV) (BUF)

Single‐Gate Relay Inverter/BufferR. Nathanael et al., VLSI‐TSA 2012

1 0 1 1 000 1

BUF

INV

VOUT

VOUT

0

0.5

1

0 0.2 0.4

VIN(V)

0

0.5

1

0 0.2 0.4

VOUT(V)

Time (s)

(a)

(b)

23

Dual‐Gate, Dual Source/Drain Relay

• Gate electrodes are interdigitated to ensure that each gate has equal influence on the movable body

Bottom (Gate) Electrode Layout

Gate 1Gate 2

Drain 1 Drain 2

Body

Source 1 Source 2

Circuit Symbol

R. Nathanael et al., VLSI‐TSA 2012

24

0

4

8

12

16

20

Input [V IN1, V IN2]

VPI, V

RL (V

)

VPI VRL

[0, 1] [1, 0] [1, 1]

VDS=1.5V, VB=0V

Measured VPI & VRL of Dual‐Gate Relay

• “1”≡VG

• Each gate has equal influence

• Depending on VB, relay can be actuated using one or two gate electrodes

Gate 1

Gate 2

R. Nathanael et al., VLSI‐TSA 2012

25

VIN1

GND

VIN2

VOUT

VOUT

VDD

VB_HIGH

VB_LOW

=8V

=0V

=15V

=‐4V

(AND)

(NAND)

(a)

(b)

(c)

0 0 1 1

0 1 0 1

0

0

NAND

AND

VOUT

VOUT

0

4

8

0 0.1 0.2 0.3

V IN2(V)

048

0 0.1 0.2 0.3

V IN1(V)

0

4

8

0 0.1 0.2 0.3

V OUT(V)

Time (s)

Dual‐Gate Relay Circuit: AND/NANDR. Nathanael et al., VLSI‐TSA 2012

26

VIN1

GND

VIN2

VOUT

VOUT

VDD

VB_HIGH

VB_LOW

=8V

=0V

=12V

=‐6V

(OR)

(NOR)

(a)

(b)

(c)

0 0 1 1

0 1 0 1

0

00

4

8

0 0.1 0.2 0.3

V IN2(V)

048

0 0.1 0.2 0.3

V IN1(V)

NOR

OR

VOUT

VOUT0

4

8

0 0.1 0.2 0.3

V OUT(V)

Time (s)

Dual‐Gate Relay Circuit: OR/NORR. Nathanael et al., VLSI‐TSA 2012

27

See‐Saw (Active Turn‐Off) Relay• Perfectly complementary switching , symmetric about VDD/2

ID-VG characteristics

Scanning Electron

Micrographs:

Switching Voltages vs. VDD

J. Jeon et al., IEEE Electron Device Letters, Vol. 31, No. 4, pp. 371‐373, 2010

1

3

5

7

9

7 9 11 13

V ON

(V)

VBR or VDD (V)

VON_RIGHT

VON_LEFT

VBR/2=VDD/2

LA=42μmLA1=9μmWA=40μm

1E-15

1E-13

1E-11

1E-09

1E-07

1E-05

1E-03

0 2 4 6 8 10

I DS

(A)

VG (V)

IDS_RIGHT

IDS_LEFT

VON_LEFT=VOFF_RIGHT=7.14V

VON_RIGHT=VOFF_LEFT=3.16V

LA=42μmLA1=12μmWA=40μm

28

See‐Saw Relay Logic GatesCircuit Symbol Relay Configurations

Demonstrated Single-Input Operations

Demonstrated Dual-Input Operations Function VG VBL VSL VBR VSR

BUFFER VIN LO HI HI LO

INVERTER VIN LO LO HI HI

AND VIN1 LO VIN2 HI LO

OR VIN1 LO HI HI VIN2

G DRDL

BL

SRSL

BR

VOUT

0

6

12

V IN

1(V

)

0

0.5

1

V IN

2(V

)

0

0.5

1

V OU

T (V

)0

0.5

1

0.00 0.03 0.06 0.09 0.12

V OU

T(V

)

Time (s)

00 01 11 10

AND0 0 1 0

OR0 1 1 1

IN2

IN1

0

0.5

1

V OU

T(V

)

0

0.5

1

0.00 0.03 0.06 0.09 0.12

V OU

T(V

)

Time (s)

INVERTER

BUFFER0 1

1 0

0

6

12

V IN

(V)

0 1 INPUT

J. Jeon et al., IEEE/ASME Journal of MicroElectroMechanical Systems, Vol. 19, No. 4, pp. 1012‐1014, 2010

29

Stiction: Relay Scaling Limiter (?)

To turn on the relay: electrostatic force Felec > Fspring

In order for a conventional electrostatic switch to turn off properly, Fspring > Fadhesion

> Fadhesion

Limits scaling of actuation area A and/or VPI

30

Contact Adhesive Force Scaling

• Adhesive force is lowered by TiO2 coating

Schematic cross-section of contact dimple:

• Model indicates that adhesion is due to van der Waals force– FA should scale with area, 0.02 nN/nm2 for W‐W contact

tunneling current

J. Yaung et al., IEEE/ASME Journal of Microelectromechanical Systems, Vol. 23, pp. 198‐203, 2014

31

10 mV Micromechanical Switch OperationU. Zaghloul et al., IEEE Electron Device Letters Vol. 35, pp. 669‐671, June 2014

32

4‐T piezoelectric relay I‐V Characteristics

Input/Output Waveforms

• Small hysteresis is indicative of low surface adhesion

• ~23 aJ projected switching energy for 5 mV operation

Non‐Volatile Memory TechnologiesITRS (Table ERD3), 2011 Edition

In contrast to logic switches, NVM devices can have:

• Long write/erase times (>1 us)

• Modest endurance (< 106 cycles)

• Large operating voltages (>1 V)

33



• Nanomechanical memory– Early designs– Recent design for cross‐point array architecture

• Summary

First MEMS NVM Cell

• Bistable buckled beam– Switched with electrostatic force

– Immune to radiation, shock

• Too large (>100um2) for reasonable storage capacities…

B. Halg, IEEE Trans. Electron Devices, Vol. 37, pp. 2230‐2236, 1990

35

• The beam can be pulled out of contact by biasing the cap.• A select device (e.g. a transistor) is needed for each MEM

switch in the memory array.

NanomechTM Technology

TEM cross-section

R. Gaddi et al. (Cavendish Kinetics), Microelectronics Reliability Vol. 50, pp. 1593‐1598, 2010

metal cap

Endurance test results

36

Cross‐Point Array Architecture• Most compact architecture (4F2 cell size)• Requires selector device at each cross‐point to reduce

“sneak” leakage current during a read operation– e.g. 2‐terminal diode

http://www.smartplanet.com/blog/thinking‐tech/what‐might‐replace‐flash‐memory/943

Bit Lines (BL)

+VRead

37

Electro‐Mechanical Diode NVM Cell• Achieve bi‐stable operation of an electrostatic gap‐closing

actuator by leveraging the built‐in electric field of a diode:

W. Kwon et al. (UC Berkeley), IEEE Electron Device Letters, Vol. 33, pp. 131‐133, 2012

BL (n-type)

WL (p-type )

Isolation Dielectric BL (n-type)

WL (p-type )

Isolation Dielectric

Reset StateCROSS‐SECTIONAL ILLUSTRATIONS

BL (n-type)


WL (p-type)

BL (n-type)


WL (p-type)

Set State

Fadhesion + Felec > Fspring

V

g

0

pull‐in

release

reverse diode biasforward diode bias

×2 stable states

×VRead

VPIVRL

38

First Prototype MEM Diode• Cross‐point arrays of MEM diodes were fabricated using conventional planar processing techniques.

Bird’s‐eye view of memory array Cross‐sectional view of a bit‐cell


The WL (100‐nm p‐type poly‐Si0.4Ge0.6) is supported by SiNx spacers formed along the sidewalls of the BL (100 nm n‐type poly‐Si).

The air‐gap (~13 nm thick) between the WL and BL is formed by selectively removing a sacrificial layer of LTO using HF vapor.

39

Set Operation

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

0 2 4 6 8

VBL[V]

Cur

rent

[A

]

IGIGWith 1M Ω resistorWithout resistor

Current reduction by external resistor

Vpull-in1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

0 2 4 6 8

VBL[V]

Cur

rent

[A

]

IGIGWith 1M Ω resistorWithout resistor

Current reduction by external resistor

Vpull-in

VWL = 0V• A sudden increase in current is seen at the voltage when the WL is pulled in to the BL.― VSet 6 V, tSet 2 us

• Since it is an applied voltage (not current) that is required to actuate the WL, the Set current can be lowered by inserting a current‐limiting resistor.

Current vs. Applied Voltage


40

I‐V Characteristics

-25

-20

-15

-10

-5

0

5

10

-1.5 -1 -0.5 0 0.5 1 1.5VBL[V]

Cur

rent

[μA

]

Set stateReset state

1E-13

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

-1.5 -1 -0.5 0 0.5 1 1.5VBL[V]

|Cur

rent

| [A

]

Log Current Scale Linear Current Scale

• Set/Reset current ratio > 106– Leakage through SiNx spacers can be reduced with process improvements.

• For VRead = 1.2 V, the ratio of Set cell current to sneak path leakage current is ~100 for the prototype device

– This rectification ratio can be increased with process improvements.


>106

41

Reset Operation

• To Reset a memory cell, a voltage pulse is applied to counteract the built‐in field of the p‐n diode.

– forward bias current flow

• A sudden decrease in current is seen at the voltage when the WL comes out of contact with the BL. VReset ‐6 V, tReset 100 ms

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

-8 -7 -6 -5 -4 -3 -2 -1 0VBL[V]

|Cur

rent

| [A

]

Vrelease1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

-8 -7 -6 -5 -4 -3 -2 -1 0VBL[V]

|Cur

rent

| [A

]

Vrelease

VWL = 0V

Current vs. Applied Voltage


42

Retention Behavior

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

1E+00 1E+01 1E+02 1E+03 1E+04 1E+05Retention Time [sec]

|Cur

rent

| [A

]

Set stateReset state

T = 200oC


43

Endurance Characteristics

P = 1 atm; T = 25oC

1E-141E-13

1E-121E-11

1E-101E-09

1E-081E-07

1E-061E-05

1E-04

1 10 100 1000 10000# of cycle

|Cur

rent

| [A

] Set: VBL=6V, VWL=0V, 1msec

Reset: VBL=-15V, VWL=0V, 100msec

Read : VBL=-1.2V

1E-141E-13

1E-121E-11

1E-101E-09

1E-081E-07

1E-061E-05

1E-04

1 10 100 1000 10000# of cycle

|Cur

rent

| [A

] Set: VBL=6V, VWL=0V, 1msec

Reset: VBL=-15V, VWL=0V, 100msec

Read : VBL=-1.2V


44

Technology NAND Flash PCM STT-MRAM Redox RRAM Electro-mechanical diode

Cell Size 2.5 F2 6 F2 20-40 F2 5-8 F2 4-6 F2

Scaling Limit 16 nm 5-10 nm 7-10 nm 5-10 nm 5 nm W x 20 nm L

Storage Mechanism F-N TunnelingPhase change

by Joule heating

Electron spin torque transfer

Ion transport and redox reaction

Mechanical gap closing actuation

Write/Erase Voltage 18-20 V < 3 V < 1.8 V < 0.5 V < 3 V

Write time >10 us 50-120 ns < 100 ns < 5 ns < 1 ns

Endurance 104 - 105 1015 1012 1016 >1010

Retention 10 yrs 10 yrs 10 yrs 10 yrs > 10 yrs @ 200 ℃

Ease of Integration 10 Masks 2-3 Masks to BEOL

3-4 Masks to BEOL

2-3 Masks to BEOL 2 Masks

Write Energy per Bit > 1 fJ < 2 pJ < 4 pJ 1 fJ < 0.1 fJ

Scaled NVM Technology Comparison

• NEMory technology potentially offers the best performance and lowest energy consumption!

W. Kwon et al. (UC Berkeley), 2012 International Memory Workshop

http://www.itrs.net/Links/2010ITRS/2010Update/ToPost/ERD_ERM_2010FINALReportMemoryAssessment_ITRS.pdf

45

3‐D Integration

• Conventional cross‐point memory array technologies require 2 lithography steps per memory layer

Unity Semiconductor Corp.

• NEMory technology requires only 2 lithography steps to define the 3‐D memory array

– built‐in redundancy (2 WL/cell)– allows for longer beam length

W. Kwon et al. PhD thesis, UC BerkeleyWord Lines

Bit Lines

46




• Summary

Summary• Electronic devices which enable more energy‐efficient

computing and information storage, at ever lower cost per function, will be required to realize the vision of ambient intelligence.

• Mechanical devices show promise in this regard:Ideal switching behaviorSimple fabrication process (lower cost)Enhanced device functionalityAdequate reliability

Contact adhesive forces must be well controlled in order to fully realize this promise.

48

Acknowledgements• Faculty: Elad Alon, Vladimir Stojanović; Dejan Marković (UCLA)• Former post‐docs: Vincent Pott (LSI Logic), Louis Hutin (CEA‐LETI)• Former students: Hei Kam, Jaeseok Jeon, Rhesa Nathanael, Jack Yaung,

Wookhyun Kwon @ MIT: Fred Chen, Sumit Datta, Hossein Fariborzi@ UCLA: Kevin Dwan, Cheng C. Wang, Mingzhe Jiang

• Students: I‐Ru Chen, Yenhao Chen, Chuang Qian, Matt Spencer• SEMATECH: Muhammad Hussain, Casey Smith, Chanro Park, Weize Xiong,

Rinus Lee

• Research Funding:DARPA/MTO NEMS ProgramDARPA/MARCO Focus Center Research ProgramNSF Center of Integrated Nanomechanical Systems (COINS)NSF Center for Energy Efficient Electronics Science (E3S)

• UC Berkeley Micro/Nanofabrication Laboratory 49

nanomechanical switches for ultra low power and memory · 2014-07-08 · nanomechanical switches...

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