nanotechnology: spatial computing using molecular electronics mihai budiu joint work with seth copen...
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Nanotechnology: Spatial Computing Using Molecular
Electronics
Mihai Budiujoint work with
Seth Copen Goldstein
Dan Rosewater
SSS April 20, 2001 2
Intersection of Three Areas
Reconfigurablecomputing
Nanotechnology
Computerarchitecture
SSS April 20, 2001 3
Prophecies, A Risky Endeavor
I think there is a world market for maybe five computers.
--- T. J. Watson
640K ought to be enough for everybody. --- Bill Gates
There is no reason anyone would want a computer in their home. --- Ken Olson
I will propose this semester.--- Anonymous
There is not the slightest indication that nuclear energy will ever be obtainable.
--- Albert Einstein
SSS April 20, 2001 4
Moore’s Law
SSS April 20, 2001 5
Moore’s Second Law
Plant cost Mask cost
generation
X 1
000$
SSS April 20, 2001 6
Our Proposal
Nanotechnology+ cheap+ high-density+ low-power– unreliable
Computer architecture+ vast body of knowledge – expensive– high-power
Reconfigurable Computing+ defect tolerant+ high performance– low density
++++ +
+_
__
_
SSS April 20, 2001 7
Paradigm Shift
Executable Configuration
Complex fixed chip+
Program
Dense, regular structure+
Configuration
SSS April 20, 2001 8
Outline
Introduction
• Reconfigurable computing
• Nanotechnology
• Nano-architecture proposal
• Preliminary results
• Conclusions and Future Work
SSS April 20, 2001 9
Reconfigurable Computing
• Back to ENIAC-style computing
• Synthesize one machine to solve one problem
SSS April 20, 2001 10
Island-Style RC Architecture
Universal gates
and/or
storage elements
Interconnectionnetwork
Programmable Switches
SSS April 20, 2001 11
Switch controlled by a 1-bit RAM cell
0001
Universal gate = RAM
a0a1a0
a1
dataa1 & a2
0data in
control
Main RC Ingredient: RAM Cell
SSS April 20, 2001 12
Place and Route
int reverse(int x){ int k,r=0; for (k=0; k<64; k++) r |= x&1; x = x >> 1; r = r << 1; }}int func(int* a,int *b){ int j,sum=0; for (j=0; *a>0; j++) sum+=reverse(*b
SSS April 20, 2001 13
Kernel Speedup Using PipeRench
189.7
15.511.3 12.0
63.342.4
26.0
57.1
29.0
1
10
100
1000
ATR
Cordic
DCT
DCT-2D
FIRID
EA
Nquee
nsOve
r
PopCou
ntTim
es O
ver
300M
hz
Ult
raS
par
c-II
SSS April 20, 2001 14
Defect Tolerance
Despite having >70% of the chips defective, Teramac works flawlessly.
Compilation has two phases:• defect detection through self-testing• placement for defect-avoidance
SSS April 20, 2001 15
Outline
Introduction Reconfigurable computing
• Nanotechnology
• Nano-architecture proposal
• Preliminary results
• Conclusions and Future work
SSS April 20, 2001 16
Nanotechnology
SSS April 20, 2001 17
Predicted Features
• Low Power: 1010 gates use less than 2 W(compare to 3x107 transistors using 100 W in
CMOS)
• Low cost (nanocents/gate)
• Small size (105 factor area gain)
Nano-RAM cell
In yellow: a CMOS RAM cell.
SSS April 20, 2001 18
Nano-wires
• carbon nanotubues, Si, metal• >2nm diameter, up to mm length• excellent electrical properties
A carbon nanotube: one molecule
SSS April 20, 2001 19
Nano-switch
SSS April 20, 2001 20
Nano-switch Between Nano-wires
SSS April 20, 2001 21
Self-assembly
SSS April 20, 2001 22
No Complex Irregular Structures
SSS April 20, 2001 23
No Three-Terminal Devices
SSS April 20, 2001 24
Diode-resistor Logic
VDD
OutputInput 1
Input 2
A * B
V AND
BA
A ^ B
VVV AND
A
BA
B
A * B
Nano-implementation Electrical equivalent
SSS April 20, 2001 25
Nanoscale Latches
D clock
data out
Provide:• signal restoration (amplification)• clocking (synchronization)• memory
SSS April 20, 2001 26
High Defect Rate
SSS April 20, 2001 27
Outline
Introduction Reconfigurable computing Nanotechnology
• Nano-architecture proposal
• Preliminary results
• Conclusions and future work
SSS April 20, 2001 28
The nanoBlock (3-in to 3-out Logic)
+VddG
nd
Gndclk
Inputs
Outputs
CMOS
clk
SSS April 20, 2001 29
Interconnecting nanoBlocks
Switch block
SSS April 20, 2001 30
Global View
SSS April 20, 2001 31
Con
trol
cluster
long-lines
Many Clusters = nanoFabric
SSS April 20, 2001 32
Compilation
1. Program
2. Split-phase Abstract Machines
3. Configurations placed independently
4. Placement on chip
int reverse(int x){ int k,r=0; for (k=0; k<64; k++) r |= x&1; x = x >> 1; r = r << 1; }}
Computations& local storage
Unknown latency ops.
SSS April 20, 2001 33
Outline
Introduction Reconfigurable Hardware Nanotechnology Nano-architecture proposal
• Preliminary results
• Conclusions and Future work
SSS April 20, 2001 34
A graph of the whole program execution:
A Limit Study of Performance
Memory word
Basic block
Memory write
Memory read
Control-flow transfer
SSS April 20, 2001 35
Area(106 units/cm2 available)
0
50000
100000
150000
200000
250000
099.
go
129.
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pres
s13
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132.
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un
its
memory area
code area
SSS April 20, 2001 36
Typical Program Graph (g721_e)
Control flow transfer
100% memory cluster
Memory reads
100% code cluster
SSS April 20, 2001 37
Typical Program Graph (g721_e)
Control flow transfer
memory
Memory reads
code
memcpy
SSS April 20, 2001 38
Program Graph After Inlining memcpy
memcpy
SSS April 20, 2001 39
Application Slowdown
-1
0
1
2
3
4
5
6
7
8
9
10
11
tim
es s
low
er t
han
nat
ive
1 clock/square 5 clocks/square
SSS April 20, 2001 40
How Time Is Spent
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
099.g
o
129.c
ompr
ess
130.l
i
132.i
jpeg
adpc
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gsm
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jpeg_d
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mpe
g2_d
per
cen
t
idle
executioncontrol flow
register traffic
No caches: reads expensive
No speculation
SSS April 20, 2001 41
Future Work
• Better nano-devices
• More accurate hardware models in simulations
• Compilation technology
SSS April 20, 2001 42
Conclusions
• Electronic nanotechnology promises to transcend the limitations of CMOS
• Nanofabrics are very well suited to reconfigurable computation
• 109-gate designs can be managed through hierarchies of abstract machines