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9 July 2013

FOCUS ON SENSORS • BATTERY CHARGING • COMMUNICATIONS PROCESSORS

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THE EVOLUTION CONTINUES

IMAGINE A WORLD WITHOUT

ELECTRONIC SYSTEMS

Contents Vol 46 No 13

9 July 2013 3www.newelectronics.co.uk

Comment 5

ESCO Report says

industry should ‘get

smart’ in order to

deliver growth

News 7

Xilinx readies 20nm

and 16nm devices

which move ‘beyond

programmable logic’

Digi-Key puts its

weight behind the

Electronics Design

Show and

Conference

Silicon Labs

launches MEMS/

cmos combo

oscillator for high

volume applications

EPSRC plugs £18m

over six years into

four areas of power

electronics research

The most popular

items from the

New Electronics

website

24

8

16

Interview 12

Maverick or visionary?Andy Pease says Quicklogic’s focus on programmable logic

in the mobile market is the right path – despite what its

competitors might think

Cover Story 16

Designing the futureThe Electronic Systems sector is a vital contributor to the

UK’s GDP. Can that contribution be grown by 50% by 2020

and employment increased? Yes, says the ESCO Report

Sector Focus: Sensors

Little energy for perfect pixels 22

Getting the right light balance in pictures can be a tricky

business, but a new sensor chip could make expert

photographers of us all

Ink draws on negative charge 24

Commercial exploitation of carbon nanotube based sensors

remains just around the corner. But that may be about

to change with the development of a customisable ink

Digital Design 26

Packaging pushes performanceHow the bandwidth of DDR applications can be extended

and performance improved by changing from wirebond to

flip chip packages

Power 28

Charging is conditionalSmaller products, as well as demand for faster charging

and longer times between charges, are providing the

momentum for changes in battery charging technology

Processors 31

Many core magiciansMany core solutions with low power consumption are

being developed in order to meet the demands of those

designing communications infrastructure equipment.

Backplanes & Boards 35

The next generation

Devices in the 4th generation of Intel Core processors

are bringing one microarchitecture suitable for all mid

to high end embedded applications

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Comment

After 18 months of discussion, research and analysis, the ESCO Report –

Electronic Systems: Challenges and Opportunities – has been published,

providing, in a way which hasn’t been done before, an accurate picture of

electronics’ contribution to the UK economy.

We know electronics is pervasive, but previous ‘best guesses’ have put UK

employment closer to 250,000 people. ESCO says the electronic systems sector

– by definition, wider than pure electronics – sustains 850,000 jobs. It also

estimates the electronic systems sector contributes £78billion to the UK’s GDP –

another figure which focuses the mind.

But ESCO is about growth – it wants GDP contribution to grow to £120bn and

employment to 1million by 2020. The big question is ‘how’? Its three top line

objectives are: to build greater recognition of the sector; to help vertical sectors

grow; and to exploit the UK’s ES capability globally.

One of the big surprises is the absence of calls for funding, special initiatives

and so on. Perhaps that’s a realistic appraisal of the economic situation, but it

could also be an acceptance that it’s up to the industry to sort itself out.

Industry leaders, the report says, should take ownership of making change

happen. ‘We believe our future is in our hands’, it says.

The word ‘smart’ is a recurrent theme – leadership, industries, partnerships,

supply chains, skills and brands. The implication is we aren’t, but need to be.

The report points out the lack of any large electronics companies beyond ARM

and Imagination – both IP developers, rather than hardware. It wonders why

countries of similar physical size and GDP – Taiwan and South Korea are cited –

have successful electronics industries while the UK doesn’t. It wonders – with a

nod towards the likes of Samsung – why the UK doesn’t have ‘globally dominant

consumer facing brands’. That question alone would take a while to answer.

For now, the future lies in helping verticals to develop better products,

bringing benefits to entire supply chains and, hence, to the UK’s economy.

But, first things first, there’s the small matter of uniting the industry behind

one flag. New Electronics has used the phrase ‘herding cats’ before in this

context and has no hesitation in using it again.

Graham Pitcher, Group Editor ([email protected])

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Programmable Logic News

A matter of scale‘Asic like’ architecture to underpin Xilinx’ future

products. Graham Pitcher reports.

Xilinx has launched the Ultrascale architecture, intended to take its products beyond the 20nm node.

European marketing director Giles Peckham said: “Ultrascale devices, which support 20nm linear and

16nm finfet technology and beyond, will bring asic class performance to customers looking for a high level

of integration and performance.”

According to Peckham, each generation of programmable logic brings bottlenecks. “Routing, clocking,

critical paths and power are some,” he offered. “Customers want high throughput and low latency.”

The Ultrascale architecture is said to deal with a number of these issues. “The number one issue is

interconnect,” Peckham noted. “We learned from our first generation 3d products that 10,000

interconnects are not always enough. We have extended this and made it lower latency.” However, he said

the problem hadn’t been solved by ‘throwing metal’ at it. “It’s a matter of applying it intelligently,” he

claimed. Clock skew – another pressing issue – has been addressed using a ‘more asic like’ architecture

with smaller clock domains. The 20nm process also consumes 30% less static power than 28nm devices.

Design closure has been improved, with the updated Vivado design software enabling utilisation rates

of more than 90%.

Ultrascale also sees the end of the numerical progression of Xilinx’ products. “That was synonymous

with process node,” said Peckham. “Ultrascale will span nodes.” The Ultrascale brand will be applied to any

Xilinx device made on a 20nm process and beyond.

Meanwhile, Xilinx has taped out 20nm devices and expects silicon by the end of the year. It says 16nm

parts will be taped out shortly, with silicon by the end of 2014.

Described as an important step in the

development of thin film solar cells,

imomec and Solliance have

developed a 1cm2 CZTSe

(Cu2ZnSnSe4) based

solar cell with an

efficiency of 9.7%.

“This is a big win for

us,” said Marc Meuris,

Solliance’s programme manager.

“Our efficiencies are the highest in

Europe and approaching the world record

for this type of thin film solar cell.”

CZTSe, an emerging solar cell absorber, has

properties similar to CZTS (Cu2ZnSnS4).

Imomec, imec and Solliance have

defined a path towards further

improving the layers and

cell structures of

CZTSe and CZTS

absorbers to

produce solar cells

with 20% efficiency.

Imec’s thin film solar

cell activities at imomec

(imec’s associated laboratory at

the University of Hasselt) are

integrated in the Solliance collaboration

platform. The research was partially

supported by the Flemish government.

Bright future for solar cells

Momentum is building for the Electronics Design

Show, which takes place at the Ricoh Arena in

Coventry on 2 and 3 October 2013.

With 16 high level conference sessions, 20 free

practical workshops and more than 80 companies

exhibiting cutting edge technology and innovation,

the Electronics Design Show addresses all aspects

of electronics design under one roof.

The Electronics Design Show is supported by

headline sponsors Altium, Premier EDA Solutions,

Digi-Key, RS Components and Avnet Memec.

Digi-Key’s president

Mark Larson, pictured,

said: “Digi-Key is excited

to be a headline sponsor

of the 2013 Electronics

Design Show. As we

continue to expand our

global presence in Europe, we’re pleased to have

this opportunity to interact face to face with

suppliers, customers and prospects in the UK.”

To register, go to www.electronicsdesignshow.co.uk

Digi-Key backs Electronics Design Show


More MIPS cores

Imagination Technologies will update the MIPSAptiv core range and unveil new 32bit and 64bitMIPS cpus later this year. The Series5 generationof cores, codenamed Warrior, will integrate newarchitectural features.

Hossein Yassaie, Imagination’s ceo, said: “Wehave an outstanding range of cores and that willbe complemented by our forthcoming ‘Warrior’cores, which will provide levels of performance,efficiency and functionality that go beyond otherofferings.”

A small footprint single core device will beadded to the interAptiv family and a floatingpoint core to the microAptiv family. Meanwhile,Warrior cores will focus on providing higherperformance efficiency across the range.

East to lead

ESCO efforts

ARM’s outgoing ceo Warren East will chair the

ESCO Leadership Forum (ESLF), a body which

aims to realise the goals set out in the recently

announced ESCO Report. Included in the report’s

targets are increasing the sector’s GDP

contribution to £120billion per annum by 2020

and supporting 1million jobs.

“There is huge opportunity for industry and

government to work together on a modern

industrial partnership strategy,” said East. “UK

based Electronic Systems companies will lead

the world if we get this right and, at the same

time, drive economic growth in the UK.”

• For more on the ESCO Report, see the Cover

Story on p16 of this issue.

Power management

acquisition

Dialog has signed a definitive agreement to

acquire iWatt for $310million in cash. Silicon

Valley based iWatt specialises in digital power

management ics (pmics). Its PrimAccurate

technology platform is said to enable energy

efficient, small form factor and cost effective

solutions for a range of markets.

Jalal Bagherli, Dialog’s ceo, said: “This

acquisition is complementary to our existing

pmic business, enabling Dialog to address

adjacent emerging power management

segments, including cutting edge ac/dc solutions

for next generation fast portable chargers, as well

as ics for led solid state lighting.”

Briefs

News Frequency Management

In a move said to ‘fill a hole’ in its timing technology

portfolio, Silicon Labs has launched what it believes

to be the most integrated MEMS based oscillators

currently available. The devices are intended to

replace general purpose crystal oscillators in cost

sensitive, high volume applications.

The Si50x range is made using the company’s

CMEMS technology, which allows MEMS structures

to be built directly on top of standard

cmos wafers.

Mike Petrowski, general

manager of the company’s

timing solutions business, said:

“Integration not only has cost

advantages and makes it easier

for us to scale to volume, it also

gives the best performance.”

The Si50x oscillators support

frequencies between 32kHz and

100MHz, with frequency stability

options of ±20, ±30 and ±50ppm across

the extended commercial and industrial

temperature ranges.

Four products have been announced. The Si501

is a single frequency oscillator with output enable

(OE) functionality, while the dual frequency Si502

boasts OE and frequency select (FS) functionality.

The quad frequency Si503 supports FS technology.

The fourth device, the Si504, is fully programmable

between 32kHz and 100MHz via a

single pin interface.

All devices feature

passive temperature

compensation, achieved by

making the resonator from a

combination of SiGe and SiO2.

“Both materials have different

temperature performance,”

said Petrowski. “SiGe gets

harder as it cools, while SiO2 gets

softer. Their interaction over

temperature minimises frequency drift.”

9 July 20138 www.newelectronics.co.uk

Timing is everythingMEMS oscillator range is ‘most highly integrated’.

Graham Pitcher reports..

Tek to use leading

edge IBM process

The next generation of high performance real timeoscilloscopes from Tektronix will feature devicesmanufactured on IBM’s 9HP SiGe process. Thetechnology, along with other advances, will enableoscilloscopes with bandwidths of up to 70GHz andimproved signal fidelity.

Tektronix’ next generation performanceoscilloscopes, set for launch in 2014, willsupport 400Gbit/s and 1Tbit/s opticalcommunications and fourth generation serialdata communications.

Wireless at

Williams

More than 130 design engineers attended the RFand Wireless Forum, held at the end of June atthe Williams Formula 1 Centre near Oxford.

A full conference programme wascomplemented by an exhibition, with some newproducts launched. New offerings included theeRIC (easyRadio IC) radio transceiver from LPRSand Murata’s LBEP series of wireless modules,providing LAN, Bluetooth and Bluetooth LowEnergy connectivity. Linear Technology alsotalked about releasing an rf mixer chip and amesh network solution this summer.

One delegate commented: “A customer askedme to investigate wireless technologies for itsnext generation consumer product – which mustwork in a bathroom environment. I’ve metleading industry experts and gained sufficienttechnical knowledge to address itsrequirements.”• The next event, Power and Power Management,takes place at the same venue in October. Formore, go to fortronicuk.com


FPGAs for automotive apps

Looking to enable new functionality in automotive

designs, Lattice has launched the LA-LatticeECP3

family of AEC-Q100 qualified fpgas. It says the

family is aimed at mid to low range vehicles.

Gordon Hands, director of marketing for low

density products, said: “We have been looking to

drive down power consumption and cost in such a

way that fpgas can be adopted in applications

where they couldn’t be used before. This family will

enable automotive designers to adopt the

technology more broadly.”

The family is available with a choice of 17,000

and 35,000 look up tables and each variant has

three packaging options. All variants are in volume

manufacture and are suitable for use in

temperatures ranging from -40 to 105°C.

One potential application for an fpga/sensor

package is as a rear facing camera to replace wing

mirrors – a move that could improve fuel economy

by up to 5%.

News Analysis Power Electronics

It’s approaching two years since the Department for

Business, Innovation and Skills published a report

outlining the importance of the power electronics

sector to the UK, along with a way to maintain what

was perceived as a leading position in the technology.

While the report – called Power Electronics: A

Strategy for Success – acknowledged that UK

universities and industry have extensive expertise

and experience in the sector, it identified four sectors

where power electronics was likely to see rapid growth

and the need for further innovation: transport; energy

generation, transmission and distribution; consumer

electronics and lighting; and industrial drives.

Despite the opportunities, the report highlighted

issues which needed to be addressed, not the least of

which was ensuring there were enough suitably

skilled people to meet future needs.

Addressing the various issues, it concluded, would

require coordinated action. But the lack of a single

organisation promoting power electronics meant there was poor

communication, poor skills and missed opportunities.

Looking to deal with these points, an industry initiative called

PowerelectronicsUK (www.power-electronics.org.uk) was launched in May 2013.

While the group believes power electronics innovation in the UK is ‘in good

shape’, it concedes the sector needs more support to ensure companies doesn’t

miss out on what it sees as a range of opportunities. Importantly, it pointed out

that power electronics – as a technology – does not feature in national projects.

And one of the funding bodies at which the finger was pointed was EPSRC.

That situation has been remedied with the recent establishment by EPSRC of

the National Centre of Excellence for Power Electronics, backed with £18million

of funding over the next six years.

EPSRC chief executive Professor David Delpy explained the move. “This

investment in a six year research initiative is part of EPSRC’s response to the

Government’s 2011 report. We will invest an initial tranche of £12m, with a

further £6m being released subject to a future

review of progress. Power Electronics was also a

priority area in our recent call for new Centres for

Doctoral Training.”

The investment will be made as a series of

grants, each bringing together a number of

universities. At the centre of the network will be a

coordinating hub, led by Professor Mark Johnson at

Nottingham University. There will also be four

technical programmes, addressing devices,

components, converters and drives. The hub and

programmes will bring together researchers from

the universities of Bristol, Greenwich, Imperial

College London, Manchester, Newcastle,

Nottingham, Sheffield, Strathclyde and Warwick.

PowerelectronicsUK has three workstreams

examining technology, skills and the supply chain.

The technology workstream is identifying and

prioritising technologies in order to develop a

opportunities focused roadmap. It has identified 42 technology areas which it

says are ‘critical’ to power electronics. The top 10 of these feature six

semiconductor related and four system related functions. Amongst the

semiconductor challenges are higher voltage devices and higher switching

frequencies.

Welcoming the establishment of the Centre, David Willetts, Minister for

Universities and Science, said: “We have a leading power electronics industry in

the UK, but we need to keep investing in research to ensure it remains globally

competitive. This National Centre will bring together our excellent universities

and businesses to ensure industry has access to the latest science and

technology, as well as helping to maintain a supply of skilled people.”

According to Alsthom UK’s Steve Burgin, chairman of PowerelectronicsUK:

“The EPSRC Centre for Power Electronics will be key to the future success of UK

power electronics. It will help to keep UK industry and academia at the forefront

of next generation power electronics technologies.”

EPSRC plugs into power sector£18m investment set to fuel six years of power electronics research.

Graham Pitcher reports.

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New Electronics, incorporating ElectronicEquipment News and Electronics News, ispublished twice monthly by Findlay Media Ltd, Hawley Mill, HawleyRoad, Dartford, Kent, DA2 7TJ

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ISSN 0047-9624Online ISSN 2049-2316

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News

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Nissan unveils ‘world’s fastest’ electric racing carDesigned to reach speeds of more than 300km/h, Nissan's ZEOD RC

is claimed to be the fastest electric racing car in the world. 52453

2. £3m project in the UK will bring

Star Trek Tricorder to life to enable

quick and portable medical

diagnostics 52458

3. ESCO Report targets 55%

growth in electronic systems

sector by 2020 52467

4. Significant drop in Q1

semiconductor inventory 52448

5. Graphene-based inks could

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6. Exciting times for M2M?

Survey shows 'dramatic change'

in geographic uptake. 52524

7. David Cameron backs scheme

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Graphene supercapacitors:

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Put female engineer on our bank

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Flash storage or disk drives:

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GaN set to play central role in

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Voice controlled applications

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Verifying fpga systems using

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1Advanced power devices for slimmer PSUsMore features packed into power

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Process high voltage inputlevels without losing SNRHow to minimise SNR loss when

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Read it here first – if it is relevant!

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8. Long range RFIC platform

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To read these items online, go to www.newelectronics.co.uk and type in the article number

1

Andy Pease

Andy Pease joined QuickLogic in November 2006 as vp of

worldwide sales and was promoted to president in 2009, then

appointed president and chief executive officer in January

2011.

Prior to joining Quicklogic, Pease was senior vice president of

worldwide sales for Broadcom and vp of sales for Syntricity.

From 1997 to 1999, he was vp of sales for Vantis. From 1984 to

1996, Pease was with AMD, where his last position was group

director, worldwide headquarters sales and operations.

Pease holds a BS degree from the United States Naval Academy

and an MS in computer science.

Interview Andy Pease

There is no doubt the programmable logic market is evolving, but

while the leading companies push towards the lowest process node,

QuickLogic is marching to the beat of a different drum. Its portfolio is

largely based on 180nm technology – although the latest ArcticLink III VX

is a 65nm part – but insists that is not holding the company back. It

distances itself further from Altera and Xilinx as it transitions from being

an fpga supplier to a supplier of customer specific standard products – or

cssps.

It is a risky strategy: cssps are targeted at price conscious mobile and

consumer markets, where margins are lower than those of fpgas. Pease

refused to be goaded when asked if there is still a place for assps. “Do you

know how large the programmable logic industry is? $3billion. The market

is growing and demand for assps are growing. I certainly agree that asics

are dead, but assps? Really?”

The company is transitioning from being a broad based fpga supplier.

Target markets are portable computing, smartphones and mobile internet

devices, as well as broadband data cards, mobile enterprise and personal

media players, and portable navigation devices.

“Here is a fundamental truth that we fight all the time – why do you

have fpgas?,” he asked. “Because they are flexible, but the cost is

obscenely high. The development cost for a 28nm chip may be

$20million. And here’s another truth they don’t talk about – it’s eye

popping the space it takes to put in a given function in programmable logic

versus putting it in a standard cell or assp technology.” Warming to his

theme, he issued a challenge: “What do you think the size penalty is?”

Without waiting for an answer, he declared: “You can put 10 times as much

in a standard cell as you can in programmable logic. The things we put into

a standard cell are things you cannot do in programmable logic; any

analogue or mixed signal, MIPI, USB – all need a standard cell component.”

Quicklogic put the full algorithm for VEE (Visual Enhancement Engine)

and DPO (Display Power Optimiser) in its ArcticLink chip; the earlier

PolarPro could only accommodate part of the algorithm. It also took x10

less space, leaving room for more fabric. Pease enthused: “We added a full

MTDI interface; we even put a frame buffer in the interface and the

resulting chip was smaller. The whole point of ArcticLink is to have some

programmable logic and, in the mobile space, we have to be very, very cost

effective.”

Pease knows programmable logic; he worked at Vantis, AMD’s

programmable logic spin off. He estimated that, in 2000, fpgas were 45% of

the programmable logic market. Today, he estimates 75 to 80%, dominated

now, as then, by Altera and Xilinx. So where does QuickLogic fit?

He whips a business card from his jacket’s inside pocket. It is from the

early days of the company and bears the Via Link logo, similar to the Jedec

symbol. “I keep this as a ‘show and tell’,” he confides. “Via Link [the

company’s metal to metal technology] is non reprogrammable; the rest of

the industry’s is reprogrammable. They have static ram cells – if you take

power from the static memory, the cell becomes blank.”

What could have been a technology that pigeonholed the company into

high end applications has become a differentiator. Just as the company was

pondering how it could take its programmable logic, which could differentiate

hardware, into a space where Altera and

Xilinx were not, ‘the mobile market

popped up’, said Pease. “The cool thing

about [it] is that every metal to metal

connection is a possibility. It is more

dense and, once you have made the

connection and turn off the power, the

connection is still there, so static power

is minuscule.

“With fpgas, you need code for the

algorithm to be stored in either a

separate on chip memory or on a

prom. But you need to boot these;

there is no instant on. That doesn’t

sound like mobile, does it? The

second problem is you always need to

apply power; when you remove power [from an fpga], it goes blank, ready

for reprogramming”.

Until QuickLogic, Pease points out, there was no programmable logic in

mobile devices, aside from small cplds selling for 25 to 50cents. The first

mobile design the company did was the Ultra Mobile PC for HTC.

The company is happy to be playing catch up in the process technology

game. “We can be two process nodes behind the leaders, but still be every

bit as dense and every bit as fast, because of Via Link technology”.

QuickLogic celebrates its 25th anniversary this year, six years after

introducing cssps. At the GlobalPress Electronics Summit 2013, Pease

outlined another evolution – catalog cssps. He described them as ‘a cssp

designed with a partner, to include in a reference design. It will help [the

partner] sell its product and we become part of the BoM for their

customer – which is why we call it ‘catalog’, rather than collaboration.”

The first catalog cssp is the CAMI/F and Camera Cape board for the

BeagleBone Camera Cape. This avoids using a USB port on the Texas

Instruments AM335x processor to control video data, saving a precious

port for other functions.

When asked about future catalog cssp developments with TI, Pease

became uncharacteristically guarded. “We showed them the display

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Maverick or visionary?Andy Pease tells Caroline Hayes his company’s focus on programmable logic

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On its cover, the ESCO Report asks its readers to ‘imagine a world

without electronic systems’. It’s not something which those who

produced the report can envisage. Instead, the report believes the

potential exists for the UK’s electronic systems sector to grow its revenues

by more than 50% over the next few years. The report – compiled by

industry leaders following some 18 months of research – also believes the

sector could sustain 1million jobs by 2020.

According to the research, the electronic systems (ES) sector currently

contributes £78billion to the UK’s economy and employs 850,000 people

directly and indirectly. Growing revenues to £120bn would place ES in the

top five industries in the UK.

Setting targets is one thing, achieving them is another. The report makes

several key recommendations, including improvements

to supply chains, better strategic procurement and

skills development. It also calls for a strategic ‘think

tank’ to identify future opportunities for the sector.

Failure to take action, it believes, will have implications

for the competitiveness of every industrial sector in the

UK and for the UK economy.

The ESCO initiative – with ESCO standing for

Electronic Systems: Challenges and Opportunities – was

chaired by Jamie Urquhart, a venture capitalist with

Pond Ventures and an erstwhile director of ARM.

When the initiative was announced in September

2011, Urquhart said it was an ‘interesting time to start

to stick things together’. Speaking to New Electronics at

the time, he said: “The UK has a broad spread of

companies which are invisible, but whose technology

appears in exciting products. The report gives the

opportunity to take a longer term view again.”

Now, almost two years later, what does Urquhart

think about the report? “It isn’t about the report,” he

contended. “The report is an outcome. But if the report is all that happens,

that’s not what I ‘signed up’ for.”

Somewhat dismissive of his role, Urquhart said: “These reports are easy to

write if you lock MBA students up in a room. The result will be 90% good and

full of relevant words. But if you ask whether this is a result, the answer is ‘no’;

that will come in a few year’s time when we start making a difference.”

The report was compiled from a number of workstreams (see box).

“When I’ve been involved in developing strategy,” Urquhart said, “it wasn’t

about locking yourself away in a room, then saying ‘this is what we do’. At

ARM, I involved as many people as possible; people who knew what was

going on, where we were and what the markets were. Importantly, they

helped us to decide where we wanted to be.


Designing thefuture

The Electronic Systems sector is already a vital contributor to the UK’s GDP. Can thatcontribution be grown by 50% by 2020 and employment increased?

The ESCO Report says ‘yes’. By Graham Pitcher.

“The ESCO process was more about trying to understand from our

constituency what is going on – not just because we wanted the information,

but also because it will help to make changes with the stakeholders.”

The report’s ‘top line’ recommendations are the economic and

employment targets. But how might these be attained? In his statement in

the report, Urquhart says the ESCO team will:

• Build recognition of this strategically important key enabling technology

sector.

• Accelerate growth in the UK vertical sectors as a result of the use of UK

Electronic Systems, and

• Develop and exploit UK Electronic Systems capabilities, nationally and

globally.

Building recognition

“The electronic systems industry is invisible and the electronic systems

themselves are invisible,” said Urquhart. “So our first challenge is to

motivate the various groups and to bring them together. This will make the

industry more cohesive. But this is just a first step; there has to be more.”

The report spells out the way forward, using inward (industry) and

outward (government and other bodies) facing approaches. Inward goals

will be to develop broad recognition of ESCO and support for its aims and

objectives. For the outward flow, the report recommends the development

of a well supported and connected UK Electronic Systems Leadership

Forum (ESLF). Working in partnership with government, the ESLF will lead

the implementation of the Action Plan and promote it across the ES

community, engage with the community by working through trade

associations and key stakeholders, who will be urged to commit resources

to support the Forum and the ESCO Action Plan.

It’s not the first time that a call has been made for the industry to unite

behind a common goal. In 2005, the Electronics Innovation and Growth

Team made a similar rallying call, but with little success. Is the ES sector a

herd of electronic cats or a supertanker to be turned? “It’s not so much a

supertanker,” said Urquhart, “more a flotilla of small ships. It’s like a school

of fish: they will act together. It’s one of the challenges and one of the

reasons the report took longer to produce than anticipated – we needed to

get ‘buy in’ from across the industry.”

Are there too many trade organisations to get this ‘sign up’? “Irrelevant,”

Urquhart asserted. “They are there for good reasons. We now have to work

amongst them, rather than saying we have too many.”

Accelerating growth

The report states ‘Leading companies provide the basis for strong

ecosystems. Using PowerElectronicsUK as a model, the Electronic Systems

community will develop ecosystems around strategic supply chain

development opportunities’.

The report sets out initial priorities as:

• Energy: the intelligence in the smart grid

• Healthcare: the heart of smart healthcare

• Transport: the hub of smart transport

The ESLF plans to build what it calls ‘strong relationships’ with key

Cover Story ESCO Report


Jamie Urquhart, chair,

ESCO Steering Group:

“My hope is that you –

whether in industry,

academia, government

or the wider public

sector – will engage in

driving delivery of the

Action Plan to ensure

the UK’s future as a

global leader in

innovation and deliver

growth.”

vertical sectors – such as aerospace, automotive and defence – in order to

ensure strategic alignment at the most senior level. This will be achieved via

‘sector focused ambassadors’, who will establish a dialogue with their

counterparts in the key sectors and identify strategic supply chain

development opportunities that could bring ES R&D and manufacturing to

the UK.

Urquhart noted: “It used to be about vertical companies, such as Plessey,

which would do everything. While society and government still think about

vertical companies, the world has changed. There are now laminar strips of

capability across multiple industries. We need to understand and highlight

the fact that some capabilities cross all industries.”

He pointed out that ES is an enabling technology. “It’s not about

companies like ARM,” he contended, “it’s about whether we can build

systems of the future. It’s a strategic capability. The UK has a knowledge

economy, so there has to be strategic underpinning.”

Developing and exploiting

The ESCO report calls for UK industry to develop a global outlook, for the UK

to develop companies ‘of scale’ and for it to develop ‘smart skills’ and ‘smart

partnerships’.

The goal, says the report, is to ensure that UK industry and academia

create ‘great’ new technology whilst striving for greater UK led exploitation

and increasing exports. It calls for a concrete action plan to ensure the ES

community and its capabilities is ‘properly represented’.

It also wants to see more UK companies with globally dominant,

consumer facing brands. “The world has changed dramatically,” Urquhart

said, “but we all take it for granted. That’s dangerous and it means we fail to

invest. We have an industry with a small number of larger companies, but

not by international standards, and that’s a problem.”

He pointed to the benefits of DARPA in the US – ‘a significant driver’ – and

of similar initiatives in Taiwan and Korea. “I’m not arguing for top down

control,” he explained, “but government involvement is important, because it

acts as a catalyst. However, it’s important that we shouldn’t think only about

electronics; it’s as much about motivating industry to work with those in

other sectors who use electronics and it’s about working with government.”

When it comes to skills, the report notes there is a real need to increase

the number of bright young people considering careers in the ES

Community and a particular opportunity to address the gender imbalance.

The industry needs to increase coordinated activity reviewing ways to

‘inform and excite’ young people about working in the industry.

“We need to make ES an easy career choice,” Urquhart asserted, “and we

need to make sure we have enough ES engineers to go around as we

increase dependence on ES in the future.”

Will it work?

Urquhart says he has seen more engagement over the last couple of years,

with more passion from companies and a desire to reach out across

industry. “If you have strategic focus, it’s easier to get them to work

together,” he believes. “It’s about alignments; about many incremental

improvements. That’s where we are today, but we need to align a bunch of

things and to make people aware of why it matters. We have a strategic

direction with goals and we will build a team which will help to deliver them.

Together, it will make a difference.

“There are statements and predictions in the report; will they all come

true? Not all of them,” Urquhart concluded. “Will the report put us on a

better path? I hope so.”

• For more on the ESCO report, go to www.esco.org.uk


Cover Story ESCO Report

Warren East, chair, Electronic

Systems Leadership Forum:

“Today’s ES products are truly

children of the world, the offspring of

global enterprise; and tomorrow’s

products will be even more so. For

the UK to be genuinely successful,

we need decision makers who have

genuine understanding of the levels

of complexity within technology,

supply chains, business models and

global partnerships that represent

the way ES businesses operate.”

Sir Hossein Yassaie, ceo,

Imagination Technologies:

“The UK has many highly successful

ES businesses, but we need ‘scale’

to overcome the rising costs of

design and manufacture if we are to

be profitable. More can be done to

help UK businesses develop strong

roots locally to enhance their

international ambitions.”

ESCO methodology

The ESCO report drew on the findings from a number of Working Groups,

commissioned to focus in more detail on specific areas relevant to the

community.

• Workstream 1: Economic footprint of the UK Electronic Systems

community

• Workstream 2: Research, development and Intellectual Property

creation

• Workstream 3: Innovation climate

• Workstream 4: Manufacturing

• Workstream 5: Skills – supply, demand, provision and gaps

Each workstream focused on the collection and processing of relevant

information and the direct engagement of representative stakeholders.

A series of consultations took place across the UK to validate suggested

actions and to gather further information.

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www.eurekamagazine.co.uk July 2013

In this issue: Sensors, Test & Measurement • Rapid Prototyping • Power Transmission • Defence

RealitycheckMeeting the challenges of virtual design

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Whatever the problem, or quest for

improvement, with image processing,

the trend is to try and find solutions in

software. The problem is that software

complexity turns graphics processors into power

hungry beasts.

Rahul Ridhe, a graduate student at MIT, is

working towards his thesis looking at efficient

systems for portable multimedia processing. He

is one of the team that has developed a chip that

enable huge strides in photograph and video

quality.

“The processor that we have built is equally

applicable to any energy-constrained devices,”

commented Ridhe. “Smartphones and cameras

are great examples, but it could also apply to

tablet computers or even laptops. What this chip

offers is real time functionality while offering

extremely low power compared to your

smartphone or laptop processor. For example, if

you are trying to do high dynamic range imaging

on your laptop computer, it currently uses several

Watts. With this new chip, you can do that with a

few milliWatts – the energy reduction is more

than 1000 times. So this chip can be used for all

kinds of battery constrained devices.”

Such improvements in energy efficiency

result from real-time image processing in

hardware, rather than using software. Equally,

the new chip adds functionality to the camera,

allowing photographic applications such as

lightfield photography, in which pictures can be

‘created’ in difficult lighting conditions that would

not have been possible with a traditional camera

(see left). The principal technique is bilateral

filtering, which opens the door to a range of

applications, including High Dynamic Range

(HDR) imaging, Low Light Enhanced (LLE)

imaging, tone management and video

enhancement.

There are two techniques for creating

pictures using HDR. The first involves taking a

number of pictures – typically three – virtually

instantaneously using a regulation camera. The

second option – soon be available in some new

digital cameras – is to use three sensors to take

the three pictures instantaneously. In either

case, one picture captures a normal shot, one

Little energy forperfect pixelsGetting the right light balance in pictures can be tricky,but a new chip could make expert photographers of us all.By Tim Fryer.


Sector Focus Sensors

captures the brightest parts of the shot and the

other the darkest. Each of these pictures has a

low dynamic range, but a single HDR image can

be obtained by combining them – and this is

what the MIT chip, nicknamed Maxwell, can do.

Maxwell was named after Scottish scientist

James Clerk Maxwell. Maxwell was prolific in his

scientific and engineering output – his work on

electromagnetism was of huge importance to

the modern world. But he also developed the first

technique for creating colour photography. His

trichromatic process split a picture into three

images using red, green and blue filters, then

recombined them in a single image. And this is

the same fundamental concept used by Rihde for

the image processing chip, hence the tribute.

Maxwell (shown right) is an asic built using

TSMCs 40nm cmos technology. Rihde

commented: “The chip was developed by us

completely, but TSMC has a University Shuttle

Programme that allows universities to fabricate

their ICs. Foxconn provided funding for the project.

We had discussions during the project with them

and had some feedback during the design

process, but the development was done by MIT.”

The test chip is verified to be operational from

25MHz at 0.5V to 98MHz at 0.9V. It is designed

to function as an accelerator core as part of a

larger microprocessor system, using the

system’s existing dram resources. For

standalone testing of this chip a 32bit wide

266MHz DDR2 memory controller was

implemented using a Xilinx XC5VLX50 fpga.

In tests that compare the runtime for a

10Mpixel image with gpu/cpu implementations

of C++ code, that replicates the functionality of

the testchip, the processor achieves an x15

reduction in run time compared to the cpu

implementation, while consuming 17.8mW, a

significant reduction compared to previous cpu

or gpu implementations.

Bilateral filtering is a non iterative process

for smoothing images, while still preserving

edge integrity. Rihde noted: “In this work, we

implement bilateral filtering using a

reconfigurable grid, which reduces the storage

requirement to 21.5kbyte [compared to

65Mbyte for a 10Mpixel image using software

filtering] by scheduling the filtering engine so

that only two grid rows need to be stored at a

time. The implementation is flexible to allow

varying grid sizes for energy/resolution scalable

image processing.

“The reconfigurable filtering engine performs

HDR imaging, LLE imaging and glare reduction.

The filtering engine can also be accessed from

off chip and used by other applications. The

implementation accelerates bilateral filtering

significantly and enables various edge aware

image processing applications in real time on

HD images. The testchip can also process a

10Mpixel image in 771ms with 17.8mW power

consumption while operating at 98MHz/0.9V.”

The testchip contains two bilateral filter

engines, each processing 4pixel/cycle.

Displaying HDR images on LDR media requires

tone mapping that compresses image dynamic

range by non linear filtering. A tone mapped HDR

image is created by bilaterally filtering HDR

intensity values in the log domain, followed by

contrast reduction. In HDR mode, both bilateral

grids are configured to perform filtering in an

interleaved manner, where each grid processes

alternate blocks in parallel. Glare reduction is

similar to performing single image tone

mapping and is integrated with the HDR

architecture. LLE imaging is performed by

merging two images captured in quick

succession, one taken without flash and one

with flash. The bilateral grid is used to

decompose both images into base and detail

layers. In this mode, one grid is configured to

perform bilateral filtering on the non flash image

and the other to perform cross bilateral filtering

on the flash image using the non flash image.

There is no critical lower limit to the picture –

if the picture is very small, there won’t be any

detail in it and changes will not be detectable.

On the higher side, the processor can handle up

to 16Mpixels.

Although Maxwell is currently operated and

tested through a laptop (see main image), its

value will not be realised until it can be designed

into the new breed of camera bearing devices.

While suited to the digital SLRs featuring the

triple sensors mentioned above, a more

important target could be smartphones, where

battery life is emerging as a more important

battleground parameter than functionality.

But would a camera featuring Maxwell appeal

to everyone? Photographers may feel that this

level of processing would remove the skill in

taking good photographs and remove some of

the effects that would have been deliberately

introduced. Not so, according to Ridhe: “The

functionality can be enabled – it doesn’t always

have to be used. You don’t want to be too

prescriptive. You could enable the functionality

and see the results in real-time as you would an

ordinary picture. The real time performance

allows you to apply these techniques to video as

well. So if you were shooting a video with a

DSLR, you can do a high dynamic range video by

using the chip as it will process the frames in

real time. That is another advantage of having a

dedicated processor rather than doing it on a

computer or doing it on a general purpose

processor.”


Dr Sian Fogden was a researcher

at Imperial College, studying

nanotubes for her PhD, when

Linde Electronics became interested in

her work. Now Linde Nanomaterials,

part of Linde Electronics, is pursuing

this line of work in California with Dr

Fogden at the helm. The resulting

product, a nanotube ink, was launched

at NT13 – the international nanotube

conference held in Helsinki in the

closing days of June 2013.

Dr Fogden is clearly a fan of carbon

nanotubes: “Nanotubes is have amazing

electrical, mechanical and physical

properties. They are stronger than steel.

They are more conductive than copper

and they are the world’s best heat

conductor.”

Unsurprisingly, they therefore lend

themselves to a huge range of

applications, one of which is in sensors.

Carbon nanotubes are simply very

long, very thin tubes of carbon atoms –

like a sheet of graphene (or chicken

wire) rolled up – so they have a huge

surface area. Nanotubes are made from

a naturally occurring allotrope of

carbon. Their large surface area aids

which are used now. You can measure at

the very low parts per million for

example for some gases and obviously

that has huge benefits for the sensing

industry.”

To turn these nanotubes into an ink

– a useable solution – is not difficult,

but Linde has developed a process to

ensure that it does it well. Because

nanotubes are long and thin, they have

high van der Waals forces between

them and they stick together. The

sensitivity, while the interaction of a

molecule with a nanotube greatly

affects the conductivity, hence the

suitability for nanotubes as a sensing

device.

Some gases react strongly with the

nanotubes, while others require

functionalisation. “Nanotubes are very

pure structures with just pure carbon in

the hexagon structure,” explained Dr

Fogden. “To functionalise it, you just

choose a chemical group that would

interact strongly with the molecule you

want to sense and attach it to the

outside of the carbon nanotube. So you

break one of the bonds in the nanotube

structure and attach it to the molecule

of the substance that will interact

strongly with the molecule you want to

sense.”

Sensing any substance

Essentially, this means that any

substance can be sensed with a carbon

nanotube sensor, as long as it has an

identifiable chemical that it can react

with.

“Depending on what atoms react

with the carbon nanotube, sometimes

they become more conductive and

sometimes less,” Dr Fogden

continued. “You can

measure very low

concentrations. In fact

one of the very good

reasons for using carbon

nanotubes for sensors is

that they are much more

sensitive than the materials

Ink draws on negative chargeNanotechnology continues to hover around the real world, generally as a misused term forsomething in existence that is merely ‘very small’, or in areas where commercial exploitationremains tantalisingly just round the corner. Using carbon nanotubes for sensors falls intothe latter category – but it may be about to reach the realisation stage, as Tim Fryer reports.


“Manotubes haveamazing electrical,mechanical and physicalproperties. They canalso sense in liquids andgases.” Dr Sian Fogden

Nanotubes dissolve

spontaneously in

certain organic

solvents to form a

printable ink

Sector Focus Sensors

standard way to separate them is by

sonication – high powered sound

waves. This has the effect of creating

minute explosions within the solution,

which can damage the nanotubes and

affect their properties.

Dr Fogden commented: “With our

inks, we use a very specific process

that doesn’t require sonication but

which produces solutions of individual

nanotubes that maintains the length of

the nanotube that you put in in the first

place – however long it is as a raw

material is the length that it is in our ink.

The process we use to make our inks is

called SEER – Salt Enhanced

Electrostatic Repulsion. All that that

means is that we add an electron to the

nanotube and because negative

charges repel, the nanotubes repel each

other. It is a very simple idea.”

To charge the nanotubes negatively,

an alkaline metal, like sodium, is added

to liquid ammonia containing

nanotubes. When this turns blue, the

outer electron in the sodium has joined

the nanotube, giving it its negative

charge. Removing the ammonia leaves a

salt of negatively charged nanotubes,

which in turn dissolves spontaneously

in certain organic solvents to form the

ink – the product that is now being

released by Linde. This ink can easily be

functionalised to create the desired

sensor and can be deposited by

printing, spraying or any other regular

method of dispensing a liquid.

Applications for carbon nanotubes

are many and varied and include solar

cells and displays, particularly flexible

touch screen displays. However, even

within the sensor arena, there are many

possibilities. Carbon nanotubes are a

promising material for gas sensors

because they have high sensitivity at

room temperature. They have been

used to sense a range of gas molecules

including: nitric oxide, with the hope of

providing real time asthma monitoring

by measuring the NO content in breath;

ammonia, a toxic chemical used in the

chemical and food industry and whose

current sensors have problem with

sensitivity; ethylene, a chemical

released when fruit ripens so could be

used to help supermarkets manage fruit

shipments; and NO2, CO, CO2 and H2, all

of which could be used to produce fire

gas sensors to increase the speed and

reliability of fire detection.

“One of the unique things about

nanotubes is that you can sense in both

liquids and gases,” Dr Fogden continued.

“So they can be used as biosensors, for

example to test glucose from saliva to

help diabetics to keep better check on

their blood sugar levels without having

to do a pin prick.”


Carbon nanotubes –

long, thin rolled up

tubes of carbon atoms

– have a huge surface

area. This large area

enhances sensitivity

Seeing sense from service provider

One sensor offering comes from what is perhaps an unexpected quarter, given that Sanmina is primarily a

service company. It offers custom optical design solutions and manufacturing services from passive and

active optical devices, high speed optical modules and circuit packs to end-to-end optical system solutions.

Jose Descoteaux, director of design engineering services at Sanmina, commented: “Customers not only

want the optical sensors to meet performance specifications, but also want them to be reliable and

manufacturable with shorter time to market.”

The types of products in which Sanmina specialises are not at the commodity end of the market. “The

optical products Sanmina designs are usually with leading edge technologies, such as 100Gbit/s DP-QPSK

modulator, 4x25Gbit/s Transmitter Optical Subassembly and compact Optical Coherence Tomography,” said

Descoteaux. “For optical sensors, there are standard technologies that can be fairly easily customised for

particular applications, but they are getting more sophisticated for advanced applications, and when

customers come to us, the optical sensors are usually a combination of leading edge technologies in

wavelength discrimination, light routing and optical property manipulating, signal detection, and

packaging.”

Fibre optical sensors have some well-known advantages, such as EMI immunity, small size, good erosion

resistance, long term reliability, direct absolute measurement, and wavelength multiplexing capability.

Descoteaux continued: “These characteristic advantages of optical sensors enable them to be used in a

variety of ways like monitoring power line loading or fault detection, and metering where electrical

counterparts cannot perform well.”

The Double Data Rate (DDR) interface, which

transfers data at the rising and falling

edges of the clock signal, has been used in

a range of applications. In each cycle, the data is

sampled at the clock’s rising and falling edges

and the maximum data frequency is typically

twice the clock frequency.

The trend is toward higher data rates and

lower voltages. For a system to function

accurately, its signal integrity performance has to

be optimised and must meet certain minimum

requirements. Although DDR2 and DDR3 are not

as fast as a Serial Link interface, the signal

integrity issues are challenging and will be

greater for DDR4. This is due to the parallel versus

serial nature of these interfaces. Signal integrity

concerns, such as crosstalk, jitter, power supply

noise and reflections, are dominant for parallel

interfaces and increase with data rate.

With the shift toward DDR3 and higher data

rates, the period during which data can be

sampled reliably (the data valid window) shrinks

steadily and sensitivity to signal integrity issues

increases dramatically. The package becomes an

important consideration at these high data rates,

especially with respect to the chip interconnect

method. The current IDT DDR3 package is

configured to be a wirebond die, but there are

benefits in changing to a flip-chip type and the

performance benefits are outlined below.

DDR interface challenges

First generation DDR interfaces were designed

for a maximum rate of 400Mtransfer/s, with the

respective bit period or unit interval (UI) of

2.5ns. These interfaces typically used a 2.5V

power supply. Current DDR3 interfaces run at

1600Mtransfer/s, with DDR4 based systems

expected to run at 3200Mtransfer/s. At that rate,

each UI is about 312.5ps, with the power supply

dropping to 1.2V.

Some of the challenges encountered include:

• Shrinking bit period. This brings a shorter

setup and hold time window, making it harder to

meet timing between clock and data signals

• Fast signal edges. Shrinking bit periods mean

sharper signal edges, exacerbating crosstalk and

power supply noise performance

• Lower voltages. For a 2.5V supply, a 5% noise

tolerance results in a maximum acceptable level

of noise of 125mV. For a 1.2V supply, a 5%

tolerance translates into 60mV of acceptable

noise. Interconnect design and selection

therefore becomes critical.

Packages are a critical component of the total

system interconnect and a sub optimal selection

can degrade device performance significantly.

Today, IDT’s DDR3 devices use wirebonds to

connect the chip to the package substrate. The

3d nature of the wirebonds makes controlling

the electromagnetic fields emanating from

aggressor signals difficult to manage.

Wirebonds, in general, are inductive and the

mutual inductance between two neighbouring

wires is a major contributor of signal to signal

crosstalk. Inductive wirebonds also cause the

power supply impedance to increase, resulting in

more power supply noise at the chip.

Converting to a flip-chip package will

eliminate a key source of signal integrity

concerns without impacting the overall package

form factor (see fig 1).

Understanding crosstalk

Crosstalk is caused by the leakage of

electromagnetic signal energy from one

conductor to another through mutual

capacitance (electric field coupling) and mutual

inductance (magnetic field coupling).

• Capacitive crosstalk

In a victim-aggressor situation, capacitive

crosstalk injects current from the aggressor line

onto the victim line, with the magnitude of

crosstalk proportional to the rate of change of

voltage and the amount of mutual capacitance

between the two lines. The injected energy will

split and flow toward both ends of the victim line

– both ends being near end (close to the driver

side) and far end (close to the receiver side).

Packaging pushesperformanceHow the bandwidth of DDR applications can be extended by changingfrom wirebond to flip-chip packages. By Jitesh Shah.


Fig 1. Cross section of two chip to package interconnect types

Wirebond Flip chip

Research & Development Digital Design

• Inductive crosstalk

Crosstalk due to mutual inductive coupling

induces a voltage on the victim line proportional

to the rate of change of current on the driven line

and the magnitude of mutual inductance

between the two conductors. The current due to

the induced voltage flows in the opposite

direction of the driven line from the far end to the

near end (based on Lenz’ law).

In substrate based packages, there are two

crosstalk components: crosstalk in the

transmission line section of the package

interconnect; and crosstalk in the 3d structures,

such as vias, wirebonds and solder balls. In the

transmission line section, crosstalk is

predominantly electromagnetic; in the 3d

section, it is mostly inductive. For most

packaging applications, far end crosstalk is

usually negative, identifying inductive crosstalk

emanating from the 3d sections of the package

as the dominant mechanism.

With the wirebonds eliminated (mutual

inductance reduced), the flip-chip version of the

package shows less far end crosstalk than the

wirebond version (see fig 2).

Crosstalk effects on modal delays

The flight time of a signal through a conductor

depends on how neighbouring coupled

conductors switch. This difference in flight time

gets exacerbated as crosstalk increases. In a

multiconductor system, there are three possible

switching modes: quiet mode; odd mode; and

even mode.

• Quiet mode: Where the rise and fall times of the

victim signal do not coincide with the

neighbouring coupled aggressors or when the

victim signal is held quiet.

• Odd mode: Where the rise and fall times of

neighbouring, coupled aggressors coincide with

the victim signal and where the aggressors are

switching 180° out of phase with the switching

signal.

• Even mode: When the neighbouring aggressors

switch in the same phase as the victim signal and

at the same time.

In a coupled system, a signal experiencing

odd mode switching arrives at the receiver first,

followed by the quiet mode signal and then the

even mode signal. This spread in flight time in an

I/O bank increases with crosstalk. In a DDR type

system, where a common clock samples multiple

parallel signal bits, this spread in crosstalk

induced skew can have a detrimental impact on

the setup and hold time window available for

proper clocking. As data rate increases with the

associated shrinkage in UI, reducing crosstalk to

improve setup hold time windows will become

paramount.

Fig 3 compares the modal delay spreads of

the two packages. Wirebond delay is more spread

out, with a total modal delay spread of 41ps,

compared to 15ps for the flip-chip variation. With

the UI for DDR4 applications expected to be half

that of DDR3, this increase in package skew will

make timing extremely challenging and flip-chip

will be a preferred interconnect option.

Power delivery

Delivering power to the chip efficiently requires

a reduction in the input impedance of the power

delivery network looking out from the chip

power and ground nodes. Package type and the

chip to package substrate interconnect

technology are critical components of this

network. Package impedance is largely a

function of the loop area formed by the power

and ground interconnects and the type of chip

to package interconnect method used.

Eliminating wirebonds from this loop reduces

loop inductance – and hence impedance – by

more than 50%, with a resultant drop in power

supply noise at the chip.

Author profile:

Jitesh Shah is a principal engineer with

Integrated Device Technology.


Fig 2. Crosstalk on victim with aggressors switching

Wirebond

Cros

stal

k (r

elat

ive)

1.2

1.0

0.8

0.6

0.4

0.22 3 4 510

Time (ns)

Flip chip

Fig 3. Modal delay spreads of the two package types

Odd mode

Wirebond Flip flop

Quiet mode Even mode

There are few products on the market

today which rely on disposable alkaline

batteries for their power. Instead,

designers are specifying lithium-ion batteries

in various formats. But the general trend is for

products to get smaller and for users to not

only expect longer times between charges, but

also a faster charging process. These demands

are pushing battery charging product

developers to adopt more innovative

approaches.

Patrick Heyer, battery charging product line

manager for Texas Instruments, pointed to

three charging approaches. “There’s ‘run of the

mill’, including USB and adaptors, which is still

developing, with new USB standards and

charging interfaces. Then there’s wireless

charging, with a charge management ic on the

receiver side, a device which could also be a

direct charger. Finally, there’s anything related

to energy harvesting. It’s an emerging area

that’s not as visible as the others but which is

clearly important.”

While TI is interested in all three areas, its

recent focus has been on what Heyer called

the ‘run of the mill’. But the technologies being

applied are far from mundane.

“What we see happening is being driven by

smartphones and tablets,” said Heyer, “where

there’s a need for higher charge currents. There

are also new charge sources, including USB PD,

which allows higher power levels to be

delivered over USB, although with a new

connector.” He added that USB will, in the

future, support voltages of more than 5V and

currents greater than 500mA.

TI recently introduced two power

management chipsets featuring MaxLife

technology, which allows single cell Li-ion

batteries to charged more quickly and to

provide longer life. The bq27530 and bq27531

fuel gauge circuits, when coupled with the

bq2416x and bq2419x chargers, optimise

battery performance by using the highest

possible charge rates with minimal battery

degradation.

“We want to take care of the battery,” said

Heyer. “Trying to put too much current into the

battery isn’t good and charging has to be

controlled. That’s where MaxLife comes in.”

MaxLife combines a fuel gauge, which

gathers information about the battery’s

condition, with the power stage, which puts

energy into the battery. “That’s a new

approach,” Heyer claimed. “Before, these

processes would be separate, regardless of the

battery’s state.”

Heyer said fuel gauges have a lot of

information about batteries. “They can be used

to determine warranty claims,” he noted.

“What’s new is making more use of the data.”

By controlling charging

based on the battery’s

condition helps to extend its

life. Parameters being

monitored include how old the

battery is, the number of

charge/discharge cycles it has

endured, current in and out and

its temperature. “The fuel gauge

also measures battery

impedance,” Heyer pointed out. “If it

sees problems, then the power stage

won’t use a full charge current.

Instead, it’ll use something more

gentle.”

Using the information collected, the

fuel gauge control charger modifies the

charge profile. “It doesn’t go with a


Charging is conditionalSmaller products and demand for faster charging are providing the

momentum for changes in battery charging technology. By Graham Pitcher.

Fig 1. A typical battery charging application

System load

VBUS

AC adaptor orwireless power

i2c

i2c

Applicationprocessor

Single cell Li-ion battery pack

T

P+

Protectionic

P–

FETsSOCINT

Temperature sense

Current sense

Voltage sense

SWIN

USB

D+

D–

SYS

BAT

PGND

BQ2416x

BQ27350-G1

constant current,” Heyer explained.

“Predefined charging profiles are adjusted in

real time to take account of the battery’s

condition. This extends battery life, which is

important in devices where the battery cannot

be removed.”

The devices also feature new charging

algorithms, which Heyer said have been

developed ‘over time’. “It’s a variation of

constant current and constant voltage

charging adjusted to the state of the battery,

improving overall system performance.”

Looking to the future, Heyer expects charge

currents to increase, which will mean

efficiency concerns will need to be addressed.

“How can we make high current chargers more

efficient and compatible with new charging

sources?” he asked.

In fig 1, the bq27530-G1 predicts the

battery capacity and other operational

characteristics of a lithium-ion rechargeable

cell. The bq27530-G1 can control a bq2416x

charger ic without the intervention from an

application system processor. Using the

bq27530-G1 and bq2416x chipset, batteries

can be charged with the typical constant

current, constant voltage profile or through a

multilevel charging algorithm.

The bq27530-G1’s performance is

underpinned by the proprietary Impedance

Track algorithm. This uses cell measurements,

characteristics and properties to create state of

charge predictions that can achieve less than

1% error across a wide variety of

operating conditions and over the

lifetime of the battery.

While the bq27530-G1and the

bq2416x support charge currents

of up to 2.5A, the bq27531 and

bq24192 chipset provides for charge

currents of up to 4.5A.

Heyer also believes the fuel

gauge/charger combo can provide

better performance than can be

obtained from a power management

ic (pmic). “A pmic has dc/dc

converters, a battery charger and

so on. It gets hot and if pcb space is limited, it

may be placed directly opposite an apps

processor. That creates thermal issues and the

system may have to power down so it doesn’t

overheat.

“We suggest taking some of the battery

management and high current charging devices

and putting them closer to the battery. You get

a better distributed system with information

based charging.”

Pressure on process technology

Supporting such devices places pressure on

process technology. “We need to develop these

parts for a process that can create FETs with a

low Rds(on),” said Heyer, “as well as one which

can combine digital. A charger isn’t just analogue

and some big power FETs any longer. There’s a

sizeable digital content to control the charging

loop and to handle the communications

interfaces.

“We need higher digital density, but we can’t

compromise on power performance,” he

continued. “We also need higher voltage

capability because input voltages are rising; you

can’t get away with a 5V process anymore and

that demands silicon performance.”

Despite the development of such technology,

Heyer said demand remains strong for simple

linear battery charging solutions. “Expensive

gadgets that used to work from alkaline batteries

have moved to small capacity rechargeable Li-

ion cells,” he said. “But their price points haven’t

changed, which means expensive charging

components can’t be used and that benefits

linear chipsets.”

This requires TI to work at both ends of the

spectrum, he noted. “At the high end, we’re

working on efficient thermal performance. At the

low end, we’re looking to meet system cost

requirements. We’re now selling Li-ion charging

solutions into the toys market,” he concluded,

“which is one of the most cost sensitive markets

there is.”

Maxim Integrated Products is samplingthe MAX77301 Li+ battery charger,which integrates the intelligencerequired to enumerate with the hostdevice, identify the adapter typeautomatically and determine thefastest rate to charge a battery. Withtemperature monitoring features, theMAX77301 modulates the chargecurrent and battery regulation voltageautomatically to maximise safety.

To enhance battery safety, theMAX77301 solves sets charge parameters at a safe level automatically. It also provides fullprogrammability via an i2c interface.

“The MAX77301 is a perfect fit for devices that do not have application processors but which needto charge quickly,” said Sam Toba, director of Maxim’s mobility business management division. “This includes cameras, Bluetooth headsets and medical devices.”

Automatic enumeration for safe charging

Embedded Design Power


The bq27531 evaluation

module has a bq27531-G1 fuel gauge that

communicates with the bq24192 single cell Li-ion

battery charger via an i2c interface.

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www.linde-gas.com/electronics

Innovating nanomaterials. High performance nanocarbon for high-tech electronic designs.

Communications Design Processors

The volume of data being transmitted around

the globe is reaching staggering levels –

and we ‘ain’t seen nothing yet’, according to

leading players in the sector. Dealing with this

traffic, while maintaining low power consumption,

is pushing device developers to create ever more

complex comms processors.

Two of the leading companies in the field are

Broadcom and Cavium Networks and both have

recently launched devices that pack large

numbers of processor cores onto smaller pieces

of silicon. Their products are looking to provide

high levels of processing capacity for

applications ranging from networking to the

home. The difference between the two is that one

has chosen to base its latest products on

multicore ARM processors, the other is – at least

for the moment – using MIPS cores.

Broadcom is the company taking the ARM

route for its StrataGX range. Ed Doe, associate

director for the company’s infrastructure and

network group, said: “Target markets are

anything from home applications to the

enterprise, including switching control plane and

routers.”

The StrataGX family includes a number of

series and Broadcom’s latest products are in the

58000 series, comprising the 100, 300, 500 and

600 lines. The latest announcements are in the

500 and 600 lines. Where the 100 series

features Cortex-M3 based products, the 500 and

600 series are multicore parts, mostly dual core

Cortex-A9.

Doe said: “Essentially, the new products are

the third generation of a range announced only

in 2012. Originally, the products were aimed at

the home, but we have expanded into the higher

end, where you need more performance and

more acceleration.”

Venkat Sundaresan, associate director of

product line marketing in Cavium’s infrastructure

processor group, pointed out that, alongside the

volume of data, operators needed to apply

security, “...things like deep packet inspection

and intrusion detection,” he said. “There are a lot

of applications passing through the network.

Systems can’t look at headers and make a

decision; they have to do payload inspection. But

packets are fragmented and need to be

reassembled. Only then can you start parsing

the payload.”

Both companies are not only developing

multicore processors, they are also integrating

offload engines for specific tasks. In Broadcom’s

case, this is through FlexSPARX, a Cortex-R5

based acceleration engine. The Cortex-R5 is

designed to support real time applications in

applications such as mobile baseband,

automotive and mass storage. The R5 has its

own local memory and can be used for RAID/XOR

acceleration, CAPWAP/DTLS and other network

protocols. “Switch control needs more

acceleration,” said Doe. He pointed out the

design didn’t need an R5. “However, the R5 core

is more efficient for some tasks than it is to use

one of the A9 cores. It’s more power efficient and

sometimes it makes sense to hard code.”

Sundaresan noted a similar approach by

Cavium, pointing to deep packet inspection and

packet processing engines sitting alongside

the MIPS cores. “We include offload engines,

such as deep packet inspection. This allows

users to specify rules which say ‘look for this

kind of traffic’.”

Many core magiciansMany core solutions are being developed to meet demands of those designing

communications infrastructure equipment. By Graham Pitcher.

9 July 2013

Fig 1. Block diagram of the OCTEON III CN70XX processor

Power minmanagement

Authentik CN70XX, with up to four cores

MIPS64r3 core

Floating point

Cryptosecurity

Packet

78kbyte I cache

32kbyte D cache

3kbyte write buffer

MIPS64r3 core

Floating point

Cryptosecurity

Packet

78kbyte I cache

32kbyte D cache

3kbyte write buffer

Sec vault

RAID

Packetprocessor

SATA 3.0PCIeGbE

10GbEUSB 3.0

Elasticpacket

buffers forthousands

of flows

NANDTDMSPI

eMMC

Deep packetinspection

Hardwareload

balancerunit

512kbyte coherentL2 cache

Fully cpu and I/O coherent high speed interconnect

Hyper Accessmemory

controller

Up to 8Gbyte ofoff chip memory

31www.newelectronics.co.uk

Communications Design Processors

Common between the two companies is the

wide range of applications for their processors. In

Cavium’s case, the Octeon range is being used in

wireless routers at one end and in advanced

network equipment at the other. Broadcom notes

a similar spread. One of the drivers is the

emergence of IEEE802.11ac routers, not only in

enterprise applications, but also in the home.

Sundaresan said: “11ac and 11n need 1.7Gbit/s

processing and Ethernet is being replaced by Wi-

Fi in some instances. Alongside the processing

load, these links need to be secure, so the

processors have to run IPSec at 1.7Gbit/s.”

In Doe’s opinion: “A typical router will use a

processor next to two radios – either 11ac or

11n. Going forward, we’ve made the processors

pin compatible, so users can upgrade to a higher

performance device if they need to.”

Broadcom describes its StrataGX BCM58522

processor as the ‘World’s most highly integrated

processor SoC for 5G Wi-Fi enterprise access

points’. The device has been designed to work

with 11ac communications, which the company

calls 5G Wi-Fi. Alongside offering high

performance Wi-Fi, the device also caters for the

growing demand for BYOD – bring your own

device. With people looking to link their own

smartphones into corporate networks, there is

the need for higher levels of security and

Broadcom claims the 58522 allows the creation

of secure, application aware unified wired and

wireless enterprise networks.

Sundaresan highlighted some of the threats

that need to be countered by such devices as

Octeon processors. “Alongside BYOD, there are

vulnerable hot spots and evil twin Wi-Fi attacks.

Corporate and personal data is becoming muddled

and networks now need prevention at the edge.”

He also pointed that enterprise style features are

now being seen in systems designed for the home.

With this trend to integrate ever more

features, process technology has become an

important driver for comms processor

developers. Cavium is moving to a 28nm

technology for Octeon III parts. The Octeon

CN50xx range was launched on a 90nm

process, with single and dual MIPS cores

running at 0.7GHz. Now, it’s releasing the

Octeon CN70/71xx range on a 28nm

process. With up to four cores running at

1.6GHz, the parts have five times the

throughput of the original devices.

It’s not just about integration and processing

power; there is also a move to offer developers

the opportunity to trade computing power against

power consumption. Octeon III parts offer three

times the performance of Octeon II devices, but

consume the same power. Developers therefore

have the choice of more performance for the

same power or the same performance for much

less power consumption. Sundaresan gave one

reason. “Access points are often located in harsh

environments, so the processor needs to be

thermally efficient; offering high performance,

but drawing low power.”

What next?

One thing is certain: the demands being placed

on such devices will only increase. So what plans

do the companies have for their comms

processors?

Cavium has plans to launch processors with

significant numbers of cores. Although initial

CN7xxx parts have up to four cores, the range

will expand to offer devices with up to 48

cnMIPS64 III cores, more than 500 application

acceleration engines, including high

performance search processing. “While we are

supports MIPS cores,” Sundaresan noted, “we are

also developing ARM based devices.”

Broadcom’s Doe said the company had been

working with ARM for a while, but it had recently

announced the acquisition of a v7 and v8

architecture licence. This move will allow it to

develop its own processors, rather than basing

its SoCs on cores supplied by ARM. While the v7

architecture addresses 32bit applications, the v8

architecture is aimed at the 64bit world.

He also pointed out that Broadcom is a lead

licensee for the Cortex-A50 cores, based on the

v8 architecture. “We are the only lead licensee

with a business focus beyond mobile

processors,” he claimed. “We have a long history

of making modifications to processor cores,” Doe

concluded, “and there are a lot of things which

Broadcom can add to ARM cores.”

9 July 2013

Fig 2. Block diagram of the StrataGX BCM 58625 processor

1.2GHz ARM Cortex-A9NEON

32kbyte instruction cache32kbyte data cache

Dual core cpu

512kbytelevel 2 cache

with ECC

High speed interconnect

Cryptographicaccelerator

FlexSPARX engine(ARM Cortex-R5 based)

Line rate switchCFP, VLAN, MAC, RED/WRED

DDR2/3

Dram

PCIe USB2/3 GPHY RGMII Peripherals

Gen25.0G

5.0G/480Mbit

5 x GbE i2s sdio flashuart, gpio

“Broadcom has a longhistory of makingmodifications toprocessor cores andthere are a lot of thingswe can add.”Ed Doe

www.newelectronics.co.uk32

company announcement altera

Ultra high definition broadcast equipment,

400G Ethernet systems and computer

data centres – all feast on vast quantities

of data. Consuming and processing that level of

data with any electronic system is difficult. You

will need to be at the leading edge of technology,

both with the architecture you use to process

the data and the manufacturing process you use

to generate the device.

FPGAs have for many years been at this

forefront of technology, Moore’s law has been

kind to FPGAs - with the right

process/architecture design decisions you can

reduce power, increase performance and reduce

cost/increase density at each generation. Each

generation of FPGA captures more applications

that previously would have had to be designed

with ASICs, and opens a new market due to the

performance, flexibility, power or cost that

couldn’t be reached with the older technology.

There are three key aspects to consider when

creating an ideal modern FPGA.

• Leading-edge manufacturing processes

technology

• Investments in innovative architecture and IP

• High-performance integration of processors

with programmable fabric

Advanced process technologies are key for

next generation FPGAs. For example, a new 3D

transistor technology known as Tri-Gate or

FinFET transistor technology is a breakthrough

change in process technology. It halves leakage

current of transistors, which enables high

performance or low power

capabilities.

Most process-technology

foundry suppliers are in the early

test chip stages of finFET. At the

time of writing, Intel is the only

manufacturer who has production

quality products shipping using a

3D (Tri-gate) transistor

technology. Customers looking

and asking for performance

improvements will not get this

from 3D transistor technology

alone, but they will also need a

process shrink. The recently

announced 14 nm Tri-Gate process

from Intel provides this process

technology. Altera’s future Stratix

10 FPGAs will be built using Intel’s

14 nm Tri-Gate process.

Process is only part of the

story; Altera is currently

developing a new architecture

which is capable of astonishing core speeds of

up to 1 GHz. The enhancements to the digital

signal processing (DSP) architecture delivers a

dramatic improvement to DSP capability enabling

over 10 TFLOPs of single precision floating point

operations. Transceiver performance also gets a

boost with the ability to run at up to 56 Gbps

data rates.

Within the Generation 10 portfolio Arria 10

FPGAs use a 20 nm planar transistor process to

implement sixteen 28 Gbps transceivers for

next-generation multi-100G optical interfaces.

With enhanced signal conditioning techniques,

such as adaptive decision feedback equalizers

(DFE), and hardened forward error correction

(FEC), high loss backplane applications can be

addressed.

Processor Integration

FPGA integration of discrete components on a

board has reduced the complexity and cost of

many customer systems, but one of the most

important changes has been the recent

integration of an ARM-based hard processor sub-

system (HPS). Altera Arria 10 SoCs offer

enhanced dual core ARM Cortex™-A9 HPS, this is

a boost for customers wanting tighter integration

between CPU and FPGA fabric. The next

generation HPS is shown in Figure 3.

Next-Generation FPGAs and SoCs Are Coming

Altera uses a tailored innovative approach to

portfolio design, coupling new architectures to

the latest process technology to bring together

an exciting suite of FPGAs. It’s fair to say the

Generation 10 portfolio will have the largest

leap in capabilities that hardware architects

and system designers are yet to see thus far in

an FPGA.


Generation 10 Portfolio from Altera

Drain

Source

Gate

Oxide

Silicon

substrate

Figure 1: Tri-Gate Process Technology

Figure 2: 28 Gbps Operation on 20 nm Process

Technology from Altera

ARM Cortex-A9 QSPI

Flash

Control

UART

(x2)

ARM Cortex-A9

512 KB L2 Cache

EMAC with

DMA (x3) (1)

NAND Flash

(1), (2)

SPI

(x2)

JTAG Debug/

Trace

Dedicated

HPS I/O

USB

OTG

(x2) (1)

I2C

(x5)

Hard Processor System (HPS)

SD/SDIO/

MMC (1)

DMA

(8 Channels)

256 KB

RAM

Timers

(x11)

LW HPS to

Core Bridge

HPS to Core

Bridge

Core to HPS

Bridge MPFE (3)FPGA

Configuration

32 KB L1 Cache 32 KB L1 Cache

NEON FPU NEON FPU

AXI

32

AXI

32/64/128

AXI

32/64/128ACP

Notes:

1. Integrated direct memory access (DMA).

2. Integrated ECC.

3. Multi-Port front-end interface to hard memory controller.

Figure 3: Second-Generation HPS Block with ARM Cortex-A9 Processor

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9 July 201334

System Design Backplanes & Boards

Embedded computer applications demanding

mid range to high end performance always

face the same problem: they need more

speed. But this demand is frequently coupled with

strict requirements in terms of power efficiency to

deliver a level of performance per Watt that fits the

needs of space, weight and power constrained

applications that characterise many embedded

deployments. With the 4th generation Intel Core

processors, a new micro architecture has been

made available using the already proven 22nm

TriGate transistor technology.

The new microarchitecture

The new microarchitecture enables 4th generation

Intel Core processors to offer up to 15% enhanced

cpu performance. At the core, the processors

feature, for example, optimised instruction caches

and out of order execution. For multithread

applications requiring deterministic real time

behaviour, this is of great relevance. Another

feature is the improvement of the execution units,

which increases the number of micro operations

(µops) cycle from six to eight per cycle – an

increase of 33%. As such improvements take place

at the micro operations level, the effective

performance increase is a little less and depends

on the application itself. Beside these

optimisations, important improvements have

been achieved by the addition of new instruction

extensions. By adapting applications to the new

extensions, OEMs can improve the performance

density and responsiveness of their embedded

applications significantly. In detail, the new

enhancements are: Advanced Vector Extensions

2.0 (Intel AVX2), Intel Fused Multiply Add, new Bit

Manipulation Instructions (BMI) and Transactional

Synchronization Extensions (TSX). All these

improvements contribute to an improved

computing performance that is now available in

many different performance flavours.

Broad performance range

Besides supporting turbo boost technology and

the individually definable - and thus limitable –

thermal design power (TDP) of the processors, the

new microarchitecture comes in a very broad

performance range. Core frequency can be as high

as 3.9GHz, quad-core performance in Turbo mode

with 84W TDP down to 25W consuming 1.6GHz

dual core performance. For the embedded market,

the performance range of the mobile processors

is particularly relevant. These processors, which

feature integrated graphics cores, are available

from Intel Core i7 processor with up to 4x 2.4GHz

cores, down to cost optimised Intel Celeron

processor variants. And Intel will be offering a

single chip 15W TDP device later in 2013.

This latter device will accommodate higher

performance processing in a smaller chip package

to enable lighter and thinner compute platforms

for intelligent systems.

With all the different performance stages, the

4th generation of Intel Core processors is suited to

a range of applications, ranging from thermally

sensitive designs to those with compute intensive,

graphics intensive and I/O challenged applications.

Pure performance hungry applications – such as

industrial computers and servers as well as robots,

POS terminals or telecom routers and switches –

will benefit from the AVX 2.0 extensions, as well as

the Turbo Boost and Hyper-Threading support. For

I/O intensive applications ECC is provided, as well

as maximum I/O flexibility with communications

rates of up to PCIe Gen3, USB 3.0 and SATA 6G, to

connect with high speed cameras or the multitude


The next generationThe 4th generation Intel Core processors: one microarchitecture for all mid range to high end embedded applications. By Norbert Hauser.

9 July 2013 35

Kontron’s KTQ87/mITX motherboard

supports small form factor system

development

Fourth Generation processors will bring increased

performance to high end blades, such as the 6U CompactPCI

cpu board CP6005-SA, but without needing active cooling

System Design Backplanes & Boards

of different I/O in test and measurement, factory

automation or with kiosk systems and ATMs or the

wireless infrastructure.

Ubiquitous enhanced graphics

For all these different applications, the 4th

generation Intel Core processors integrate

enhanced graphics. Entry level graphics, entitled

Intel HD graphics, now feature 10 execution units

instead of the six found in the previous processor

generation. While drawing comparable levels of

power, embedded appliances can now offer round

about 35% higher graphics performance.

Meanwhile, the mid range graphics now provide

20 execution units, instead of the previous 16.

A completely new introduction for the bga

packaged processor variants is the top of the line

Intel Iris graphics with 40 execution units. This

comes in two different versions: the Intel Iris

graphics 5100; and the Intel Iris Pro graphics

5200, which features additional fast dram on the

processor package. It offers twice the graphics

performance of the most powerful 3rd generation

Intel Core processor gpu. The new graphics cores

support latest graphics APIs, such as DirectX 11.1

and the platform-independent Open GL 4.x, to

provide a more immersive and realistic 3d

experience at higher resolutions. Monitor

resolutions of up to 4K (3840 x 2160, with VESA

HBR2) are now supported. Support for 4K enables

information to be displayed on huge panels which

provide sharp and detailed visualisation without

visible pixilation, even when in close proximity to

the screen.

Improved security

Designs based on 4th generation Intel Core

processors will allow developers to enjoy

improved security, thanks to the provision of new

Intel AES Instructions.

The architecture consists of six instructions

that offer full hardware support for AES. Four

instructions support the AES encryption and

decryption, while the other two support the AES

key expansion. Between them, they offer a

significant increase in performance compared to

the current pure software implementations

because application performance is not affected.

Beyond improving performance, the AES

instructions provide important security benefits.

By running in data independent time and not

using tables, they help in eliminating the major

timing and cache based attacks that threaten

table based software implementations of AES. In

addition, they make AES simple to implement, with

reduced code size helping to minimise the risk of

inadvertent introduction of security flaws, such as

difficult to detect side channel leaks.

Many different shells

With their highly attractive feature sets, 4th

generation Intel Core processors will allow

engineers to design and build sophisticated

embedded applications in a range of physical

configurations, as well as including a range of

interface configurations. At the same time, the

continuous evolution in x86 innovations puts a lot

of pressure on OEMs to not fall behind with the

implementation. To ensure that customers can

keep up pace with new innovations as simply,

quickly and as cost efficiently as possible,

embedded hardware manufacturers like Kontron

work with a dual strategy – firstly, with regards to

standardisation and, secondly, by offering value

added services for implementing new processor

technology. The aim is to ensure that customers

will have very few worries about implementing the

latest processors.

The first Kontron intelligent platforms to

feature the 4th generation Intel Core processors

will be the Mini-ITX, COM Express and 6U

CompactPCI form factors, as well as the Kontron

SYMKLOUD media cloud platforms. Further boards

and systems will follow.

An impressive fact is that there are not only

board level products available right from the start,

but also dedicated carrier cloud systems. This

underlines Kontron’s efforts to shape the product

offerings even more to industry specific demands

and to deliver a wider range of application ready

platforms.

With their improved processing, graphics

performance, energy efficiency and broad

scalability, the 4th generation Intel Core

processors with the new microarchitecture will

provide an attractive solution for a broad array of

mid to high end embedded applications in markets

such as medical, communications, industrial

automation, infotainment and military.

Author profile:

Norbert Hauser is Kontron’s executive vice

president of marketing.


Kontron’s SYMKLOUD Media Platform is designed for

applications to be deployed in the cloud infrastructure

new electronics - 9 july 2013.pdf-meta

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