nexray 2012 zürich

8/2/2019 NEXRAY 2012 Zrich

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Nexray RTD 2009

2012 | Page 1

Nexray

A. DommannA, H. von KnelC, P. GrningB, T. BandiA, R. BergamaschiniD, C.A.

BosshardA, F. CardotA, D. ChrastinaD, H.R. ElsenerB, C. FalubC,

S. GiudiceA, A. GonzalezC, F. IsaD, G. IsellaD, R. Jose JamesA, R. KaufmannA,

C. KottlerA, Th. KreiligerC, R. LongtinB, A. MarzegalliD, L. MiglioD, A. NeelsA,

P. NiedermannA, A. PezousA, J. SanchezB, G. Spinola DuranteA, Y. ZhaA

A: CSEM C: ETHZ,

B: EMPA D: L-NESS, Politecnico di Milano,

Como, Italy

Zrich, 26. 4. 2012


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Nexray RTD 2009

A System Approach

Source Sample Detector

Contrast mechanism Resolution, Size, EfficiencySpectrum, power,Coherence, Size

Miniaturized, fast

and programmable

X-ray sources

Phase contrast X-

ray imaging

Direct X-ray

detectors without

bump-bonding

Breakthroughs required in all key building blocks of X-ray systems


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Nexray RTD 2009

Network of Integrated Miniaturized X-ray Systems Operating in

Complex Environments

Single-photon solid-

state X-ray detection

Si-Ge layers high-energy X-ray detection

Miniaturized, fast andprogrammable X-ray sources


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Nexray RTD 2009

Novel Concepts of Applications

Large area X-ray sources

Pixelated X-ray sources

Pulsed operation of X-ray source (and individual source-pixels)

Highly efficient sensors, applicable in medical diagnostics

Energy resolved X-ray image detection

Detector

Source


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Nexray RTD 2009

X-ray Source Microfabrication

ExtractionAnode

Emission Cathode

Diamond X-ray Window


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Nexray RTD 2009

Microfabrication

CNT compatibility to Micro-fabrication

CNT samples grown on Ni catalyst on Si

Tested for resist application and lift off

No mechanical delamination found

Gold-Tin solder electroplating

developed

to bond extraction grid on cathode

Layers for Transient Liquid Phasebonding

Eutectic gold tin

Thickness of up to 17 m achieved

To lower the extraction grid voltage

Compatibility to CNT deposition

AuSn Ring for sealing


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Nexray RTD 2009

Integration

Gold-Tin hermetic sealing

High temperature stable(375C/30mins) UBM

for Getter activation developed

Transient liquid phase (TLP) bonding tests for step

annealing and 3D stacking shows first results;

Transformation to Au5Sn proved

Hermetic sealing with a leak rate >10-12mbar*l/sec (at 10-

5 mbar atmosphere) proven with Eutectic

Vacuum levels inside the package to be tested

AuSi tests

To be used for grid-spacer stack bonding

Electroplated Au to bare silicon

Hermeticity achieved on smaller area samples

AuSn

solder

Silicon

SiliconHigh temperature UBM

After shear test bonded

through out the ring

AuSi Flow out shows

formation of Eutectic

CNT cathode AuSn bond

AuSn bond

SpacerAuSi bond

Window

Grid

Au5Sn

TLP Fully transformed Au5Sn


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Nexray RTD 2009

CNT Fabrication 1: Paste CNT Cathode

Paste based CNT deposition

Stencil printing technology: Pixel size of 400m

Process development

Different substrates (Si/Mo), processes

Surface grinding techniques to improve emission

Results

86 mA/cm2 at 350V achieved

(Measured using SAFEM)

Short term reliability tests show stability

V-I follows Fowler-Nordheim plot

Grinding of surface improves emission

characteristics

CNT paste on Mo after Sintering

V-I characteristics of CNT paste

measured using SAFEM


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Nexray RTD 2009

PE-CVD based CNT Deposition Process development

Different Underlayers /recipes

Best growth achieved on Ni catalyst on Si wafer

Tests ongoing to improve homogeneity of the

growth/emission using E-beam lithography

Results

0.5 mA/cm2 at 250V achieved

(Measured using SAFEM) Short term reliability tests show stability

V-I has a some shift from Fowler-Nordheim

E-beam lithography tests needs to be

improved for vertical growthV-I characteristics of the PE-CVD

CNT measured using SAFEM

PE-CVD CNT deposited onSi substrate with Ni catalyst

CNT Fabrication 2: PE-CVD based CNT


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Nexray RTD 2009

Emission Comparison of Different Cathodes

Comparison of emission for

different substrates

Paste deposition on Mo substrates

after grinding shows best results

PECVD growth has potential for

improvements with the E-beam

lithography


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Nexray RTD 2009

Device tests

CTNs show also reproducible electron emission in a source mock-up

44

44

44Insulator (Kapton, Macor, ?)

C

AB

Transmission anode (Cu, Ag, ?)

Assembly holder (Macor, Teflon, ?)

XX

44

Extraction grating

Insulators

CNTs


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Nexray RTD 2009

MEMS for X-ray: Novel X-ray Detector

Epitaxial pillar-like growth of Geon microstructured silicon

wafers

Direct detection without

bump-bonding

pixel

CMOS circuit in p-well

Ge

back-thinned Si

implant

charge carriers

HV

x-ray


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Nexray RTD 2009

MEMS for X-ray: Concept of X-ray Detector

Thick Ge layer

(50 150 m)

Epitaxially grown withLEPECVD

On backside of

CMOS wafer

Ge absorption layer is

hence monolithically

integrated

No bump-bonding needed

n-

Si

1 Pixel

n+p+

- HV

depleted

area

electric

field

lines

CMOS circuit

X-ray

p-

Ge

e h


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Nexray RTD 2009

Primary coil

Plasma source

Primary coil

Turbo pump

Wobblers

Wobblers

Load lockArgon p lasm a

Anode plate

Wafer stage

Wafer

Gas inlet

Electrons emitted by a hot filament sustain a DC plasma

Low (~10eV) ion energy no ion damage

Discharge confined by a magnetic field (~1 mT)

Deposition rates 0.01-10nm/s depending on gas flowand plasma density

Gas phase precursors: SiH4, GeH4

Low Energy Plasma Enhanced CVD


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Nexray RTD 2009

Mutual flux shielding

The self-limiting growth mode could be modeled by taking into account the diffusion

equations and the mutual flux shielding.

From Isolated Pillars to Closely Spaced Arrays


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Nexray RTD 2009

~ 50mSEM picture of 50 m

high Ge towers,

no fusion occurring

Si

Ge

XRD reciprocal space mapsof 50 m high Ge towers,

including Si substrate

HRXRD measurements on

50m Ge towers show that

they are fully relaxed

Detailed scan of

Ge(004) reflection

HRXRD around Ge

(004) peakHRXRD analysis: 50 m Ge towers


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Nexray RTD 2009

(004) reflection

(115) reflection

Ge

(relaxed)

(115) (004)

Si

(substrate)

Reference:

Pure Ge

bulk

Ge tower

50 m

HRXRD analysis: 50 m Ge towers


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Nexray RTD 2009

Dislocation Management by Surface Faceting

415 C 515 C 585 C

All dislocations can be eliminated by controlling the morphology of Ge towers.


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Nexray RTD 2009

6 cycles x 2 min at 780-600C

At different times during the growth

Comparison to unpatterned layer growth

In situ annealing most efficient at early stages of the growth

When Ge pillars are relaxed thermal treatments become inefficient

4 4 4 4 4

.44

. x44444

. x44444

. x44444

. x44444 Pillars S ( )444=44

m

4

Pillars S( )444

= 444m4

Unpatterned Ge

TDD(cm

-4)

Anneal. step distance from interface( m)

TDD of Ge/Si Pillars: In SituThermal Annealing


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Nexray RTD 2009

Ge coverage: 50 m(!)T=490 C

Ge coverage: 7 m

Similar growth morphology irrespective of the thickness!

Self-Limiting Lateral Growth


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Nexray RTD 2009

Post-Processing Details

200 mm processed CMOS wafers Thinned to 100 m withTaiko process, Si backside preparation

Ge growth Oxide passivation & etchback, Ge etching, electrode deposition Dicing

N


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Nexray RTD 2009

N


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Nexray RTD 2009

Post-Processing Tests

On dummy test wafers (150 mm) and

CMOS processed wafers (200 mm)

Thinned to 100 m

Ge growth, 10-50 m pillar growth

200 mm wafers were cut down to

150 mm for post-processing

Fully processed CMOS wafer

with grown Ge pillars (on the backside)

N


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Nexray RTD 2009

CMOS Diode Array

Array with hetero-test diodes produced

Intended for Ge-Si diode characterisation

Front side processing done by Lfoundry

LFoundry closed one of two production sitesDelays

Back side processing done by CSEM & LETI

N


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Nexray RTD 2009

CMOS Read-Out Electronics

+

PulseShaper

-

GrayCnt

CalFSM

is 44

column

busvtst

Register

itst

gtxgrs rsel

tm4

-CSA+vref vref

+

-

DAC

ibias

calck

calib

calib

calib

dvalcout

cval

ith

dval rng

the

-HV

Ge

(substr)Si

sensor:heterojunction

diode

Block diagram and transistor-layout

of the photon counting pixel with

leakage current suppression

Impementation only this summer due

to LFoundry delays

N


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Nexray RTD 2009

Electrical Measurements on Individual Germanium Towers

Au wire

SEM pictureof Au wire

open prober station

Electrical setup at open prober station

SiO2

A

n-Si

Ge Ge Gep-Ge

p-Si

Id

Vd

Au wire

I-V characteristics of individual Ge tower

acting as p-i-n diodeGe towers are electrically

insulated from neighborsby passivated sidewalls

Nexray RTD 2009


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Nexray RTD 2009

Electrical measurements in SEM chamber in-situ

Electrical setup at SEM chamber

I-V characteristics measured in-situ

SEM Zeiss Nvision 40

Conductivetungste

n tip

10 m

2 m

SEM picture of top contact on individual germanium tower

A

n-Si

Ge Ge Ge

p-Ge

p-Si Id

Vd

tungsten tip

SEM chamber

Nexray RTD 2009


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Nexray RTD 2009

Detector:

Thick Ge layers can be grown in towers

First electrical tests on Ge-towers

Temperature compatible CMOS process is developed

Post-processing is tested, needs some fine-tuning

First CMOS processed wafers with Ge towers ready

Source:

Fist electrons could be extracted and accelerated with 10 KV

Extraction currents from CNTs sufficient for X-ray operation

Elements of packaging solutions ready

Status Summary (as of today)

Nexray RTD 2009


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Cosmicmos Add-on Nexray

A. DommannA, H. von KnelC, J. FompeyrineB, Mirja RichterB, Emanuele UcelliB,

C. FalubC, R. KaufmannA, A. NeelsA, E. MllerC, A. GonzalezC, Th. KreiligerC, T.

BandiA, F. IsaD, G. Isella D, D. Chrastina D, L. Miglio D, A. MarzegalliD,

R. Bergamaschini D

A: CSEM; B: IBM, C: ETHZ,

D:L-NESS, Politecnico di Milano, Como, Italy

Zrich, 26. 4. 2012

Nexray RTD 2009COSMICMOS


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Nexray RTD 2009COSMICMOS

Si substrates-Small mass-Good thermalconductivity-Large wafer diameter

GaAs-direct band gap alignment-high carrier mobility-Optimum for the development of optoelectronicdevices

a0GaAs= 5.6532

a0Si = 5.6532

60% difference in thermal

expansion coefficient

Anti Phase Domains:Inherent to the growth of a polarmaterial (GaAs) on top of a non-polarsubstrate (Si)-As-As and Ga-Ga bondings-high electric fields

-donor and acceptor centres. Leakcurrents

4% lattice mismatch

High TDDSolved by the

introduction of Geintermediate

layers

Challenges

Integration of III-V Materials on Si Substrates forHEMTs Development

Nexray RTD 2009

COSMICMOS


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BE regrowth: Ge (001) vs. Ge, 6 miscut towards (11

Ge tower on Si

GaAs/Getower on Si

Epitaxial structure

(001)

Good morphology in the unpatterned area

Anti-phase

domains

formation, bothin the

unpatterned partand thepillars

Si patterning + LEPCVD 2 mGe pillars growth + MBE GaAs regrowth

e epitaxial structure in two different patterned substrates after regrowth them with 2 m of epitaxial6 miscut towards (110)

Substrate: Ge (001) Subst: Ge 6miscut towards(110)

- interaction betweendifferentfacets

COSMICMOS

Nexray RTD 2009

COSMICMOS


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Nexray RTD 2009

Substrate GaAs Ge(9off)

Ge/Si(6off)

Ge(001)

Pillars(1515

m2)

Intensityratio

1 27 36 1268 165

- GaAs growth on Ge (001)substrates leads to APDformation

- GaAs good quality material has

been growth on unpatternedmiscut (6-(110)) Ge

- Our main problem in Ge pillarson miscut wafers comes fromthe interaction betweendifferent facets

- Comparable PL intensitycoming from the QWs grown inthe LEPCVD Ge substrate to acommercial 9 offcut Ge one

- Factor 4.5 on the PL intensitybetween the 1515 m2 pillarsand the unpatterned area

aAs MBE regrowth: PL

Method: Photoluminescence signal of the QWs growth on the two different patternedsubstrates (Ge/Si (001) and Ge/Si with a 6 miscut towards (110)) has been compared

with the one coming from the same structure growth by MBE both on a GaAs and amiscut (9 towards (110)) Ge comercial substrates

COSMICMOS

Nexray RTD 2009

COSMICMOS


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Nexray RTD 2009

GaAs MOVPE

GaAs on

(passivated )Si GaAs on Ge

Polycrystalline growth.

Selectivity on SiOx pillar Faceted material

We have selectivity onGaAs regrowth by MOVPEof pillars passivated with

SiOx. The first attempt ofGaAs regrowth directly onSi result in low qualitypolycrystalline material

Even though the firstresults on pillars are

promising, an optimizationof the Ge epi-readytreatment is needed

Substrates:5 m of epitaxial Ge grown on CSEM Bosch patterned miscut Si and

patterned passivated (SiOx)Growth: 2 temperatures growth method- Low temperature, nominal growthrate 6 nm/min during 5 min, high temperature , nominal growth rate 29 nm/minduring 34 min

COSMICMOS

Nexray RTD 2009

COSMICMOS


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Nexray RTD 2009

a0GaAs= 5.6532

a0Si = 5.6532

60% difference in thermal expansion coefficient

GaAs is a polar material and Si is non-polar ~> antiphase domains(As-As and Ga-Ga bondings) It involves the presence of

high electric fields and donor and acceptor centers.Leak currents

Lattice mismatch (4%) ~>1012 dislocationscm-21

2

3

COSMICMOS

GaAs on Si Substrates: Challenges

Nexray RTD 2009


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Nexray RTD 2009

Thank you for your attention

nexray 2012 zürich

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