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Next Generation SiC MOSFETsPerformance and Reliability
A CREE COMPANY © 2016 Cree, Inc. All rights reserved
Brett Hull , Dan Lichtenwalner, Sei-Hyung Ryu,Edward van Brunt, Jon Zhang, Scott Allen, DaveGrider, Jeff Casady, Al Burk, Michael O’Loughlin,John PalmourAugust 18, 2016
Performance and Reliability
ARL MOS Workshop - August 18, 2016
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• The Wolfspeed division to be acquired includes:- The Power and RF device business- The SiC substrate business for Power, RF and
gemstone applications
• The LED portion of Cree’s Materials business willremain part of Cree
INFINEON TO ACQUIRE WOLFSPEED
© 2016 Cree, Inc. All rights reserved 2
• We remain and operate as separate companies untilthe transaction closes
• It is business as usual for us until the transaction closes
• The transaction is subject to US Government regulatory approval and is expected toclose within calendar year 2016.
ACKNOWLEDGEMENTS
Sponsored in part by Army Research Laboratory under CooperativeAgreement W911NF-12-2-0064
© 2016 Cree, Inc. All rights reserved 3
The information, data, or work presented herein was funded in part bythe Office of Energy Efficiency and Renewable Energy (EERE),
U.S. Department of Energy, under Award # DE-EE0006920.Stephen Boyd and Charles Alsup monitors.
OUTLINE
• Wolfspeed SiC MOSFET Product Portfolio— Design principles and evolution of device generations
• Introduction to Trench MOSFETs for next generation
• Performance and Reliability
© 2016 Cree, Inc. All rights reserved 4
• Performance and Reliability— 900V/10 mW Gen 3 MOSFETs— Intrinsic Failure Mode High Voltage and Gate Lifetime Estimates— Gate Qualifications and Attempting to Predict Early Failures
• Summary
MOSFET RESISTANCECell Pitch
Subs
Drift
DriftSpreading
Spreading
JFET
JFET
Ohmic
Ohmic
MOS chan
MOS chan
20%
40%
60%
80%
100%
Res
isti
veC
omp
onen
t%
Resistive Components
© 2016 Cree, Inc. All rights reserved 5
• Channel resistance is a significant portion of resistance in lower voltage products
• Cell pitch drives channel packing density – the higher the channel density, the lower the totalchannel resistance (Rch)
• Proper Engineering of the JFET gap reduces JFET resistance (RJFET) while improving theshielding of the gate oxide
SubsSubs0%
Gen3 1200 V 10 kV
SPECIFIC ON-RESISTANCE AND BREAKDOWN VOLTAGE
10
100
(mc
m2)
15 kV
10 kV
6.5 kV
3.3 kVCree CMF Family
•
• Achieved the limit for 3.3 kV andhigher SiC DMOSFETs
• Gains remain to be had for lowervoltage SiC DMOSFET products
© 2016 Cree, Inc. All rights reserved 6
1
10
100 1,000 10,000
RO
N,S
P
Breakdown Voltage (V)
3.3 kV
Cree C2M Family
Cree CMF Family voltage SiC DMOSFET products– Increase channel density– Increase channel mobility
4
6
8
10
12
Spec
ific
On
Res
ista
nce
(mW
cm2 ) 25°C
150°C
1200V PLANAR MOSFET ON-RESISTANCE EVOLUTION
0.8X
Gen
1
0.5X
Gen
1© 2016 Cree, Inc. All rights reserved 7
0
2
4
Gen 1 - Planar (2011Product)
Gen 2 - Planar (2013Product)
Gen 3 - Planar (2016R&D)
Spec
ific
On
Res
ista
nce
(m
Optimized Epitaxy, reducedcell pitch, cell engineering
0.5X
Gen
1
TRENCH MOSFET – INCREASED CHANNEL DENSITY
N+ 4H-SiC substrate
P-WellP-Well
N+ N+
Source Source
Aluminum
Poly-Si Gate
Intermetal Dielectric
Gate Oxide
Drain
4H-SiC n- Epitaxial Layer
Cell Pitch Planar MOSFET
2
4
6
8
10
12
Sp
eci
fic
On
Re
sist
an
ce(m
Wcm
2 ) 25°C
150°CReaching
practical limits
© 2016 Cree, Inc. All rights reserved 8
N+ 4H-SiC substrate
Source Source
Aluminum
Intermetal Dielectric
Drain
4H-SiC n- Epitaxial Layer
P-Well
N+
P-Well
N+Poly-SiGate
Gate
Oxid
e
Cell Pitch
Trench MOSFET
Must demonstrate equivalent orbetter reliability in going from
Planar to Trench geometry
0
Gen 1 - Planar(2011 Product)
Gen 2 - Planar(2013 Product)
Gen 3 - Planar(2016 R&D)
Gen 4 - Trench(Est)
Sp
eci
fic
On
Re
sist
an
ce(m
PERFORMANCE AND RELIABILITY UPDATE
© 2016 Cree, Inc. All rights reservedA CREE COMPANY
PERFORMANCE AND RELIABILITY UPDATE
RELIABILITY REQUIREMENTS
• Large segment of thepotential market driven byhigh power applications,requiring many chips inparallel
— Solar Inverters— Industrial Drives and Power
© 2016 Cree, Inc. All rights reserved 10
— Industrial Drives and PowerSupplies
— EV Drives
• Need to drive to PPM failurerates or better 900V/2.5 mW Half Bridge Module
4x 900V/10 mW MOSFETs per switch position
11MOTIVATION FOR SiC IN EV DRIVES
•Assume Ford Focus EV equipped with 90kW IPM motor
•C-Max 90kW Si IGBT inverter or Wolfspeed 88kW SiCinverter as the traction drive
•Synchronous rectification of SiC devices; no diodes inparallel with SiC MOSFETs
© 2016 Cree, Inc. All rights reserved 11
Compared with Si inverter, SiC reduces inverter losses ~67% incombined EPA drive cycle
Simulation data courtesyof Ford Motor Company,based on measuredresults of Wolfspeed900V, C3M 10mOhm SiCMOSFETs
12BENCHMARK 900V SiC & 650V Si (IGBT) POWER MODULES
• 900V SiC XAB350M09HM3 compared with650 V EconoDUAL3 Si IGBT
• 250 V higher blocking voltage
• 10-20x lower body diode recovery, gatecharge, and reverse transfer capacitance.
• Symmetrical 3rd quadrant conduction
• Lower on-state losses
© 2016 Cree, Inc. All rights reserved 12
Parameter Wolfspeed XAB350M09HM3 silicon FF450R07ME4_B11Package HT-3000 (custom) EconoDUAL3Blocking voltage (V) 900 650TJ,MAX (°C) 175 150RDS, ON 2.5 / 3.6 N/AIDS @ 150°C (A) 405 430QG (nC) 648 4800QR @ 150°C (µC) 2.02 (0.504 x 4) 35.5Input capacitance, Ciss / Cies (nF) 15.7 (3.93 x 4) 27.5Rev. transfer cap, Crss / Cres (pF) 72 (18pF x 4) 820
13
0
1
2
3
4
5
6
7
8
0 200 400 600 800 1000 1200 1400 1600 1800
Dra
inC
urr
en
t(u
A)
VGS = 0V150°C
ALT-HTRB – 1200V/80 mW GEN 2 MOSFETS
V BD=
1660
V
Tim
e(H
ours
)
C2M0080120D
© 2016 Cree, Inc. All rights reserved 13
0 200 400 600 800 1000 1200 1400 1600 1800
Drain Bias (V)
Extrapolated Mean Timeto Failure at 800V
30 Million Hours3400 Years
Accelerated Life Testing under High TemperatureReverse Bias Conditions (ALT-HTRB)• 150°C• Drain Bias Conditions: 1460V, 1540V, 1620V• Test to Failure• Collate Failure Time Statistics
14ALT-HTRB – 900V/65 mW GEN 3 MOSFETS
40
60
80
100
120
140
160
180
200
Leak
age
Cu
rren
t(u
A)
VDS
© 2016 Cree, Inc. All rights reserved 14
C3M0065090D MOSFETs – 900V/65mW
• 60 Devices• Parts Run for >1800 hours at 150°C at 1200V+• Three failures from the population as of 1800 hours
VGS = 0V
VDS = 1360V
0
20
0 500 1000 1500 2000
Time (Hours)
15HV LIFETIME PROJECTIONS FOR 900V/65 mW GEN 3 MOSFETS
1E+04
1E+05
1E+06
1E+07
1E+08
1E+09
Pro
jec
ted
Lif
eti
me
(Ho
urs
)
T1%(slope based
on Gen 2)
© 2016 Cree, Inc. All rights reserved 15
• 900V rating results in 65 years before the first projected 1% of failures
• Avalanche rated: zero fails in 1,000 hours at 50 μA, V > 1200V
1E+01
1E+02
1E+03
500 600 700 800 900 1000 1100 1200 1300
Pro
jec
ted
Lif
eti
me
(Ho
urs
)
Vd Stress (Volts)
First failurein
avalanche
16GATE LIFETIME PROJECTIONS FOR 900V/65 mW GEN 3 MOSFETS
~600M hours~10M hours
MTTF(T50%)
© 2016 Cree, Inc. All rights reserved 16
• Extrapolated Intrinsic VGS lifetime of ~600M hours at +15V (DC recommendedoperating point)
• Passed AEC-Q101 qualification of 3 lots x 77 parts with Ø fails in 1,000 hrs atVGS=15V, 150C
T=150°CTested to Failure35 parts per step
17
Part Type Sample Size Total Area Tested Conditions900V/65mW Gen 3 3x77 = 231* 790 mm2 150°C, 15V, 1000 hrs
1200V/25mW Gen 2 3x25 = 75 1380 mm2 150°C, 20V, 1000 hrs
1200V/25mW Gen 2 3x25 = 75 1380 mm2 175°C, 20V, 1000 hrs
1700V/45mW Gen 2 3x25 = 75 1660 mm2 150°C, 20V, 1000 hrs
1700V/45mW Gen 2 3x25 = 75 1660 mm2 175°C, 20V, 1000 hrs
CAS300 Module 6 switches x 665 mm2 125°C (limited by module
HIGH TEMPERATURE GATE BIAS QUALIFICATIONS
© 2016 Cree, Inc. All rights reserved 17
CAS300 Module1200V/25mW Gen 2
6 switches x6 die/switch
665 mm 125°C (limited by modulehousing), 20V, 1000 hrs
• 7500 mm2 total die area tested
• Equivalent of 1,200 of C2M0080120D (1200V/80 mW Gen 2)MOSFETs tested for 1000 hours with zero failures
* Full AEC-Q101 Qualification to meet Automotive Qualification Standards
18ACCELERATED HTGB
Part Type SampleSize
Total AreaTested
Conditions Elapsed Time
1200V/25mW Gen 2 290 5350 mm2 175°C, 27V (20V Vuse) 1000 Hours, 0 Fails
900V/10mW Gen 3 240 5540 mm2 175°C, 20V (15V Vuse) 800 Hours (and counting), 0 Fails
5.0E-09
6.0E-09
Gat
eLe
akag
e(A
)
Assuming a voltage accelerationfactor of 4.0 cm/MV:
• A Gen 2 MOSFET that survives
© 2016 Cree, Inc. All rights reserved 18
0.0E+00
1.0E-09
2.0E-09
3.0E-09
4.0E-09
0 200 400 600 800 1000 1200
Gat
eLe
akag
e(A
)
Time (Hours)
60 Representative parts1200V/25 mW MOSFETs
• A Gen 2 MOSFET that survivesfor 1000 hours at VGS = 27V isestimated to survive for 50years at VGS = 20V
• A Gen 3 MOSFET that survivesfor 800 hours at VGS = 20V isestimated to survive for 21years at VGS = 15V
SUMMARY
•fraction of total device resistance
— We continue to drive to higher cell density and optimized epitaxy of ourPlanar DMOSFET technology to drive to more efficient MOSFET products
— We are approaching the limits of the planar technology, but there is onemore generation of device that we can achieve
• Any forthcoming technology must match the reliability of the
© 2016 Cree, Inc. All rights reserved 19
• Any forthcoming technology must match the reliability of thePlanar DMOSFET platform
• Intrinsic Reliability is superb, but we will continue to examinedefectivity and accelerated test conditions to drive failure ratesdown on large populations of parts
• We have demonstrated T1% Lifetimes of greater than 50 years (GateLifetime and High Drain Bias Lifetime)
A CREE COMPANY © 2016 Cree, Inc. All rights reserved