noise canceling in 1-d data: presentation #6 seri rahayu abd rauf fatima boujarwah juan chen liyana...
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Noise Canceling in 1-D Data: Presentation #6
Seri Rahayu Abd RaufFatima BoujarwahJuan ChenLiyana Mohd SharippArti Thumar
M2
Feb 23rd, 2005Functional Layout/Floorplan
Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware
Project Manager: Bobby Colyer
Status
• Design proposal (Done)
• Architecture proposal (Done)
• Size Estimates and Floorplan (Done)
• Gate Level Design
- Schematics (Done)
• To be done:– Layout (28%)– Spice simulation
Design Decisions
1. Compared the performance of the mirror adder with the our Mux-Adder
• Area vs Speed• Discovered that they have the same size, so
stick to the original one
2. Decided to implement Booth Recoding for the Wallace tree multiplier
• Need more testing
Last Monday…
Today…
Functional Block Layout
ROM Table
Input from counter
Output to converter
Tentative Layout for Fixed Point Multiplier (aka the Wallace)
Left TreeRight Tree
Pseudo-Layout for the fpAdder
Improved Half Adder
Improved Full Adder
Alternative: Mirror Adder
Completed 16 bit 2-1 Mux
Challenges…
• Booth…
• Revision to Floorplan due to optimized layout of the functional blocks
Questions?