noise canceling in 1-d data: presentation #7 seri rahayu abd rauf fatima boujarwah juan chen liyana...
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Noise Canceling in 1-D Data: Presentation #7
Seri Rahayu Abd RaufFatima BoujarwahJuan ChenLiyana Mohd SharippArti Thumar
M2
Feb 28th, 2005Functional Block Layout/Floorplan
Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware
Project Manager: Bobby Colyer
Status
• Design proposal (Done)
• Architecture proposal (Done)
• Size Estimates and Floorplan (Done)
• Gate Level Design
- Schematics (Done)
• To be done:– Layout (35%)– Spice simulation
Updated Transistor Count
PartLast Week’s Transistors
New Transistors
16-bit FPA 3x 4154 = 12462 3x 2746 = 8238
16-bit FPM 3x 3858 = 11574 3x 4456 = 13368
Registers 7x16x14 = 1568 7x 272 = 1904
ROM 800 783
Converter 2x312 = 624 2x 108 = 216
MUX 384 402
Adder 248 248
Counter 214 222
Alternator 64 0
Total≈ 27938 + Misc ≈ 30000
≈ 25381 + Misc ≈ 27000
Challenges…
• Finishing up layout
• Make sure that the signal strength is sufficient
• Need to decide (multiplier) – symmetry vs. trans count