OCP: Open Core OCP: Open Core ProtocolProtocol

Marta PosadaMarta Posada

ESA/ESTECESA/ESTEC

June 2006June 2006

MotivationMotivation

SOC designers want to SOC designers want to reusereuse IP cores to IP cores to shorten development schedules.shorten development schedules.

Problem:Problem: IP cores need to be re-adapted IP cores need to be re-adapted into each system designinto each system design

Motivation:Motivation: reuse without rework reuse without rework Plug-and-playPlug-and-play between cores and between cores and

interconnects systems from different sources.interconnects systems from different sources.

What is needed?What is needed?

What is required is a What is required is a standard, well-defined standard, well-defined protocolprotocol for cores to talk to a system for cores to talk to a system interconnect.interconnect.

On-chip interconnect

Core 1

core i/f

System socket

Core 2

core i/f

System socket

Core N

core i/f

System socket

Core designers

Systemintegrator

OPEN CORE PROTOCOL 2.0OPEN CORE PROTOCOL 2.0

Point-to-point, uni-directional, synchronousPoint-to-point, uni-directional, synchronous Easy physical implementationEasy physical implementation

Master/Slave, Request/Response modelMaster/Slave, Request/Response model Well-defined, simple rolesWell-defined, simple roles

ExtensionsExtensions Added functionality to support cores with more Added functionality to support cores with more

complex interface requirementscomplex interface requirements ConfigurabilityConfigurability

Match a core’s requirements exactlyMatch a core’s requirements exactly Tailor design to required features onlyTailor design to required features only

OPEN CORE PROTOCOL 2.0OPEN CORE PROTOCOL 2.0

OCP is configurable to tailor the interface OCP is configurable to tailor the interface exactly to the features required by the coreexactly to the features required by the core

Basic OCP is very simpleBasic OCP is very simple Many extensions exist for cores with more complex Many extensions exist for cores with more complex

interface requirementsinterface requirements

OCP is configured via a set of parametersOCP is configured via a set of parameters Control the presence of a set of signalsControl the presence of a set of signals

• example: core makes use of byte enablesexample: core makes use of byte enables Control the width of a set of signalsControl the width of a set of signals

• example: address width is 14 bitsexample: address width is 14 bits Control protocol featuresControl protocol features

• example: core uses data handshaking to pipeline write dataexample: core uses data handshaking to pipeline write data

BASIC OCP INTERFACEBASIC OCP INTERFACE

Mas

ter

Sla

ve

Request

Write Data

Response

Read Data

Control signals

test signals Sys

tem

Cor

e

Accept Request

Accept WR Data

Accept Response

Clock

Dataflow

signals

Response

R

equest

Optional handshake signals

Master / SlaveMaster / Slave Split protocolSplit protocol Multiple phases:Multiple phases:

Request phaseRequest phase Response phaseResponse phase Separate data Separate data

handshake handshake (optional)(optional)

COMUNICATION PHASESCOMUNICATION PHASES

Read ReadEx ReadLinked Write w/o datahandshake WriteNonPost WriteConditional Write w/datahandshake

Response

Request

Data

Request

Request

Request

Response

Response

Response

Possible Response Code

DVA / ERR

DVA / ERR

DVA / ERR

DVA / ERR

Request Response DVA / FAIL / ERR

Response

DVA Data Valid / Acknowledge

Optional response phase

ERR Transfer Error

FAIL Write operation has failed

SIMPLE EXTENSIONSIMPLE EXTENSION Byte enablesByte enables

Provide byte addressing capability on a multi-byte Provide byte addressing capability on a multi-byte interfaceinterface

Multiple address spaces, mapped at non Multiple address spaces, mapped at non contiguous address ranges. Typically to:contiguous address ranges. Typically to: Differentiate core registers from core memory spaceDifferentiate core registers from core memory space Differentiate cores within a sub systemDifferentiate cores within a sub system

Custom in-band signalingCustom in-band signaling To any of the transfer phases: Request, response, To any of the transfer phases: Request, response,

datahandshakedatahandshake Typical usage: Cache signaling, application/emulation Typical usage: Cache signaling, application/emulation

qualifier, dynamic endianness qualifier…qualifier, dynamic endianness qualifier…

BURST EXTENSION(I)BURST EXTENSION(I)

Multiple Multiple independent independent OCP transfersOCP transfers can be can be linked together into a single burst transaction.linked together into a single burst transaction. Burst allow target to know there are more Burst allow target to know there are more

transfers coming for pre-fetchingtransfers coming for pre-fetching Use of burst can greatly improve overall system Use of burst can greatly improve overall system

performanceperformance

Burst are linked together using a burst code that is Burst are linked together using a burst code that is supplied with every transfersupplied with every transfer Burst signaling supplies the burst address Burst signaling supplies the burst address

sequence, the burst length, the burst typesequence, the burst length, the burst type

OCP BURST EXTENSION(II)OCP BURST EXTENSION(II)

Ability to handle Ability to handle preciseprecise bursts (the length is known) and bursts (the length is known) and un-preciseun-precise bursts (the length is unknown). bursts (the length is unknown).

Ability to specify standard address sequences Ability to specify standard address sequences ((incrementing, wrapping, streaming, XORincrementing, wrapping, streaming, XOR) as well as ) as well as custom address sequences.custom address sequences.

Ability to support Ability to support single request/multiple datasingle request/multiple data transaction models.transaction models.

Ability to define atomic sub-units within a burst for fine Ability to define atomic sub-units within a burst for fine control of the request interleaving throughout the system control of the request interleaving throughout the system interconnect.interconnect.

Ability to add complete Ability to add complete framing informationframing information with all with all transfer phases.transfer phases.

OCP THREAD EXTENSIONOCP THREAD EXTENSION Within an OCP thread, responses must return in the Within an OCP thread, responses must return in the

order of the requests.order of the requests.

For some cores, out-of-order responses are desirableFor some cores, out-of-order responses are desirable A multi-bank DRAM controller can return requests to an A multi-bank DRAM controller can return requests to an

open bank faster than to a closed oneopen bank faster than to a closed one A DMA controller can handle multiple outstanding A DMA controller can handle multiple outstanding

transactions from multiple channels on the same OCP porttransactions from multiple channels on the same OCP port

An OCP interface can support An OCP interface can support multiple threadsmultiple threads Allows for concurrency and out-of-order returnsAllows for concurrency and out-of-order returns Each thread retains strict ordering semanticsEach thread retains strict ordering semantics BUT: there are is no ordering between transfers in different BUT: there are is no ordering between transfers in different

threadsthreads

SIDEBAND SIGNALSSIDEBAND SIGNALS

ResetReset InterruptInterrupt Transaction error reportingTransaction error reporting Core Flags (core-to-core)Core Flags (core-to-core) Core Status/Control (system-to-core)Core Status/Control (system-to-core) TestTest

Converting Existing Cores to OCPConverting Existing Cores to OCP

Determine the OCP characteristics that the core Determine the OCP characteristics that the core will havewill have

Design conversion logic to wrap the coreDesign conversion logic to wrap the core Describes the core’s interface and timing Describes the core’s interface and timing

constraintsconstraints Develop a portable testbench for the coreDevelop a portable testbench for the core If the core is synthesizable, develop a If the core is synthesizable, develop a

technology-independent synthesis script for ittechnology-independent synthesis script for it Assemble the core, modelsm documentation… Assemble the core, modelsm documentation…

and packageand package

CORE CONVERSIONCORE CONVERSION

1.1. Know the native core interfaceKnow the native core interface2.2. Know OCPKnow OCP3.3. Build bridgeBuild bridge4.4. TestTest5.5. Package OCP corePackage OCP core

Existing Core

OCPBridge

Core interface

OCP interface

OCP CORE BRIDGEOCP CORE BRIDGE

Match OCP configurations to native Match OCP configurations to native protocol patterns.protocol patterns. Chose the kind of socket Chose the kind of socket Master or Slave Master or Slave Choose the interface signalsChoose the interface signals

- Choose the simplest configuration that - Choose the simplest configuration that meets the functional and performance meets the functional and performance requirements of the corerequirements of the core

Develop the bridge logic to convert core Develop the bridge logic to convert core signals into OCP signalssignals into OCP signals

Case of Study: CAN CORECase of Study: CAN CORE

Tx_bit

Bit_stream

Remote_frameResetClock

Tx_msg[0-101]StartPs1Ps2RsjBpr

Bus_offTx_completedRx_completedRx_msg[0-101]

Err_passiveRx_err_cntTx_err_cnt

SyncbitTx_busy

TestSample

Sample_bitReset_asynFilter_remote = ‘1’

= ‘1’

CAN CORE

CAN (Control Area Network) is a serial communications protocol which supports distributed real time control with a very high level of security.

We are going to convert CAN Core 5.1 (developed by ESA) to OCP.

Interface CAN:

Case of study: CAN CORECase of study: CAN CORE

OCP BRIDGEOCP BRIDGE We are going to design a SLAVE OCP socketWe are going to design a SLAVE OCP socket OCP Burst Extension, with single request OCP Burst Extension, with single request

multiple data.multiple data. OCP Word : 1 byte (8 bits)OCP Word : 1 byte (8 bits) Commands : Idle (IDLE), Write (WR) and Commands : Idle (IDLE), Write (WR) and

Read (RD)Read (RD) Responses: Null (NULL), Data Valid (DVA) Responses: Null (NULL), Data Valid (DVA)

and Error (ERR).and Error (ERR).

Case of study: CAN CORECase of study: CAN CORE

OCP INTERFACEOCP INTERFACE

Remote_frameResetClock

Tx_msg[0-101]StartPs1Ps2RsjBpr

Bus_offTx_completedRx_completedRx_msg[0-101]

Err_passiveRx_err_cntTx_err_cnt

SyncbitTx_busy

TestSample

Sample_bitReset_asyn

Filter_remote= ‘1’

= ‘1’

OCP SLAVE

REGISTERS STATE MACHINE

Clk

Mreset_nMCmdMaddrMData

MBurstLengthMBurstSeq

MBurstPreciseMBurstSingleReq

MDataValidMdata

MDataLast

SCmdAcceptSData

SDataAcceptSresp

SRespLast

Case of study: CAN CORECase of study: CAN CORECAN TO OCP CAN TO OCP

Model inspired in Model inspired in HurryAmba (developed HurryAmba (developed by ESA).by ESA).

The CAN core signals The CAN core signals are going to be store in are going to be store in some registers. some registers.

Both CAN and OCP Both CAN and OCP bridge have access to bridge have access to the registersthe registers

Pooling to know there Pooling to know there are received data in the are received data in the registersregisters

F4hF4hRx_error_cntRx_error_cnt

F0hF0hTx_error_cntTx_error_cnt

8Ch - ECh 8Ch - ECh Rx_msg0 – Rx_msg0 – Rx_msg12Rx_msg12

28h – 88h28h – 88hTx_msg0-Tx_msg12Tx_msg0-Tx_msg12

24h24hFilter3Filter3

20h20hFilter2Filter2

1Ch1ChFilter1Filter1

18h18hFilter0Filter0

14h14hStatus1Status1

10h10hStatus0Status0

0Ch0ChSetup3Setup3

08h08hSetup2Setup2

04h04hSetup1Setup1

00h00hSetup0Setup0

ADDRESSADDRESSREGISTERREGISTER

Case of study: CAN CORECase of study: CAN CORETIMING DIAGRAMS. Write operationTIMING DIAGRAMS. Write operation

Case of study: CAN CORECase of study: CAN CORE

TIMING DIAGRAMS. Read operationTIMING DIAGRAMS. Read operation