octilinear redistributive routing in bump arrays

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1 Octilinear Redistributive Routing in Bump Arrays Renshen Wang Chung-Kuan Cheng Department of Computer Science & Engineering University of California, San Diego

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Page 1: Octilinear Redistributive Routing in Bump Arrays

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Octilinear Redistributive Routing in Bump Arrays

Renshen WangChung-Kuan ChengDepartment of Computer Science & EngineeringUniversity of California, San Diego

Page 2: Octilinear Redistributive Routing in Bump Arrays

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Outline of Today’s Talk� Introduction & Background� Redistribution Layer (RDL) Routing

Problem Formulation� Previous Approaches� Grid Network Approach�Min-cost max-flow and RDL routing solution

�Grid network construction

� Experimental Results� Conclusions and Future Works

Page 3: Octilinear Redistributive Routing in Bump Arrays

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Background� Chip to package connections�Wire bonding � Ball grid array

� On-chip I/O patterns & Array patterns�Possible mismatch

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Redistribution Layer� A “re-distribution layer” (RDL) is used to

connect I/O pads to solder bumps

� RDL routing

Page 5: Octilinear Redistributive Routing in Bump Arrays

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Redistribution Layer (RDL) Routing Problem Formulation

� Connect I/O pads to bumps� Given wire width

� Minimum wire spacing

� Characteristics� Interchangeability (no crossings)

�8-geometry wires are usually used (“ – | × ”) to reduce wire length and routing congestion

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Previous Approaches� Manual design� Routing on graph models�Effective for Manhattan routing, but not for

handling 45°wires

� Design for special patterns4 wires 7 wires ?

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Grid Network Approach� Manhattan routing using a grid network�Construct a grid in the bump array

�Routing solution ↔ network flow solution

… …

… …Pads

Bumps

Unit size = wire width + spacing

Edge capacity = 1

Vertex capacity= 1

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Grid Network Approach� Octilinear routing�Octilinear grid?

Not enough spacing between 45°tracks

Excessive crossing points

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Octilinear Grid for RDL Routing� Line shifting�Topologically shift the 45°tracks on to

Manhattan grid�Preserve the actual positions of 45°tracks

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Octilinear Grid for RDL Routing� Spacing violations avoided by min-cost

max-flow on the grid�Between a grid node and a 45°track

Not a violation

Between an off-grid node and an H/V track

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Octilinear Grid for RDL Routing� Octilinear routing on the grid network�Construct a Manhattan grid in the bump array

�Add “topologically shifted” 45°tracks by area

�Routing solution ↔ network flow solution

… …

… …Pads

Bumps

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Detailed Grid Construction� Crossing area of H/V channels

� (Ccross – 2) 45°tracksdistributed at center � Actual diagonal

capacity = 4 �

( ) ( )( ) / 2 /cross H VC W W s w s = + − +

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Detailed Grid Construction� Channel segment area

� (Cseg – 1) 45°tracksdistributed at center

� Cseg = 4 �

( ) ( )( ) / 2 /seg seg segC L W s w s = + − +

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Detailed Grid Construction

� On the boundary of 2 adjacent areas

If there is a spacing violation, shift the 45°tracks onto the same grid node

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Detailed Grid Construction� Missing bump area�Extend the tracks in the channel segments

�Add two diagonal tracks

� (Cseg – 1) tracks in each channel segment

� Min-cost max-flow � RDL routing solution

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Wire Smoothing

� Min-cost max-flowgives shortest paths�With possible zigzag shapes

� Iterative post processingA

B

Shortest path area

Repeat {For each unit of flow:

1) Delete the flow unit from source to sink; 2) Find a shortest path with min #turnings;3) Resume the flow unit by the new path;

} Until no path is changed in the iteration

Page 17: Octilinear Redistributive Routing in Bump Arrays

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Shortest Path with Minimal Number of Turnings� Dynamic programming on Shortest path

algorithm� “α-β routing”, [Hu1985]

�1 node � 8 states�distance � (distance, #turnings)

� O(nlogn) time

node splitting

A graph node with 8 edges

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Experimental Results� Two different pad distributions in the same

bump array

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Experimental Results� More test cases (running time counted in

seconds)

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Conclusions and Future Works� First octilinear RDL router�Automatic and optimal RDL routing is possible

� Topological “line shift” for octilinear grid

� Limited for single layer cases�System complexity ↑ & I/O connections ↑�Multiple redistribution layer

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Q & A

� Thank you for your attention

This work is done in Mentor Graphics Corporation during an internship