operand addressing and instruction representation cs355-chapter 6
TRANSCRIPT
Operand Addressing And Instruction Representation
Cs355-Chapter 6
Design Issues
• A good ISA – Ease of implementing on current hardware – Provide clean target for compile code
Choice of the number of operands in the instruction set is a matter of discussion.
Zero Operand Instructions
• Zero address architecture machines are called as the stack machines.
• The Instruction does not specify any operands.
• Operands are implicit.
• Push adds a given node to the top of the stack.
• Pop removes current top node of the stack and places it in the memory.
• Based on the Last in first out principle.
From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.
One Operand Instruction
• Architecture that limit each instruction to single operand is known as 1-address design.
• Relies on implicit operand for each instruction to store in special register known as an accumulator.
Step to process one operand per Instruction
• Processor extracts the current value of the accumulator .
• Performs the specified operation using the extracted value and the operand .
• place the result back in the accumulator
• Ex: Add X
• Accumulator Accumulator + X
From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.
Disadvantage of One Operand Per Instruction
• It does not allow instructions to specify two values.
• It requires two instructions that load the value into the accumulator and then need to store the values back in the new location
Two Operands Per Instruction
• Overcomes the limitation 1-address systems
• Using 2 address process, an operation can be applied to a specified value.
• It also offers data movement instructions that treat the operand as source and destination.
• Ex: Move Q R
Copies directly from Q to R
From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.
Three Operand Per Instruction
• Similar as Two Operand Per Instruction except that it can operate three input value per instruction.
• For processors which have multiple general purpose registers.
• Ex: Add X Y Z
• Computes Z X + Y
Operand Sources And Immediate Values
• Operand that specifies a source must be
-A signed constant
-An Unsigned constant
-The content of a register
-The value in a memory location
Operand Sources And Immediate Values
• Operand the specifies a destination must be:
-A signed register
-A pair of contiguous registers
-A memory location
Von Neumann Bottleneck
• Operand addressing is the central weakness of a von Neumann architecture.
• memory access may become a bottleneck because instructions are stored in memory and a processor must make at least one memory per instruction.
• To Optimize the performance, operand must be taken from a register instead of memory.
Types of Encoding
• 1. Explicit Operand Encoding
• 2. Implicit Operand Encoding
Implicit Operand Encoding • The Opcode specifies the types of operands.
• A processor that uses a implicit encoding contains multiple operand code for a given operation.
Disadvantage of Implicit encoding
• Multiple opcodes are needed for a given operation.
• A list of opcodes can become large, when a processor allows many types of operands.
Explicit Encoding• Using Explicit can overcome the disadvantage of
implicit encoding.
• Each operand is represented by two fields: 1. Type of Operand 2. Type of Value
From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.
Tradeoffs in the choice of operands
• Ease of Programming
• Fewer Instructions
• Smaller Instructions
• Larger Range of Immediate Values
• Faster Operand Fetch and Decode
• Decreased Hardware size
Tradeoffs in the choice of operands
Ease of Programming :
• We know that complex forms of operands make programming easier
• 3-address approach mean we do not need to code separate instructions.
Fewer Instructions :
• Reduces the number of instruction in a program by increasing the expressive power of operands
• Lowers the count of instructions by increasing the number of addresses
Tradeoffs in the choice of operands
Smaller Instructions :How to keep smaller Instruction?
• Limiting the number of operands
• Limiting the set of operands types
• Limiting maximum size of an operand keep instruction small
Tradeoffs in the choice of operands
Larger Range of Immediate values :
• Increasing the size allows larger values because the size of a field in the operand determines the numeric range of immediate values.
• Disadvantage: Larger instruction results
Tradeoffs in the choice of operands
Faster Operand Fetch and Decode :How to operate hardware faster? • limit the number of operands
• limit the possible types of each operand
Decreased Hardware size :How to decrease the hardware size? • limits the types and complexity of operands
• Reduces the size of circuitry
Values in Memory
• Every processors include at least one instruction that allows an operand to specify value in memory
• Values in the operand interpreted as an memory address.
• This memory address is for the processor to perform memory lookup.
Advantage of memory look up
• Helps ease programming
• Helps allowing arbitrary instruction to reference memory.
• improves performance.
Operand Addressing Modes
• Instruction register is used to hold an instruction that is being decoded.
• A immediate value can be found in instruction register
From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights reserved.
Key Points
• Different type of Operand instruction
• Von Neumann Bottleneck.
• Different choice of Operand Addressing Modes