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The University of Texas at Dallas

Department of Electrical Engineering

EECT 6326 ANALOG IC DESIGN

“DESIGN OF AN OPERATIONAL AMPLIFIER”

BHARAT ARUN BIYANI (2021152193)

MOINAK PYNE (2021185405)

RAVI TEJA ELESWARAPU (2021185138)

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TABLE OF CONTENT

Sr. No. Description Page #

1 Design Specifications 3

2 Design Procedure 4

3 Design Layout 5

4 Region Testing 6

5 Measurement of GAIN, PHASE MARGIN, GBW 7

6 Measurement of CMRR 9

7 Measurement of POWER DISSIPATION 11

8 Measurement of SLEW RATE 12

9 Measurement of OUPUT VOLTAGE SWING RANGE 14

10 Summary of Simulated Values 16

11 Final Score 17

12 Conclusion 17

13 Reference 17

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DESIGN SPECIFICATIONS

Design a differential input and single-ended output amplifier. The amplifier is to be powered from a 1.8V power supply. The amplifier should consist of ONE current reference that can be realized by either an ideal current source or a supply independent current source. The current mirrors required for biasing different transistors in the amplifier can be derived from the current mirrors. Use capacitive load as 3pF. Use CMOS 0.35-μm technology given in this course or other relevant 0.35-μm CMOS to best meet the following specifications:

Sr. No. Parameters Value

1 Differential Voltage Gain (Avd) ≥ 85 dB

2 Output Voltage Swing- Range (OVSR = Vo(max) - Vo(min) ) ≥ 1.4 V

3 Average Slew Rate (SR) ≥ 15 V/µs

4 Common Mode Rejection Ratio (CMRR) ≥ 80 dB

5 Unity Gain-Bandwidth (GBW) ≥ 15 MHz

6 Phase Margin ( f(GBW)) ≥ 60o

7 Power Dissipation (Pdiss) ≤ 0.3 mW

Table 1: Design Specifications

Note

Average slew rate = (SR++SR-)/2

Power Dissipation including dissipation form the current reference and current mirrors.

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DESIGN PROCEDURE

In order to achieve required gain, we need to use two-stage amplifier. We are using Two

Stage Miller Compensated Amplifier for our design.

Figure 1: A Two-Stage Miller Compensated Amplifier

On the similar page, two-stage amplifier introduces second pole which brings instability

to our system. In order to compensate this effect we need to use a capacitor (Cm), connecting

the output of the first stage and output of second stage to pull two poles away from each

other.

In addition, two-stage amplifier reduces the phase margin of our system. In order to

increase the Phase Margin (f (GBW)) we need to use a resistor (Rm), connecting the output of

the first stage and output of second stage which won’t affect the pole position.

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DESIGN LAYOUT

Figure 2 is the schematic of our design which we implemented using Cadence. Dimensions of each

component are listed in the Table 2.

Figure 2: Design Layout

Sr. No. Device Size (W/L)

1 Differential Amplifier pMOS (M0, M1) 25µm/1µm

2 Differential Amplifier nMOS (M3, M6) 60µm/3.5µm

3 First Branch nMOS (M7) 18µm/3µm

4 Differential Amplifier tail Current Source nMOS (M4) 108µm/3µm

5 Second Stage pMOS (M2) 290µm/2µm

6 Second Stage nMOS (M5) 360µm/3µm

7 Resistor (r) 3.4 kΩ

8 Capacitor(c) 2.1pf

Table 2: Component Dimensions

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REGION TESTING

Figure 3: Transistor Region Testing Circuit

For our design, all the transistors should be in Saturation region. In order to check this we need to

perform DC analysis. As shown in Figure 3

1. Apply 1V DC to both the input terminals (INP & INN).

2. Apply 1V AC to positive input terminal (INP). This will generate 1V AC differential voltage

between the two terminals.

3. Apply 6µA Reference Current Source (Iref) to input terminal (Ibias).

4. Apply 1.8V DC between VDD and GND terminal.

5. Check the region by choosing Result > annotation > DC operation point,.

From Figure 3, it can be seen that all the transistors are in REGION 2 which implies that they are in

SATURATION.

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MEASUREMENT of GAIN, PHASE MARGIN, GBW

After generating a symbol view of Figure 2, we can apply the test vector to this symbol view

as shown in Figure 4 to calculate the Gain, Phase Margin and GBW.

6. Apply 1V DC to both the input terminals (INP & INN).

7. Apply 1V AC to positive input terminal (INP). This will generate 1V AC differential voltage

between the two terminals.

8. Apply 6µA Reference Current Source (Iref) to input terminal (Ibias).

9. Apply 1.8V DC between VDD and GND terminal.

10. Check the result at the OUT terminal.

Figure 4: Test Circuit to Calculate GAIN, PHASE MARGIN, GBW

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Waveform 1: GAIN & GBW calculation

Waveform 2: PHASE MARGIN calculation

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From the waveform 1, we get the Differential Voltage Gain (Avd) of our system as 80.13dB.

Frequency at which is Gain becomes 0dB is Unity Gain-Bandwidth (GBW). From

waveform 1, we get the Unity Gain-Bandwidth (GBW) of our system as 19.26MHz.

We know the Phase at Unity Gain-Bandwidth (GBW) is nothing but the Phase Margin

(PM). From waveform 2, we get the Phase as -119.4 o at 19.26MHz which is GBW of our system

from waveform 1.But as the waveform 2 starts from 0 o, the actual Phase Margin (PM) is,

Phase Margin (PM) = 180 o - 119.4 o = 60.6 o

Hence, we get Phase Margin (PM) of our system as 60.6 o.

Measurement of CMRR

A good differential amplifier generally has very low common mode gain such that even

drastic common mode variations are not very significant. The output is purely generated by the

comparative conditions of the symmetric circuits and this depresses the disturbances giving a

faithful output.

Common mode Rejection ratio (CMRR) is difference between the differential voltage

gain (Avd) and common mode voltage gain (Av_cm) in dB.

After generating a symbol view of Figure 2, we can apply the test vector to this symbol view as

shown in Figure 5 to calculate Common Mode Voltage Gain (Av_cm). We already know the

Differential Voltage Gain (Avd) of our system as 80.13dB.

1. Apply 1V DC to both the input terminals (INP & INN).

2. Apply 1V AC to both the input terminals (INP & INN). This will generate a 1V AC common

mode voltage between the two terminals.

3. Apply 6µA Reference Current Source (Iref) to input terminal (Ibias).

4. Apply 1.8V DC between VDD and GND terminal.

5. Check the result at the OUT terminal.

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Figure 5: Test Circuit to calculate COMMON MODE VOLATGE GAIN (Av_cm)

Waveform 3: COMMON MODE VOLATGE GAIN (Av_cm) calculation

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Form Waveform 3, we get the COMMON MODE VOLTAGE GAIN (Av_cm) as -5.4 dB. So,

CMRR = Differential Voltage Gain (in dB) - COMMON MODE VOLTAGE GAIN (in dB)

= 80.13 dB – (- 5.4 dB) = 85.53 dB.

Hence, we get Common Mode Rejection Ratio (CMRR) of our system as 85.53 dB.

MEASUREMENT OF POWER DISSIPATION

Power Dissipation (Pdiss) in the circuit is product of voltage and current. As we have three branches in our design, Power Dissipation is nothing but the supply voltage multiplied by the total current through the circuit (sum of currents from all the branches).We knows that our supply voltage is 1.8V. In order to calculate total current, we need to perform DC analysis.

After generating a symbol view of Figure 2, we can apply the test vector to this symbol view as shown in Figure 6 to calculate total current in circuit.

Figure 6: Test Circuit to calculate Power Dissipation (Pdiss)

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Choose the Result > annotation > DC operation point, it can clearly show the total current through our system is -165.3uA. This can be clearly seen from figure 4. So,

Power Dissipation (Pdiss) = Voltage * Current.

= 1.8V * 165.3µA = 297.54W

Hence, we get Power Dissipation (Pdiss) of our system as 297.54W or 0.29754mW.

MEASUREMENT OF SLEW RATE

Slew Rate (SR) is how fast output changes with respect to input. The slope of output

voltage (dVo/dt) is defined as the Slew Rate (both positive and negative). Slew Rate should be as

high as possible which denotes that the output voltage waveform follows the input voltage

waveform more closely. In order to calculate Slew Rate we need to perform transient analysis.

After generating a symbol view of Figure 2, we can apply the test vector to this symbol view as shown in Figure 7 to calculate Average Slew Rate of the circuit.

1. Connect the negative input terminal (INN) to the output terminal (OUT).

2. Apply a Pulse Voltage to the positive input terminal (INP) with below specification.

Pulse Width = 200ns, Period = 400ns, V1 = 0V, V2= 1.8V.

(Note that above specification we have used for our design to generate the Pulse voltage)

3. Apply 6µA Reference Current Source (Iref) to input terminal (Ibias).

4. Apply 1.8V DC between VDD and GND terminal.

5. Check the result at the OUT terminal.

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Figure 7: Test Circuit to calculate Slew Rate (SR)

Waveform 4: SLEW RATE calculation

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We need to calculate positive slew rate and negative slew rate, in other words positive

slope and negative slope. As seen from the waveform 4-

Positive Slope or Positive Slew Rate (SR+) = (1.542-0.4485)/ (0.4699-0.4106) V/µs = 18.44 V/µs

Negative Slope or Negative Slew Rate (SR-) = (1.654-0.6477)/ (0.618-0.6953) V/µs = 13.018 V/µs

(Neglected negative sign for Negative Slope or Negative Slew Rate)

So,

Average slew rate = (SR++SR-)/2

= (18.44 + 13.018)/2 = 15.729 V/µs

Hence, we get Average Slew Rate (SR) of our system as 15.729 V/µs.

MEASUREMENT OF OUPUT VOLATGE SWING RANGE

Output Voltage Swing range is the difference between the maximum and the minimum

value that can be achieved by the output voltage.

Figure 8: Test Circuit to calculate Output Voltage Swing Range (OVSR)

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Waveform 5: Output Voltage Swing Range calculation

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After generating a symbol view of Figure 2, we can apply the test vector to this symbol view as shown in Figure 8 to calculate Output Voltage Swing Range (OVSR) of the circuit.

1. Apply a variable DC from 0 V to 1.8 V to the positive input terminals (INP).

2. Apply 1V DC to negative input terminal (INN) through a 1KΩ resistor.

3. Output terminal (OUT) is connected to the input terminal through a 10KΩ resistor.

4. Apply 6µA Reference Current Source (Iref) to input terminal (Ibias).

5. Apply 1.8V DC between VDD and GND terminal.

6. Check the result at the OUT terminal.

From waveform 5, the bottom plot is the derivative of the top plot. The derive value on the

bottom plot shows the rising point and falling point of the output when input values are

0.9003V and 1.045V respectively. Thus we can find out the same input voltage value on the top

plot and check out the output voltage value which is 64.52mV and 1.488V respectively. So,

Output Voltage Swing Range (OVSR) = Vo (max) – Vo (min)

= 1.488 V – 64.52mV = 1.42348 V

Hence, we get Output Voltage Swing Range (OVSR) of our system as 1.42348 V.

SUMMARY OF SIMULATED VALUES

PARAMETER VALUE

Differential Voltage Gain (Avd ) 80.13 dB

Output Voltage Swing Range (OVSR) 1.42348V

Slew Rate (SR) 15.729 V/µs

Common Mode Rejection Ratio (CMRR) 85.53 dB

Unity Gain-Bandwidth (GBW) 19.26MHz

Phase Margin, f(GBW) 60.6 o

Power Dissipation (Pdiss) 0.29754mW

Table 3: Simulated Results

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FINAL SCORE

Avd(dB) OVSR(V) SR(V/µs) CMRR(dB) GBW(MHz) PM(deg) Pdiss(mW)

Required ≥ 85 dB ≥ 1.4 V ≥ 15 V/µs ≥ 80 dB ≥ 15 MHz ≥ 60o ≤ 0.3mW

Actual 80.13 dB 1.42348V 15.729 V/µs 85.53 dB 19.26MHz 60.6 o 0.29754mW

Score 14.14 10 20 10 20 10 15

Table 4: Final Score for individual parameters

Score Formula = min[15,15(𝐴𝑣𝑑

85𝑑𝐵)] + min[10,10(

𝑂𝑉𝑆𝑅

1.4𝑉)] + min[20,20(

𝑆𝑅

15𝑉/𝑢𝑠)] +

min[10,10(𝐶𝑀𝑅𝑅

80𝑑𝐵)] + min[20,20(

𝐺𝐵𝑊

15𝑀𝐻𝑧)] + min[10,10(

𝑃𝑀

60)] + min[15,15(

0.3𝑚𝑊

𝑃𝑑𝑖𝑠𝑠)]

Final Score = 99.14

CONCLUSION

The developed Operational Amplifier using “Two-Stage Compensated Amplifier” design

met all the specifications except Gain. The gain has been sacrificed to avoid huge sizing of the

transistors.

REFERENCES

[1] B. Razavi, Design of Analog CMOS Integrated Circuits, New York: Tata-McGraw Hill, 2002.

[2] H. Lee, Class notes, EE6326 – Spring 2014, University of Texas, Dallas, 2014