osmania university be 2/4 electronic devices lab manual

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1. V-I CHARACTERISTICS OF SILICON AND GERMANIUM

DIODES AND MEASUREMENT OF STATIC AND DYNAMIC

RESISTANCES

AIM:

1. To determine the forward & reverse characteristics of a PN junction diode.

2. From the graph to determine static & dynamic resistances (forward and reverse)

APPARATUS:

Resistor 1K 1No

DC power supply (0-30) V 1No

DC Ammeter (0-30) mA, (0-100) A, (0-10) A 1No

Diode (1N4007, OA79) 1No

Digital multimeter (DMM) 1No

CIRCUIT DIAGRAM:

FORWARD BIAS (Ge):

2

REVERSE BIAS (Ge):

Expected Graph:

3

FORWARD BIAS (Si):

REVERSE BIAS (Si):

4

OBSERVATION:

Forward Bias Reverse Bias

Vi

(Volts)

VD

(Volts)

ID

(mA)

Vi

(Volts)

VD

(Volts)

ID

(mA)

Expected Graph:

5

PROCEDURE:

FORWARD BIAS (SI & GE)

1. Connect the circuit as shown in fig.1.

2. Change the forward bias voltage VI. Note down the corresponding voltage

across the diode (VD) and current through the diode (ID).

3. Now vary Vi such that the current ID is 1 mA, 2mA . 20 mA and

note down the corresponding voltage VD.

4. Plot the graph VD Vs ID.

REVERSE BIAS (Si & Ge)

1. Connect the circuit as shown in fig.2

2. Change the reverse bias voltage Vi from 0 to 20V in steps of 2 volts.

3. Note down the corresponding voltage across the diode (VD) and the current

through the diode (ID) (while note down the current voltmeter should be

disconnected).


RESULT:

1. The Forward and reverse characteristics of the PN diode is plotted.

2. Static resistance

i) Forward resistance = ___________________

ii) Reverse Resistance = ___________________

3. Dynamic resistance

i) Forward = ____________________

ii) Reverse = ____________________

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PRE LAB QUESTIONS:

1. Write the applications of PN junction diode?

2. Define PN junction diode.

3. What is the difference between Si and Ge diode?

4. Define Cut-in voltage of diode?

5. Define dynamic resistance of a diode?

6. Name the different types of Junction formations.

7

2. ZENER DIODE CHARACTERISTICS AND ITS APPLICATION

AS VOLTAGE REGULATOR

AIM:

1. To determine the forward & reverse characteristics of Zener diode.

2. From the graph to determine the break down voltage, static and

dynamic resistances. (Forward and reverse)

APPARATUS:

D.C. source (0-30) V 1No

Ammeter (0-20) mA 1No

Voltmeter (0-1) V, (0-20) V 1No

Variable resistance box 1No

Zener diode (1N4735, 1N4739) 1No

Resistor (1K) 1No

CIRCUIT DIAGRAM:

FORWARD BIAS

8

REVERSE BIAS

PROCEDURE:

FORWARD BIAS

1. Connect the circuit as shown in figure.

2. Change the forward biased voltage (Vi) and note down the corresponding

Voltage (VD) and current (ID).


REVERSE BIAS

1. Connect the circuit as shown.

2. Change the reverse voltage from 0 to 20V in steps of 2v and note down the

Voltage and current.

3. Plot the reverse characteristics VD Vs ID.

From the graph determine the breakdown voltage of the diode.

9

OBSERVATIONS:

Forward Bias Reverse Bias

Vin

(Volts)

IR

(mA)

VZD

(Volts)

Vin

(Volts)

IR

(mA)

VZD

(Volts)

EXPECTED GRAPHS: FORWARD CHARACTERISTICS & REVERSE

CHARACTERISTICS

RESULT:

1. The Forward and reverse characteristics of the Zener diode is plotted.

2. The breakdown voltage VZ = ____________________________

Static resistance

3. Forward resistance = ___________________

10

4. Reverse Resistance = ___________________

Dynamic resistance

5. Forward = ____________________

6. Reverse = ____________________

PRE LAB QUESTIONS:

1. Explain the phenomenon of Zener breakdown & avalanche breakdown?

2. Compare the characteristics of Zener diode with an ordinary PN diodes both

Forward and reverse biased conditions?

3. Why do you use an ammeter in Micro-amps range when a diode is used in reverse

bias?

4. Differentiate between Avalanche and Zener break down?

5. In what region of the characteristics you prefer to use a zener diode? Find out

Izmin and Izmax for the given configuration? Mention applications and specifications

of a zener diode?

VOLTAGE REGULATOR

*AIM:

To determine the line and load regulation for a given Zener

diode.

APPARATUS:

D.C. Source (0-30) V 1No.

Ammeter (0-30) mA, (0-20) mA 1Each.

Volt meter (0-20) V 1No.

Variable resistance box 1No.

Zener diode (1N4735, 1N4739) 1No.

Resistor (1K) 1No.

Connecting wires as per required

11

CIRCUIT DIAGRAM:

PROCEDURE:

LINE REGULATION:

1. Connect the circuit as shown in fig.

2. The zener diode is used under reverse biased condition.

3. The reverse bias voltage VI should be greater than the breakdown voltage. To

maintain this keep the load resistance RL constant at 5K.

4. Vary VI in steps of 2V from the breakdown voltage and note down the

corresponding total current (IT) and the load current (IL).

5. Determine IZ, zener current (IT - IL).

6. Plot Vi Vs V0 to get the line regulation characteristics.

LOAD REGULATION:

1. Adjust VI to slightly greater than the breakdown voltage and keep it constant.

2. Vary the load resistance RL such that current varies in steps of 1mA up to 10mA.

3. Note down the corresponding total current (IT) and load current (IL)

4. Determine IZ, zener current (IT - IL).

12

5. Plot IL Vs VO to obtain the load regulation characteristics.

OBSERVATIONS:

LINE REGULATION:

S.NO. Vin

(Volts)

IT (mA)

IR (mA) Iz=IT--IL VO (volts)

LOAD REGULATION:

S.NO. RL(K) IT(mA) IL(mA) IZ = IT - IL

VO(volts)

13

MODEL GRAPHS:

RESULT:

PRE LAB QUESTIONS:

1. Explain the phenomenon of Zener breakdown & avalanche breakdown?

2. Compare the characteristics of zener diode with ordinary PN diodes both forward

and reverse biased conditions?

3. Compare the characteristics of zener diode with an ordinary PN diodes both

Forward and reverse biased conditions?

4. Explain how a zener diode acts as a voltage regulator for line and load

regulations?

5. Why do you use an ammeter in micro-amps range when a diode is used in reverse

bias?

6. Differentiate between Avalanche and zener break down?

7. In what region of the characteristics you prefer to use a zener diode? Find out

Iz (min) and Iz( max) for the given configuration?

8. Explain the voltage stabilization with load in zener voltage regulator?

9. Mention applications and specifications of a zener diode?

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10. List the drawbacks of zener regulators.

3. DESIGN, REALIZATION AND PERFORMANCE EVALUATION

OF HALF-WAVE RECTIFIERS WITHOUT FILTERS AND WITH

LC & PI SECTION FILTERS

AIM:

To verify the ripple factor of half wave rectifier without filter and with filters.

APPARTUS REQUIRED:

AC Voltmeter (0-20) V 1 No.

DC Voltmeter (0-20)V 1 No.

DC Ammeter (0-100)mA 1 No.

Diodes (1N4007) 2 Nos

Transformer (Step down) 1 No.

Capacitors 100 F 2 Nos

DRB (Decade Resistance box) 1 No.

Inductors 2Nos

CIRCUIT DIAGRAM:

HALFWAVE RECTIFIER (WITHOUT FILTER)

15

PROCEDURE:

HALF WAVE RECTIFIER (WITHOUT FILTER)

1. Connect the circuit as shown in fig. with S1 open keep RL in maximum position.

2. Tabulate Vdc , Vac by varying the IL in steps of 5mA (The change of RL causes the

change of IL)

3. Observe the rectified output on CRO. Calculate ripple factor & compare with

theoretical value.

HALF WAVE RECTIFIER (WITHOUT FILTER):

MODEL GRAPHS:

16

CIRCUIT DIAGRAM:

HALFWAVE RECTIFIER WITH (LC) FILTER:

PROCEDURE:

HALF WAVE RECTIFIER WITH (Pi) SECTION FILTER

PROCEDURE (WITH FILTER):


2. Tabulate Vdc , Vac by varying the IL in steps of 5mA (The change of RL causes the

change of IL)

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theoretical value.

RESULT:

PRE LAB QUESTIONS:

1. Define regulation of half wave rectifier?

2. Define peak inverse voltage (PIV)?

3. Does the process of rectification alter the frequency of the waveform?

4. What are the applications of a rectifier?

5. What is the necessity of the transformer in the rectifier circuit?

6. What is mean by ripple and define ripple factor?

7. How capacitor helps to improve the ripple factor?

18

4. DESIGN, REALIZATION AND PERFORMANCE EVALUATION

OF FULL-WAVE RECTIFIERS WITHOUT FILTERS AND WITH

LC& PI SECTION FILTERS

AIM:

To verify the ripple factor of full wave rectifier without filter and with filters

APPARTUS REQUIRED:

AC Voltmeter (0-20) V 1 No.

DC Voltmeter (0-20) V 1 No.

DC Ammeter (0-100) 1 No.

Diodes (1N4007) 2 Nos

Transformer (Step down) 1 No.

Capacitors 100 F 2 Nos

Inductors 2Nos

DRB (Decade Resistance box) 1 No.

CIRCUIT DIAGRAM:

FULLWAVE RECTIFIER (WITHOUT FILTER)

19

PROCEDURE:

FULL WAVE RECTIFIER (WITHOUT FILTER)

1. Connect the circuit as shown in fig. with S1 closed keep RL in maximum position.

2. Tabulate Vdc, Vac by varying the IL in steps of 5mA (The change of RL causes the

change of IL)


theoretical value

TABULAR COLUMN:

S.NO. RL

(Ohms)

IL

(mA)

Vac

(Volts)

Vdc

(Volts)

Ripple

Factor

= Vac/dc

Theoretical

Ripple

Factor

20

FORMULAE USED:

FWR without filter ripple factor = 0.48 f=100HZ

CIRCUIT DIAGRAM:

FULLWAVE RECTIFIER WITH (LC) FILTER:

FULLWAVE RECTIFIER WITH () FILTER:

21

PROCEDURE:

FULL WAVE RECTIFIER (WITH FILTER)


2. Tabulate Vdc, Vac by varying the IL in steps of 5mA (The change of RL causes the

change of IL)


theoretical value

TABULAR COLUMN:

S.NO. RL

(Ohms)

IL

(mA)

Vac

(Volts)

Vdc

(Volts)

Ripple

Factor

= Vac/dc

Theoretical

Ripple

Factor

FORMULAE USED

For inductor filter ripple factor L

RL

23

For capacitor filter ripple factor LfCR34

1

For LC filter ripple factor CL24

1.

3

2

For -section filter ripple factor L

C

L

C

X

X

R

X 21 .

RESULT

PRELAB QUESTIONS:

22

1. Define regulation of full wave rectifier?

2. Define peak inverse voltage (PIV)?

3. Does the process of rectification alter the frequency of the waveform?

4. What are the applications of a rectifier?

5. What is the necessity of the transformer in the rectifier circuit?

6. What is mean by ripple and define ripple factor?

7. How capacitor helps to improve the ripple factor?

5. PLOTTING THE CHARACTERISTICS OF BJT IN COMMON

BASE CONFIGURATION, MEASUREMENT OF h-

PARAMETERS AIM:

To determine input and output characteristics and h-parameters of BJT in CB

configuration.

APPARATUS:

PNP transistor (BC 557/558) 1No

Dual regulated power supply (0-30) V 1No

Voltmeter (0-1) V 1No

Ammeter (0-20) mA 2Nos

Resistors (3.3K, 1K) each one

Connecting wires as per required.

CIRCUIT DIAGRAM FOR COMMON BASE:

23

PROCEDURE FOR COMMON BASE:

INPUT CHARACTERISTICS:

1. Connect the circuit as shown in the figure.

2. Keep VCB (output voltage) constant. (2 volt)

3. Vary VEE in steps and note down the corresponding VEB & IE.

4. Change the value of VCB and repeat the step 3 to get a set of characteristics.

5. Plot IE Vs VEB for different VCB.

OUTPUT CHARACTERISTICS:

1. The input current IE is kept constant (say 2mA) by adjusting VEE.

2. Vary VCB in steps and note down the corresponding IC.

3. Change the value of IE and for different values repeat step2.

4. Plot VCB Vs IC.

5. Plot IE Vs IC for constant. VCB using output characteristics.

OBSERVATIONS:

24


S.NO. VCB = 2V VCB = 4V VCB = 6V

VEB (V) IE (mA) VEB (V) IE (mA) VEB (V) IE (mA)


S.NO. IE = 2mA IE = 4mA IE = 6mA

VCB (V) IC (mA) VCB (V) IC (mA) VCB (V) IC (mA)

CB CONFIGURATION:

IE = Input current (Emitter current)

IC = Output current (collector current)

VEB = Input voltage (emitter to base voltage)

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VCB = Output voltage (collector to base voltage)

EXPECTED GRAPHS:



26

RESULT:

PRE LAB QUESTIONS:

1. Compare the input resistance, output resistance, voltage gain, current gain of

different transistor configurations

2. What is Early effect / base width modulation in transistors?

3. Why the input characteristics of transistor in CB-configurations originate from the

origin?

4. Explain the three different regions, Active, saturation and cut off, in the output

characteristics.

5. A CB stage is generally used as the first stage in a cascade. Why?

6. What is meant by common base configuration?

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7. Define current gain in CB configuration.

8. Give the Ebers Moll representation of a NPN Transistor?

6. PLOTTING THE CHARACTERISTICS OF BJT IN COMMON EMITTER CONFIGURATION AND MEASUREMENT OF

h-PARAMETERS AIM:

To determine input and output characteristics and h-parameters of BJT in CE

configuration.

APPARATUS:

NPN transistor (BC 547) 1No

Dual regulated power supply (0-30) V 1No


Ammeter (0-2000) A (0-20) mA each one

Resistors (47K, 1K) each one


28

CIRCUIT DIAGRAM FOR COMMON EMITTER:

PROCEDURE:


Connect the circuit diagram as shown in figure.

1. Keep VCE, the output voltage constant (say 2V).

2. Vary VBB in steps and note down the corresponding VBE & IB.

3. For different constant values connect the circuit.

4. Now to observe the input characteristics the output voltage VCE kept to be zero

and the value of input source VBB in varied. Such that the current IB increases in

steps of 50A. The respective values for VBE are noted. The same procedure is

repeated keeping VCE at 10V, graph IB Vs VEB is drawn and the h parameters

calculated.

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1. The voltage source VCE is varied keeping VBB and IB constant, keep IB at around

20A and vary the output voltage VCE in steps of 0.1V to 1V and after that

increase VCE in steps of 1V to 12V note down the current Ic.

2. Repeat the experiment for 30A and 40A values of IB. The h parameters can be

calculated from the graph.

CALCULATIONS:

INPUT CHARACTERISTICS

S.NO VCE = 2 V VCE = 4 V VCE = 6 V

VBE(V) IB (A) VBE (V) IB(A) VBE (V) IB(A)

30

OUTPUT CHARACTERISTICS

S.NO IB = 10 A IB = 20 A IB = 30 A

VCE(V) IC (mA) VCE(V) IC (mA) VCE(V) IC (mA)

EXPECTED GRAPHS:


31


RESULT:

*AIM:

1. To determine input & output characteristics of a transistor under common emitter

(CE) configuration.

2. To determine the h parameters (hybrid parameters) hie, hre, hfe and hoe from the

characteristics.

APPARATUS:

Regulated power supply (0-30) V 1No

D.C. Voltmeter (0-1) V 1No

32

Ammeters (0-200) A,(0-20) mA Each one

PNP transistor (BC 547) 1No

CIRCUIT DIAGRAM:

PROCEDURE:


1. Connect the circuit diagram as shown in figure.

2. Keep VCE, the output voltage constant (say 0.2V).

3. Vary VBB in steps and note down the corresponding VBE & IB.

4. For different constant value the circuit is connected as shown in the figure

carefully connecting the terminals. Now to observe the input characteristics the

output voltage VCE kept to be zero and the value of input source VBB in varied.

Such that the current IB increases in steps of 50A. The respective values for VBE

are noted. The same procedure is repeated keeping VCE at 10V, graph IB Vs VEB is

drawn and the h parameters calculated.


33

The voltage source VCE is varied keeping VBB and IB constant, keep IB at around

20A and vary the output voltage VCE in steps of 0.1V to 1V and after that increase VCE

IN steps of 1V to 10V note down the current Ic. Repeat the experiment for 30A and

40A values of IB. The h parameters can be calculated from the graph.

CALCULATIONS:

PARAMETERS VALUE DETERMINED

ieh

reh

feh

oeh

EXPECTED GRAPHS:


34


35

CALCULATIONS:

1. hie = input resistance (Ri) =

B

BE

I

V.. Ohms where VCE is constant

2. hre = Reverse Transfer ratio = ., where IB is constant

3. hfe = AC = forward current ratio =

B

C

I

I.. where VCE is constant

DC = IC/IB

4. hOe = Output dynamic admittance (1/r0) =

CE

C

V

I. where IB is

constant.

RESULT:

PRE LAB QUESTIONS:

1. CE stages are equally used as middle stages in a cascade why?

2. What is the phase relation between the input and output in a C.E. amplifier?

3. Mention advantages and disadvantages of CE configuration over CB & CC?

4. Explain why CE configuration is most popular in Amplifier circuits.

5. Show the Transistor current components for a forward biased emitter junction and

reverse biased collector junction?

6. Explain the terms ICBO, ICEO and VEBO ?

7. Can we inter change the collector and emitter terminals in a transistor?

8. What are typical h-parameter values for a transistor in CE configuration?

9. Why Hybrid parameters are called so?

10. Define the h-parameters?

11. What are the salient features of hybrid parameters?

36

12. Derive the equations for voltage gain, current gain input impedance and output

admittance for a BJT using low frequency h-parameter model for CE

configuration?

13. What are the advantages of using h-parameters?

37

7. PLOTTING THE CHARACTERISTICS OF JFET IN CS

CONFIGURATION AND MEASUREMENT OF

TRANSCONDUCTANCE AND DRAIN RESISTANCE

AIM:

1. To obtain the drain characteristics and transfer characteristics of the given

N-channel FET in CS configuration & to Determine Drain resistance (rd), Trans

Conductance (gm), Amplification factor ()

APPARATUS:

Resistor (680) 1 No

JFET Transistor (BFW 10/11) 1 No.

DC Power Supply (0-30) V 2 Nos

DC Ammeter (0-30) mA 1 No

DC Voltmeter (0-15) V 1 No

Silicon diode (BY 126) 1 No

CIRCUIT DIAGRAM FOR COMMON SOURCE CONFIGURATION:

38

PROCEDURE:

DRAIN CHARACTERISTICS:

1. Note the type no. of FET connected to the experimental board and trace the

circuit.

2. Make the circuit connections as shown in fig. Use milli-ammeter and electronic

voltmeter of suitable ranges.

3. For drain characteristics fix Vgs at some value, say 0 V. Increase the Vdd slowly in

steps and note down the Vds and Id for each value of Vdd. Now change Vgs to

another value (say 1V, 2V, 3V) and repeat the above. These ways take

readings for different Vgs voltages.

4. Plot the drain characteristics on the graph (between Id and Vds for fixed values of

Vgs).

TRANSFER CHARACTERISTICS:

1. Fix Vds at 4V. Increase the Vgg slowly in steps and note down Vgs and Id for each

set of Vds. Now change the Vds to another value, say 3V and repeat the above.

2. Plot the transfer characteristic on the graph (between Id and Vgs for fixed values of

Vds).

3. Determine the drain resistance, Trans conductance and amplification factor from

the above curves.

39

OBSERVATIONS:

DRAIN CHARACTERISTICS:

Vgs = 0 V Vgs = -0.5 V Vgs = -1 V

Vds (V) Id (mA) Vds (V) Id (mA) Vds (V) Id (mA)

TRANSFER CHARACTERISTICS:

Vds = 2 V Vds = 4 V Vds = 6 V

Vgs (V) Id (mA) Vgs (V) Id (mA) Vgs (V) Id (mA)

40

EXPECTED GRAPHS:

DRAIN CHARACTERISTICS WAVEFORM:

TRANSFER CHARACTERISTICS WAVEFORM:

41

CALCULATIONS:

1. Drain resistance rd = Vds / Id = ___________ K Ohms, where Vgs is constant

2. Trans conductance, gm = Id / Vgs =________ Ohms, where Vds is constant.

3. Amplification factor, = rdXgm = Vds / Vgs ___________ where Id is constant.

RESULT:

PRELAB QUESTIONS:

1. Name the different regions in case of transfer-mutual characteristics of FET.

2. What is the channel-length modulation in FET?

3. What is pinch-off voltage in FET?

4. Define the terms , gm, rd in FET.

5. What is the difference between depletion MOSFET and enhancement MOSFET?

6. What are the advantageous of FET over a BJT?

7. Compare JFET with a MOSFET. Mention at least two applications of a FET.

8. Why FET is a UNIPOLAR DEVICE?

42

8. BJT BIASING CIRCUITS

AIM:

Design different BJT biasing circuits for the given operating point and verify it

APPARATUS:


Transistor (BC 107) 1No.

DMM (Digital multimeter) 1No

Am meter (0-100)mA 1No


DRB (Decade resistance box) 3Nos


A) FIXED BIAS:

Given:

1. Transistor number: = (find from the data sheet for the given transistor)

2. Choose a given combination of conditions: VCC, ICQ, VCEQ, from below

a. VCC =10V/12V/15V/20V

b. ICQ = 50mA/75mA/100mA

c. VCEQ =5V/6V/10V/12V

43

GIVEN CONDITIONS:

For the given transistor (ensure ICQ 0.5ICmax, for any two or three combinations of

conditions above) Viz.,

1. VCC = 10V, ICQ=50mA, VCEQ=5V

2. VCC = 10V, ICQ=100mA,VECQ=5V

3. VCC = 12V, ICQ = 75mA,VCEQ = 6V

4. VCC = 12V, ICQ = 100mA, VCEQ = 7.5V

CIRCUIT DIAGRAM:

Find the values of RB & RC and verify (by actual measurement) the values of

ICQ,IBQ,VBEQ.

44

Assume for silicon transistor V BE(act) = V BEQ =0.7V

DESIGN STEPS:

Step 1:

For the given combinations of specifications (Viz., chosen: VCC=10v , ICQ =100

mA & VCEQ =5v) find RC and RB . Using IC/IB= and & writing the output loop

equation, gives

VCC = ICQRC+VCEQ i.e., ICQ = (VCC-VCEQ)/RC

i.e., RC = (VCC VCEQ)/ICQ IBQ = ICQ/,

RB VCC/IB , (since RB =(VCC-VBEQ)/IB VCC/IB, as VBEQ

45

OBSERVATIONS:

S.No Design Values

(Determined)

Combination of

Conditions chosen

Values

observed

SI

RC in () RB in () VCC ICEQ VCEQ ICQ VCEQ

B) COLLECTOR TO BASE BIAS:

CIRCUIT DIAGRAM:

46

DESIGN STEPS:

Choose the conditions: VCC=12v, ICQ=75mA, VCEQ=6v

Step 1:

Writing the output loop equations, we have:

VCC = (IC+IB) RC+VCE

Find the values of RC and RB using = IC/IB

RC (VCC-VCEQ)/IC

RB = (VCEQ-VBE)/IB

For the given combinations of specifications find RC, RB and verify the values of ICQ

And VCEQ from measurements

- Find also

SI = (1+)/(1+(RC/RC+RB))

Step 2:

Repeat step 1 for other combination of conditions also

OBSERVATIONS:

S.No Design Values

(Determined)

Combination of

Conditions chosen

Values

observed

SI

RC in RB in VCC ICEQ VCEQ ICQ VCEQ

47

C) SELF BIAS:

CIRCUIT DIAGRAM:

Self bias circuit is shown below

DESIGN STEPS:

Step 1:

- Choose the conditions: VCC = 15v, ICQ = 2mA, VCEQ = 7.5v

- Writing the mesh equations

VCC = ICQ (RC+RE) +VCEQ

(RC+RE) = (VCC-VCEQ)/ICQ

- For given VCEQ, ICQ (assuming Rc = 2.7K) find Re

- Calculate RBB & find R2 = , R1 = , Rth = R1R2/(R1+R2).

48

- Find

Vth = VCCR2/ (R1+R2) and

SI = (1+)/ (1+(Re/(Re+Rth)))

OBSERVATIONS:

S.NO. Design Values

(Determined)

Combination of

Conditions chosen

Values

observed

SI

R1 in R2 in RC in RB in VCC ICEQ VCEQ ICQ VCEQ

RESULT:

PRELAB QUESTIONS:

1. Define the term Biasing?

2. List different types of stability factors?

3. What is the need of Biasing?

4. Which method of Biasing is more suitable in most applications?

49

9. FET BIASING CIRCUITS

AIM:

Design different FET biasing circuits for the given operating point and verify it

APPARATUS:


JFET (BFW 11) 1No.

DMM (Digital multimeter) 1No



DRB (Decade resistance box) 3Nos


FIXED BIAS:

CIRCUIT DIAGRAM:

50

DESIGNING EQUATIONS:

GGG RIV From the circuit 0 GSGG VV

2

1

P

DSSDV

VGSII

from the output loop

0 DDDDDS VRIV

DDDDDS RIVV

OBSERVATIONS:

S.NO. Design Values

(Determined)

Combination of

Conditions chosen

Values

observed

SI

RD in RG in VDD IDQ VDSQ IDQ VDSQ

51

SELF BIAS:

CIRCUIT DIAGRAM:

The drain voltage, DDDDD RIVV

SDDS VVV

SDDDDD RI-RI-V

)( SDDDD RRIV

SDSDSGGGS RIRIVVV 0

52

OBSERVATIONS:

S.NO. Design Values

(Determined)

Combination of

Conditions chosen

Values

observed

SI

RD in RG in VDD IDQ VDSQ IDQ VDSQ

VOLTAGE DIVIDER BIAS:

CIRCUIT DIAGRAM:

- Voltage Divider Bias Circuit is Shown Below

53

DESIGNING EQUATIONS:

The gate voltage DDGG VRR

RV

21

2

and 21

21

RR

RRRg

The bias line satisfies the equation SDGGGS RIVV

DDDDD RI-VV

OBSERVATIONS:

S.NO. Design Values

(Determined)

Combination of

Conditions chosen

Values

observed

SI

R1 R2 Vdd Idq Vdsq Idq Vdsq

RESULT:

PRELAB QUESTIONS:

1. Define the term Biasing.

2. What is the need of Biasing?

3. Which method of Biasing is more suitable in most applications?

54

10. COMMON EMITTER BJT AMPLIFIER AND MEASUREMENT OF GAIN,

BANDWIDTH, INPUT AND OUTPUT IMPEDANCES

AIM:

To find the following parameters of Common Emitter amplifier

1. Frequency response

2. Band width

3. Input impedance

4. Output impedance

APPARATUS:

Transistors: BC 107 1No.

Resistors:

47 K 1 No.

4.7 K 2 Nos

10 K 1 No.

2.7K 1 No

Capacitors:

1 F /25V 2 Nos

100 F/25V 1 No.

DC Power Supply 1 No

Signal Generator 1 No

Cathode ray Oscilloscope 1 No

Decade Resistance Box (DRB) 1 No.

Grew board 1 No.


55

DESIGN:

Choose VCC = : R1 = ICQ =

R2 = VCEQ =

VBB = R2 /(R2 + R1) X VCC = - - - - - - -

VE = VBB - VBE =

VE / ICQ = RE

VCEQ = VCC (RC + RE) ICQ

Calculate RC =

Input Impedance = (R1 R2) hie

Out put impedance = RC

Voltage gain AV = V0 / Vi = -hfe RC / hie

56

CIRCUIT DIAGRAM:

PROCEDURE:


2. Find the maximum signal handling capacity. For this keep the frequency of input

signal at 5 kHz and increase the amplitude of input signal till the output gets

distorted. Then that maximum value of input signal is maximum signal handling

capacity.

3. Now keep the amplitude of input signal less than the maximum signal handling

capacity and vary the frequency in the range 10 Hz to 1 MHz. And for each and

every frequency find the corresponding output. Find the gain of the circuit at

different frequencies.

4. Make a plot of gain in dB Vs frequency and the plot is called frequency response

curve. Find the bandwidth from the graph.

57

5. For finding the input impedance of the circuit keep the frequency of input signal

at 1 kHz find the values of Vs and Vi. Input impedance can be calculated from the

formula given below.

6. For finding the output impedance of the circuit initially first find the output

voltage without connecting any load. After that connect decade resistance box at

output terminals and vary its resistance till output voltage becomes half.

7. Then that resistance is the output impedance of circuit

OBSERVATIONS:

1. Maximum signal handling capacity =

2. Amplitude of input signal applied VI =

(Maintained Constants for all input frequency settings)

S.NO. Frequency

(Hz)

O/P voltage V0 Gain V0/ VI Gain in dB

20 log V0 / VI

FORMULA:

Band width (BW) = fH - fL

58

Input impedance =

Where VNL = No load voltage

VL = Load Voltage

MODEL WAVEFORMS:

INPUT WAVEFORM:

OUTPUT WAVEFORM:

59

EXPECTED GRAPH:

A graph is plotted between f on X axis and 20 log V0. / VI on Y-axis. It will be

as shown figure BW = fH f L

RESULT:

1. Band width obtained from the circuit =

2. Input impedance of the circuit =

3. Output impedance of the circuit =

PRE LAB QUESTIONS:

1. Why the circuit is called Single Stage RC coupled Amplifier?

2. In which frequency range this circuit is used?

3. Indicate bypass capacitor and coupling capacitor in the circuit?

4. Why the gain of the circuit decreases in low frequency region and high frequency

region?

5. How this circuit acts in low frequency region and high frequency region?

60

11. Common Source FET Amplifier and measurement of Gain,bandwidth,input

and output impedances

AIM:

To find the following parameters of CS amplifier


2. Band width

3. Input impedance

4. Output impedance

APPARATUS:

JFET (BFW 11) 1No.

Resistors:

1 K 1 No.

10 K 2 Nos

470 K 1 No.

Capacitors:

4.7F/16V 2 Nos

47 F/25V 1No.

DC Power Supply 1 No


Cathode ray Oscilloscope 1 No

Decade Resistance Box 1 No

Grew board 1 No.

61

DESIGN:

V DD = _____

VGSQ = _____

IDQ = _____

From VGSQ = --- IDQRS. Calculate RS

And VDS = VDD - ID (RS + RD)

Choose VDS, find RD

Now I/P impedance Zi = RG

O/P impedance Z0 = rd || RD

Voltage gain, AV = Vo / Vi = -gm (rd || RD )

CIRCUIT DIAGRAM:

62

PROCEDURE:

1. As per the design specifications, connect the circuit as shown

2. Set the frequency of I/P signal at 5KHz and increase the amplitude, till O/P

gets distorted. The value of I/P signal is maximum signal handling capacity.

3. Set the I/P signal at a constant value, less than the maximum signal handling capacity, vary frequency in the range 10Hz to 1MHz and find O/P voltage for

each and every frequency.

4. Calculate voltage gain at each and every frequency.

5. Plot the frequency versus gain and determine fH and fL.

6. Calculate bandwidth fH - fL.

7. Procedure for measuring input impedance: Set the signal generator frequency

at 2KHz and measure Vs and Vi. Then Ii = Vs - Vi / RS.I/P impedance = Vi / Ii

8. Procedure for measuring O/P impedance: Open the O/P circuit and measure

voltage (V open) across O/P using CRO. After connecting DRB at O/P terminals,

vary the resistance to make the O/P (Vopen) become to half of it value. Then

existing resistance in DRB is its O/P resistance.

63

S. NO. Frequency (Hz) O/P voltage (V0) Gain (V0/ VI) Gain in dB

20 log (V0 / VI)

OBSERVATIONS:

1. Maximum Signal handling capacity=

2. Amplitude of input signal applied Vi = ------------------- V

(Maintained Constant for all input frequency settings)

FORMULA:

Band width (BW) = fH fL

Input impedance =

64

Where

VNL = No load voltage

VL = Load Voltage

EXPECTED WAVEFORM:

INPUT WAVEFORM:

OUTPUT WAVEFORM:

65

EXPECTED GRAPH:

A graph is plotted between f on X axis and 20 log V0 / VI on Y-axis. It will be

as shown in figure.

Bandwidth(BW) = fH f L

66

RESULT:

1. Frequency response curve is plotted.




PRELAB QUESTIONS:

1. What type of biasing is used in this circuit?

2. Draw the AC equivalent circuit of FET amplifier.

3. Why this circuit is called Single Stage RC Coupled FET amplifier?

4. Why the gain of the circuit decreases in low frequency and high frequency

regions?

5. How this circuit acts in LF and HF regions?

67

12. EMITTER FOLLOWER/SOURCE FOLLOWER CIRCUITS AND MEASUREMENT OF GAIN,BANDWIDTH,INPUT AND

OUTPUT IMPEDANCES AIM:

To find the following parameters of emitter follower or Common Collector

amplifier


2. Band width

3. Input impedance

4. Output impedance

APPARATUS:

BC 107 (Transistor) 1No.

Resistors:

470 K 1 No.

12 K 2 Nos

3.3 K 1 No.

1K 1 No.

Capacitors:

10 F 2 Nos.

10 kp F 1 No.

DC Power Supply (0-32V) 1 No


Cathode ray Oscilloscope (CRO) 1 No.

Decade Resistance Box (DRB) 1 No.

Bread board 1 No.

68

CIRCUIT DIAGRAM:

PROCEDURE:


2. Find the maximum signal handling capacity. For this keep the frequency of

input signal at 5 kHz and increase the amplitude of input signal till the output

gets distorted. Then that maximum value of input signal is maximum signal

handling capacity.

3. Now keep the amplitude of input signal less than the maximum signal

handling capacity and vary the frequency in the range 10 Hz to 10 MHz. And

for each and every frequency find the corresponding output.

4. Find the gain of the circuit at different frequencies. Make a plot of gain in

dB Vs frequency and the plot is called frequency response curve.

5. Find the bandwidth from the graph.

6. For finding the input impedance of the circuit keep the frequency of input

signal at 1kHz find the values of Vs and Vi. Input impedance can be

calculated from the formula given below.

7. For finding the output impedance of the circuit initially first find the output

voltage without connecting any load. After that connect decade resistance box

at output terminals and vary its resistance till output voltage becomes half.

Then that resistance is the output Impedance of circuit

69

OBSERVATIONS:

1. Maximum signal handling capacity =

2. Amplitude of input signal VI =

(Maintained Constants for all input frequencies)

S.No. Frequency (Hz)

Output voltage( V0 ) Gain V0/ VI Gain in dB

20 log V0 / VI

70

EXPECTED WAVEFORM:

INPUT WAVEFORM:

OUTPUT WAVEFORM:

FORMULAE:


Input impedance =

71


VL = Load Voltage

EXPECTED GRAPH:

A graph is plotted between f on X axis and 20 log V0. / VI on Y-axis. It will be

as shown figure

RESULT:




PRELAB QUESTIONS:

1. Why the circuit is called emitter Follower?

2. What is the Voltage Gain of the Circuit?

3. Where the circuit is widely used?

4. How are the inputs and output impedances?

72

*AIM:

To find the


2. Band width

3. Input impedance and

4. Output impedance

APPARATUS:

JFET (BFW 11) 1No.

Resistors:

1 K 1 No.

10 K 1 No.

10 K 1 No.

470K 1 No.

Capacitors:

1 F 1 No.

0.01 F 1No.

47 F/40V ----- 1 No.

DC Power Supply ----- 1 No.

Signal Generator ----- 1 No.

Cathode ray Oscilloscope ----- 1 No.

Decade Resistance Box ----- 1 No.

Bread board ----- 1 No.

73

CIRCUIT DIAGRAM:

EXPECTED WAVEFORM:

INPUT WAVEFORM:

OUTPUT WAVEFORM:

74

PROCEDURE:

1. As per the design specifications, connect the circuit as shown. Set the

frequency of I/P signal at 5KHz and increase the amplitude, till O/P

get distorted. The value of I/P signal is maximum signal handling capacity.

2. Set the I/P signal at a constant value, less than the maximum signal handling

capacity,

3. Vary frequency in the range 10Hz to 1MHz and find O/P voltage for each

and every frequency.

4. Calculate voltage gain at each and every frequency.

5. Plot the frequency versus gain and determine fH and fL.

6. Calculate bandwidth fH - fL.

7. Procedure for measuring input impedance: Set the signal generator

frequency at 2KHz and measure Vs and Vi.

Then Ii = Vs - Vi / RS.

I/P impedance = Vi / Ii

8. Procedure for measuring O/P impedance: Open the O/P circuit and

measure voltage (V open) across O/P using CRO. After connecting DRB

at O/P terminals, vary the resistance to make the O/P (Vopen) become to

half of its value. Then existing resistance in DRB is its O/P resistance.

75

OBSERVATIONS:

1. Max. Signal handling capacity =

2. Amplitude of input signal applied Vi = __________ mV

(Maintained Constant for all input frequency settings)

S. No. Frequency f O/P voltage V0 Gain V0/ VI Gain in dB

20 log V0 / VI

(1)

(2)

(3)

(4)

FORMULAE:


76

Input impedance =


VL = Load Voltage

EXPECTED GRAPH:

A graph is plotted between f on X axis and 20 log V0 / VI on Y-axis. It will be

as shown in figure.

BANDWIDTH(BW) = fH f L

RESULT:




77

PRELAB QUESTIONS:

1. Write the applications of Source follower/Emitter follower.

2. Why do we call it as Source follower/ Emitter follower?

3. What is the phase difference between input and output in CC?

78

13. CHARACTERISTICS OF SPECIAL DEVICES-UJT AND SCR

AIM:

1. To study the emitter characteristics of UJT.

2. To study the characteristics of SCR.

APPARATUS:

UJT 2N2646,

SCR

Regulated power supplies (0 30V), (0-300V) 1 No.

Resistor 1 K, 680, 470 1 No.

DC Ammeters 2 Nos.

Voltmeters 1 No.

CIRCUIT DIAGRAM OF UJT:

79

PROCEDURE:


2. Keep VBB = constant find the emitter current IE & VE varying for different

3. Repeat step 2 for different VBB & find corresponding IE by varying VEE.

TABULAR COLUMN:

VBB = 5V VBB = 10V VBB = 15V

VE IE VE IE VE IE

CALCULATIONS:

RBB = RB1 + RB2

80

BB

B

BB

B

R

R

RR

R1

21

1

BBBRR

1

12 BBBBRRR

BBPVV

EXPECTED GRAPH:

81

RESULT:

PRELAB QUESTIONS:

1. Why name of the device is UJT?

2. Can the intrinsic stand off ratio of UJT be changed? If yes, how?

3. Can UJT replace BJT? Justify!

4. What will happen if a.c. voltage is applied between emitter and base1 of UJT?

5. What is the importance of negative resistance region of UJT?

6. What will happen if intrinsic stand off ratio of UJT is doubled?

7. Enlist two applications of UJT.

8. Is it possible to use UJT to trigger SCR? If yes, draw the necessary circuit diagram.

9. From the characteristics obtained calculate the slope of negative resistance part of

Characteristics .why it is signify?

*SILICON CONTROL RECTIFIER CHARACTERISTICS

SCR CIRCUIT DIAGRAM:

82

PROCEDURE:


2. Fix VGK to a desired value and note the values of anode current IA by

varying the anode voltage VA & IG.

3. Repeat the step 2 for different values of IG.

TABULAR COLUMN

IG = 5A IG = 10A IG = 15A

VAK (V) IA (mA) VAK (V) IA (mA) VAK (V) IA (mA)

EXPECTED GRAPH:

83

RESULT:

The characteristics of a SCR are obtained.

PRELAB QUESTIONS:

1. Give the symbol and constructional diagram of SCR.

2. What is the working principle of SCR.

3. What are the Applications of SCR.

4. How to change the conduction angle in the output waveform

84

14. CHARACTERISTICS OF PHOTO DIODE AND TUNNEL DIODE

AIM:

To plot photo diode characteristics and to determine dynamic resistance

APPARATUS:

Photo diode 1No

Voltmeter (0 15V) 1No


RPS (0-30) V 1No

Light source resistor 1K. 1No

CIRCUIT DIAGRAM:

85

OBSERVATIONS:

LUMINOUS INTENSITY = LUMINOUS INTENSITY =

Vd(V) Id(mA) Vd(V) Id(mA)

PROCEDURE:

1. Connect the circuit as shown in fig.

2. Increase RB voltage insteps of 0.5V and note down corresponding Vd & Id.

3. Increase the intensity of light and note down corresponding Vd & Id.

4. For various intensities plot the graph Id Vs Vd.

86

EXPECTED GRAPH:

ID Luminous Intensity

(A)

Dark Current

Reverse Voltage (V).

RESULT:

PRELAB QUESTIONS:

1. What is the principle of operation of photodiode?

2. What are the applications of photodiode?

3. Give the symbol and characteristics of photodiode.

87

*AIM:

To study the characteristics of a tunnel diode.

APPARATUS:

Photo diode 1No

Voltmeter (0 15V) 1No


RPS (0-30) V 1No

Light source resistor 1K. 1No

CIRCUIT DIAGRAM:

88

PRELAB QUESTIONS:

1.What is the concept of Tunneling?

2. What are the applications of Tunnel diode.

3.Name the different regions of operation in tunnel diode.

osmania university be 2/4 electronic devices lab manual

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