overlay metal/ inter-dielectric layers/bcb/cu bump workshop information... · 2015-02-03 ·...

Overlay Metal/ Inter-dielectric layers/BCB/Cu BumpWorkshop

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Contributors

Contributions– Jerry Beene Sr. Photolithography Engineer – Roberta Hawkins Sr. Photolithography Engineer– Amy Zhou Sr. Photolithography Engineer– HT. Chen Sr. EBEAM Engineer– Martin Ivie Sr. Photolithography Engineer– Harold Isom Engineering Manager

Confidential & Proprietary

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Agenda

Agenda– Overlay Metals and Interconnects

• Process Flow• MET0-

– Evaporation and Liftoff– PVD Sputtering and Electroplating

• NIT1-Interlayer Dielectric (ILD)– PECVD

• MET1-MIM CAP– Etching

DryWet

• NIT2- CAP– PECVD

• MET2-Air Bridge• Final Over-Coat

– BCB– Copper Bump

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Overlay Metal-Interconnects and Dielectrics

Overlay metals may be used to increase metal conductivity or to form other features such as transmission lines, inductors and bottom capacitor plates. Dielectric films may be applied for encapsulation or capacitor formation. A second or even third metallization can be used to form other connections.

– Requirements• High electrical conductivity, good adhesion, effectiveness as a diffusion

barrier, effectiveness as an etch stop.• High electrical conductivity can be met with four metals, gold, aluminum,

silver and copper.Dielectric films are used for encapsulation, for capacitor dielectrics and crossover insulators.

– Requirements• There are generally just a couple of dielectrics used in GaAs Processing:

Si3N4, and SiO2 and sometimes Ta02.• Si02 have a lower dielectric constant and are good cross-over, Si3N4

because of the higher dielectric constant are better suited for capacitors.

Williams, Modern GaAs Processing Methods Confidential & Proprietary

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Process Flow

Ohmic/Alloy

Isolation

Wide Recess

Gate Pattern

Gate Fabrication

Nitride 0

TaN Resistors

Metal 0

Nitride 1

Cap Top Plate

Nitride 2

Metal 1

Air Bridge Post

Metal 2

Protective Overcoat

Saw Street Etch

DC Probe

Wafer Thinning

Via Etch

Backside Metal

Backside Plate

RF Probe

Chip Separation

Final Visual

*

*

*

*

*

*

* Optional Steps

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MET0 (First layer Metal)

1st-Metal (MET0)

Sputter TiWN /Ti Barrier

Sputter Ti//Pt/Au/Ti Seed layer.

Coat/Align/Develop to Pattern 1st-Metal

ADI Inspection

ASH Descum to prepare for Plate

Gold-Plate, Resist-Strip, Seed-Deplate and Clean

(This can also be a evaporated metal)

ACI Inspection

Measure Metal CD’s

Barrier/Seed Etch (if not evaporated)

TiWN/Ti Barrier strip in LAM590

AEI Inspection

Resist Strip

Deveil to remove post-etch Polymers

Spin/Rinse/Dry

ACI Inspection


Provides metal interconnect; overlay ohmic metal, underlay plating (increases sheet conductivity). Used to contact TaN resistors. Can also be used as the bottom plate in the capacitor.First Layer metals can use a variety of deposition methods: Sputtering (PVD), Evaporation, PECVD and electroplating.

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Methods for Deposition

Different Methods– Growth

• Thermal Oxidation (SiO2), Titanium Nitride– Spin on Films

• Spin on Dopants (SOD), Spin on Glass (SOG)– Deposition

• Chemical Vapor Deposition (CVD)– APCVD (atmospheric pressure)– LPCVD (low pressure)– PECVD (plasma enhanced)– Epitaxial Growth (single-crystal films)

• Physical Vapor Deposition (PVD)– Sputter– Evaporation

• Electroplating


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PVD-Evaporation

Physical Vapor Deposition (PVD) –Evaporation:

– Vaporize a metal using thermal energy @ low pressure

An Evaporation system includes the following:

– High vacuum chamber and high vacuum components

– Evaporation source: Filament, Electron beam, or Flash hot plate

Evaporation is Inferior to Sputtering:– Difficult to do alloys– Step coverage– Adhesion


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Evaporation /Lift-Off

Evaporated metal is deposited on top of the resist rather than using the resist as an etch mask.Requires an overhang to form a break between the metal on the resist and substrate.Called lift-off because if the wafer is soaked in solvent, the resist will dissolve and metal is left free to lift-off.

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Components of a Evaporator


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Evaporation and Liftoff


Source : Temescal

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Common Lift-Off Methods

Method Advantages Disadvantages

Positive or Negative ToneBi-layer High resolution

1st layer planarizes.Expensive material.Requires non standard EBR chemistry.Requires high temp bake.

AZ-5214E-IR Single coat Temperature sensitive. Requires UV flood expose.

Etch assisted High resolution Unusual for substrate to allow etching

Positive OnlyDeveloper Soaks Lip at top allows thick lift-offs Does not work for all resists.

Negative OnlyAZ NLOF High resolution

Single coatDifficult to strip

Ammonia bake Requires specialized oven for ammonia.

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Simple Bi-layer

Coat PMGI and hot plate bake

Develop

Stepper expose

Coat resist and hot plate bake

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Bi-layer for Undercut Control

Coat PMGI and hot plate bake

Develop PMGI

Stepper expose


Develop resist

DUV expose

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AZ5214 Partial Image Reversal (Positive)

Coat and hot plate bake

Short flood expose and bakeTo crosslink exposed resist

Stepper expose

Develop

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AZ5214E Image Reversal (Negative)


Stepper expose

Cross linking bake

Develop

UV Flood Expose

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Etch Assisted lift-off


Develop

Stepper expose

Etch

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Developer Soak

Develop

Stepper expose


TMAH Soak

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nLOF Lift-off


Stepper expose

Cross linking bake

Develop

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Ammonia Bake


Stepper expose

Ammonia bake

Develop

UV Flood Expose

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Lift-Off Challenges

The processes tend to be complicated.Small resist lines can suffer adhesion loss due to the undercut.The degree of undercut can be difficult to monitor without cross section.Evaporated metal will be shifted within the resist opening as distance is increased from the wafer center.

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Sputtering


Process Concerns with Sputtering:– Hillock Growth: Excess heat generated by

the plasma can cause hillock growth, grains which relieve the stress in the film by growing upward.

– Poor Step Coverage due to physical nature of the process.

– Contamination

Metal Step Coverage

Deposition 231000A Ti Deposited in Back Via (pre-plate)

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PVD and Sputtering

Physical Vapor Deposition (PVD) - Sputtering:– Use plasma energy to blast small

fragments from a target.– Purely physical process, no chemical

reaction occurs.– Reverse of physical etching (sputter etch),

used at the beginning of the sputter process to remove native oxides.

Where is Sputtering Used?– Because it is a physical process, almost

any material can be sputtered (CVD is limited to materials that can be chemically created).

– In III-V processing, sputtering is most often used to deposit seed metals before electroplating Interconnect or create barrier layers:


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Electroplating

There are two main gold plating baths in industry today, cyanide based and non-cyanide baths containing either sulfite or thiosulfate as the primary electrolyte. The cyanide bath is by far the dominant of the two. Gold (Au) is ionized in the solution at the +1 oxidation state. The gold is plated using the wafer as a cathode attracting the positively charged gold ions to the surface and reducing them to Au(s). Operation of the gold electroplating bath involves constant monitoring of key process parameters, which include gold reflectivity, film stress, and film thickness.


Advances in Gold Metallization at Motorola's Compound Semiconductor Fab (CS1) Chad M. Becker, William Rummel*, Dr. Paul Ocansey

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Plating Issues


•Problem Description– The haze comes from two

sources: Incomplete deplateleaving behind Au islands and un-removed TiW from the barrier wet etch

– Au Islands create leakage paths and have created scrapped material. This is the same failure as EMODE which resulted in the loss of 180 wfrs.

– TiW residue is not known to cause yield loss, but cannot be distinguished between Au islands.

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Cause and effect Diagrams for Plating Issues


Source: Paul Ocansey

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NIT1 (First Interlayer Dielectric, ILD)

Interlayer dielectrics (ILD) can be used for a variety of applications such as encapsulation, insulating two metalization layers (MIMS). As well as capacitors Key characteristics : Dielectric constant is dependent on deposition method and parameters. If a dielectric film is too thin, there will be a larger amount of pinholes if it is too thick then the parasitic capacitance will increase.The formation of the film can affect saturation current, breakdown voltage as well as other parameters.


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PECVD (ILD’s)

Two primary PECVD Chemistries– TEOS

• Source is Liquid TEOS...Si(OC2H5)4

• Used exclusively to deposit SiO2.• Most common.

– Silane• Source gas is Silane...SiH4

• Used to deposit SiO2 and Si3N4.

Deposition is carried out in six general steps1. Molecules are broken down into their

constituent atoms to form reactant radicals.2. Reactants diffuse to the surface of the wafer.3. Reactants are adsorbed on the wafer

surface.4. Chemical reaction starts as reactants meet.5. By-products are desorbed.6. Unreacted effluent and by-products are

pumped away.


PECVD Mechanism

Ionization:1. e

-+ AB AB

++ 2e

-

Dissociation:2. e

-+ AB A + B + e

-

Excitation / Relaxation:3. e

-+ A A

*+ e

-

4. A*

A + PhotonWhere “AB” = a common diatomic molecule and “ * ” indicates an excited state.

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MET1-MIM CAP


MET1

Sputter TiWN Barrier

Sputter Ti/Au Seed layer.

Coat/Align/Develop to Pattern 1st-Metal

ADI Inspection

ASH Descum to prepare for Plate

Gold-Plate, Resist-Strip, Seed-Deplate and Clean

(This can also be a evaporated metal)

ACI Inspection

Measure Metal CD’s

Barrier/Seed Etch (if sputtered/Plated)

TiWN/Ti Barrier strip in LAM590

AEI Inspection

Resist Strip

Deveil to remove post-etch Polymers

Spin/Rinse/Dry

ACI Inspection

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Etching

Etching removes material through physical or chemical methodsWhen photoresist or other masking medium is used, etching can replicate this pattern into the film.In III-V, etching is used to generate patterns and remove various materials such as:

– Silicon Nitride– EPI Layers– Silicon dioxide of various forms (thermal, LPCVD and PECVD)– Metals– GaAs, GaN, AlN, AlGaAs

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Dry Etching


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Dry Etching


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Etch Requirements

Must Control the amount of material being removedControl key parameters that control replication– Dimensions (Critical dimensions)– Selectivity (which material is etched)– Minimize defects

Control the amount of damage to underlying materialControl the amount of un-etched, veils, or other material left on the etched wafer

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Etching

What is Etching?:

– 1. The PERMANENT part of the patterning sequence.

Transfers the pattern in the photoresist into the underlying layer.

– 2. Removal of a “blanket” film (no patterning) whose purpose is done

sacrificial oxide

nitride used to define transistor active areas

Two Main Types of Etch Processes:– 1. Wet Chemical Etching– 2. Plasma (or “Dry”) Etching


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Wet Etching

Wet Etching– Two basic mechanisms occur:

• Diffusion-limited or mass transport etching

• Reaction-rate/surface limited or kinetically limited etching

– Almost all GaAs etchants first oxidize the surface and then dissolve the oxide, removing some of the gallium and arsenide atoms

• H2SO4-H2O2-H20 is a good example

– Almost all wet etches are isotropic


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Important Characteristics of Etching


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Capacitor Dielectric /Etch Stop/Lift off

Capacitor Dielectric and Etch-Stop Metal Dep.800Å Si3N4 Dep (Capacitor Dielectric)Coat/Align/Develop to define Etch-Stop Metal on CapacitorADI InspectionEvaporate Ti/Au film for Etch-stop and Seed-Layer(This can also be plated)

Metal Etch-Stop Lift-OffLift-off unwanted Etch-stop/Seed metal with resist.Spin/Rinse/DryAEI Inspection


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PECVD-ILD’s

Plasma-enhanced chemical vapor deposition (PECVD) is a process used to deposit thin films from a gas state (vapor) to a solid state on a substrate. Chemical reactions are involved in the process, which occur after creation of a plasma of the reacting gases. The plasma is generally created by RF (AC) frequency or DC discharge between two electrodes, the space between which is filled with the reacting gases.Collisions occur creating numerous species…electrons atoms, cations, and free radicals. Free radicals are very reactive and are the primary reason for PECVD. Collisions are either elastic or inelastic. Inelastic collisions are of the most value because it is in these that the following reaction types occur. A. Ionization B. Dissociation C.Excitation


Parallel Plate Reactor

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Applied Materials P5000


Upper Electrode

Bottom Electrode“Susceptor”

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Sequence of Events


1. Wafer is placed in chamber on Lift Pins. 2. Robot retracts from chamber.3. Chamber slit valve closes.2. Lift pins lower wafer on to the susceptor.3. Reactant gases flow in through the Lid

Assembly.4. Time is allowed for gas flow stabilize.5. RF power is turned on and plasma is

ignited.6. Thickness is determined by the amount of

time.7. RF power and gases are turned off.8. Chamber is pumped down to remove

residual gas.9. Lift pins raise wafer off of susceptor.10. Robot removes wafer from chamber.

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MET2-Air Bridge


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Air Bridge Requirements

The 1st resist layer must be thermally stable enough to withstand the 2nd layer processing. Any movement will damage the seed metal.

• The resist can be stabilized by a hard bake, electron cure, or by using a high Tg negative resist.

Stepper alignment marks must have openings in the 1st resist or they will be invisible after the seed metal.

The 1st resist layer should not have a retrograde profile or a “lip.”

• What’s good for lift-off is bad for seed metal. Any discontinuities can isolate the area from plating.

• The plating can surround and trap solution if the 1st resist layer is thin and the opening is narrow when compared with the plated metal thickness.

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Air Bridges

Air Bridges are used for crossing metal lines where low capacitance is desired. The most common is connecting FET source pads.An air bridge is formed by two litho layers.

– The 1st layer temporarily leaves resist to form the bridge support. The seed metal is then deposited.

– The 2nd layer defines the lines. – The 2nd resist layer, seed metal, and 1st resist are then removed, leaving

an air bridge.

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Air Bridge Aspect Ratio

Short and wide air bridges will need gaps to aid removal of the 1st resist layer.

– Whatever process used to stabilize the 1st layer will likely make it difficult to strip.

– The gaps also help resist coats after the bridge is formed. Air can get trapped during the coat and expand to a bubble during the soft bake.

• Prewetting the wafer to break the surface tension will also help prevent bubbles.

Long and thin air bridges can be flimsy.– Even water pressure from sawing can rip up these bridges

when they are close to the streets.

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Final Protective Overcoat


46Confidential & Proprietary

Initial Goals for Low-K Project at beginning of development of BCB process

Develop a process to:– add scratch protection– underside mechanical ‘support’ for air bridges– minimize electrical effects from subsequent package over-molding.

\

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Overview of BCB Process and Release Status

BCB overcoat process are intended to improve the PO and BCB adhesion to the second level metal (MET2)

– Addition of a 500-Ǻ evaporated titanium layer over the top of MET2

– Replacement of the tensile-stress 2000-Ǻ SiN protective overcoat (PO) deposited at 250C with a compressive stress PO deposited at 350C.

– Uniformity Target of 7um


FIB cross section of air bridge showing complete BCB underfill of airbridge as well as BCB thickness over the span.


FIB cross section and layout sketch of BCB overcoat profile of an PO style bond pad.

BCB encroachment of pad measured at 1.0um.

3MI PO Pad Layout Rules

MET1

MET2

BCB

N0/N1/N2/PO

2KPO


3MI PO Pad Layout Rules

FIB cross section and layout sketch of BCB overcoat profile of an PO style bond pad.

BCB encroachment of pad measured at 2.2 µm.MET1

MET2BCB8KPO

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First backside pattern is used to create the alignment marks for subsequent patterns.

HMDS improved resist adhesion on backside of Silicon Carbide wafers.

Pattern is aligned by looking through clear SiC wafer.

– Nickel hard mask required to withstand etch process

– Reverse image patterning leaving resist pads instead of openings.

– Advantage: Resist itself not a factor during the etch.

– No resist residues resulting from etch.

Circular resist pads define the vias for nickel plating.Nickel hard mask will be plated around the resist pattern.Resist will then be removed.SiC and GaN will be etched with high density plasma using the nickel as the hard mask.

Resist Pattern

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Cu/Sn Wafer Bumping

Copper/Tin Plated Bumps for flip chip packaging– Wafer is bumped on frontside; die is flipped during packaging– Air bridge protection with LOR resist– 85 micron thick resist processing for Cu/Sn bump plating

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Wafer Bumping for Flip Chip Packaging

Air bridge protection (Microchem LOR30B)Under-bump metallization (TiW/Cu)

– Adhesion– Step coverage– Electrical continuity, plating contacts

Thick resist patterning– Chemically amplified resist (Shin-Etsu 7120m)– Coat uniformity– 85 um thick resist– Contact/proximity printing (difficult alignment)– Long exposures, long bake times– Sidewall slope depends on mask/wafer contact

Cu/Sn platingResist removalSeed metal etch

– Minimization of undercutBump shear testing

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Pre-bump pattern after resist develop

LOR30B clear coat protects airbridges during Cu bump processing.

Postive resist is coated, baked, and exposed.

TMAH developer develops resist and etches LOR30B.

Poor LOR30B coat (rework) Good coat, expose, & develop

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During development of this process, some areas plated poorly, as if disconnected from other parts of wafer.

Discovered poor step coverage of seed metal over LOR30B pattern.

Step Coverage Issues resolved by reflowing LOR30B.

Seed metal step coverage problem due to LOR30B sidewall slopeSeed metal step coverage problem due to LOR30B sidewall slope

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No reflow Reflowed 90 sec @ 230C.

Reflowed 180 sec @ 230C. Chose this as new standard process.

Reflowed 300 sec @ 230C.

Seed metal coverage greatly improved with LOR30B reflow

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Focused on bottom of resist Focused on top of resist

Chemically amplified resist, 85 microns thick.

Must control top and bottom diameter of resist to define bump shape.

Cu Bump Resist Pattern

overlay metal/ inter-dielectric layers/bcb/cu bump workshop information... · 2015-02-03 ·...

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