overloaded cdma bus topology for mpsoc interconnect

8/8/2019 overloaded cdma bus topology for Mpsoc interconnect

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Overloaded CDM Bus Topology for

MPSoC Interconnect


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Introduction

MPSoC Overview

CDMA Basics

Ordinary CDMA Bus

Overloaded CDMA Bus

MIA Enabled spreading and despreading

Decoding of MIA enabled codes

Results and Discussion

Limitation and future work

Conclusion

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As Transistor size scales down, number of processingelements on silicon die increases

Intra-chip communication-major bottleneck in MPSoCdesigns

Bus topology-most common on-chip interconnect

technology Bus contention- Solution- Code division multiple access

(CDMA)

CDMA- limited number of orthogonal spreading codescan share medium-MIA

Overloaded CDMA-adds extra non-orthogonal spreadingcodes

Maximum number of cores sharing same CDMA bus inMPSoC –up by 25%

Resource- and speed-efficient

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Uses multiple processors targeted

for embedded applicationsUsed by platforms that contain

multiple(heterogeneous),

processing elements, memory

hierarchy and I/O components. All components linked to each

other by an on-chip interconnect

Used in multimedia applications,

telecommunication architectures,network security and other

domains

Limits power consumption

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CDMA spreading

CDMA spread spectrum generation CDMA spread spectrum decoding


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MPSoC CDMA XOR encoder and Accumulator decoder

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Reduced power consumption Fixed communication latency

Reduced system complexity


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A CDMA bus system containing the hybrid encoder, and both the orthogonal and

overloaded CDMA joint decoders


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An example of a bus sharing MAI-enabled and orthogonal codes

M1 = { 1, 0, 0, 0, 0, 0, 0, 0 }

M2 = { 1, 1, 0, 0, 0, 0, 0, 0 }

Md = { 0, 0, 0, 0, 1, 1, 1, 1 }


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The construction of 4 MAI codes in a 16-chip spreading code length,the

despreading code sends the MAI chips to the zero accumulator

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Virtex-7 FPGA VC707 evaluation kit

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Simulation results of data encoding and decoding in an overloaded CDMA bus using

16-chip spreading code length


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Implementation results for the overload CDMA bus of length N = {8, 16, 32, 64} on a Virtex-7 FPGA

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Lower bus frequency due to the increase incomputation path at the decoder

Delay optimization enables separatedecoders to run at higher bus frequency.

Bus frequency decreases with increasing N Pipelining adder implementation can fix but

increases bus latency

Other codes can be added to cause

identifiable MAI or cross correlationwaveforms

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Thus, CDMA bus capacity increased by 25%while preserving the ordinary CDMA bus

complexity

Presented approach can enable variable rate

communication-by assigning more than oneMAI-enabled code to the same IP core

Binary signalling scheme used for data

transfers in reconfigurable platforms

Increase in number of simultaneous coressharing the bus

Other codes can be added to cause

identifiable MAI

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overloaded cdma bus topology for mpsoc interconnect

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