page 1 wilfredo rivas-torres technical support application engineer october 12, 2004 power amplifier...

Wilfredo Rivas-TorresTechnical Support Application EngineerOctober 12, 2004

Power Amplifier Design using ADS

PA Workshop

ADS Power Amp Design

Outline

• Introduction• DC and Loadline analysis• Bias and Stability• LoadPull• Matching using Smith Chart Utility• SourcePull• PA Characterization – Did we meet the specification?• Optimize/Fine Tune the design• Test Design with real world modulated signals• Layout


Why do we need a Power Amplifier?

OSC

MODBaseband PADriver

Basic Transmitter

Power Amplifiers (PA) are in the transmitting chain of a wireless system. They are the final amplification stage before the signal is transmitted, and therefore must produce enough output power to overcome channel losses between the transmitter and the receiver.


PA requirements

• The PA is typically the primary consumer of power in a transmitter. A major design requirement is how efficiently the PA can convert DC power to RF output power.

• The design engineer has to often concern himself with the Efficiency of the Power Amplifier. Notice that efficiency translates into either lower operation cost (e.g. cellular basestation) or longer battery life (e.g. wireless handheld).

• PA linearity is another important requirement, the input/ output relationship must be linear to preserve the signal integrity.

• The design of PAs often involves the tradeoff of efficiency and linearity.


PA Design Requirement

• RF Output Power: 50 W PEP

• Input Drive Level : 1 W

• Output Load (RL): 50 Ω

• Efficiency (η) > 50%

• Bias Voltage: 28 V

• Device: MRF9045M


DC Curves

Set drain and gate voltagesweep limits as needed.

FET Curve Tracer

VJFSL_MRF_MET_MODELMRF1MODEL=MRF9045M

ParamSweepSweep1

Step=0.1Stop=5.0Start=2.5SweepPlan="SwpPlan1"

PARAMETER SWEEP

DisplayTemplatedisptemp1"FET_curve_tracer"

TempDisp

FSL_TECH_INCLUDEFTI

FSL_TECH_INCLUDE

DCDC1

Step=0.1Stop=28*2Start=0SweepVar="VDS"

DC

V_DCSRC1Vdc=VDS

V_DCSRC2Vdc=VGS

VARVAR1

VGS =0 VVDS =0 V

EqnVar

I_ProbeIDS


DC Curves

5 10 15 20 25 30 35 40 45 50 550 60

1

2

3

4

0

5

VDS

IDS

.i, A

0.9000.102

VDsat

27.7000.118

IQ

33.4000.004

m3

Load

_Lin

e

VDsatVDS=IDS.i=0.562VGS=3.800000

0.600IQVDS=IDS.i=0.717VGS=3.800000

28.000m3VDS=IDS.i=0.004VGS=2.500000

33.400


Bias and Stability

MRF9045M_AMPX2

VG VJ

VD

sr_avx_CR_10_K_19960828R12PART_NUM=CR10-680K 68 Ohm

MSUBMSub1

Rough=0 milTanD=0.002 T=2.8 milHu=3.9e+034 milCond=5.8E+08 Mur=1 Er=4.2 H=33.6 mil

MSub

FSL_MRF_MET_MODELMRF1

CTH=-1RTH=-1TSNK=25MODEL=MRF9045M

sc_mrt_MC_GRM40C0G050_J _19960828C17PART_NUM=GRM40C0G330J 050 33pF


PortP3Num=3

MLINTL20

L=100 milW=63.668898 milSubst="MSub1"

MLINTL21


sc_mrt_MC_GRM40C0G050_D_19960828C20PART_NUM=GRM40C0G100D050 10pF

sc_spr_293D_A025_X9_19960828C19PART_NUM=293D474X9025A2 0.47uF MLIN

TL1

L=2194.444882 milW=63.670079 milSubst="MSub1"

MLINTL23


MLINTL22



sc_spr_293D_A025_X9_19960828C24PART_NUM=293D474X9025A2 0.47uF

PortP4Num=4




sl_tok_LL2012-F_J _19960828L2PART_NUM=LL2012-F82NJ 82 nH

sr_avx_CR_10_K_19960828R13PART_NUM=CR10-150K 15 Ohm

PortP2Num=2

PortP1Num=1


Stability Analysis

VGGVDD

VDD

VGGMRF9045M_AMPX1

S_ParamSP2

Step=1.0 MHzStop=3000 MHzStart=1 MHz

S-PARAMETERS

I_ProbeIDD

I_ProbeIGG

V_DCSRC2Vdc=VGS

V_DCSRC1Vdc=VDS

VARVAR3

VGS =3.8 VVDS =28 V

EqnVar

FSL_TECH_INCLUDEFTI

FSL_TECH_INCLUDE

MuPrimeMuPrime1MuPrime1=mu_prime(S)

MuPrime

MuMu1Mu1=mu(S)

Mu

StabMeasStabMeas1StabMeas1=stab_meas(S)

StabMeas

StabFactStabFact1StabFact1=stab_fact(S)

StabFact

P_1TonePORT1

Freq=fssP=polar(dbmtow(-60),0)Z=50 OhmNum=1

TermR3

Z=50 OhmNum=2


Stability Analysis

0.5 1.0 1.5 2.0 2.50.0 3.0

1E1

1E2

1E3

1E4

1

3E4

freq, GHz

Sta

bFac

t1


Impedance Matching

• The need for matching circuits is because amplifiers, in order to perform in a certain way(e.g. maximize output power), must be presented with a certain impedance at both the load and the source ports.

• For example in order to deliver maximum power to the load RL the transistor must have termination Zs and ZL.

• The input matching network is designed to transform the generator impedance Rs to the optimum source impedance Zs.

• The output matching network transform the load termination RL (50 Ω) to the optimum load impedance ZL.

• A LoadPull measurement will help the designer determine the optimum load impedance ZL.


LoadPull Setup

Vs_low

vload

Vs_high

Set these values:

Set Load and Source impedances atharmonic frequencies

VARSweepEquations

Z0=50pts=100s11_center =-0.6 +j*0.1s11_rho =0.75

EqnVar

FSL_TECH_INCLUDEFTI

FSL_TECH_INCLUDE

VARSTIMULUS

Vlow=3.8Vhigh=28.0RFfreq=760 MHzPavs=30 _dBm

EqnVar

ParamSweepSweep2

PARAMETER SWEEP

HarmonicBalanceHB1

Order[1]=15Freq[1]=RFfreq

HARMONIC BALANCE

VARVAR2

Z_s_5 =Z0 + j*0Z_s_4 = Z0 + j*0Z_s_3 = Z0 + j*0Z_s_2 = Z0 + j*0Z_s_fund =1.0 + j*0Z_l_5 = Z0 + j*0Z_l_4 = Z0 + j*0Z_l_3 = Z0 + j*0Z_l_2 =Z0 + j*0

EqnVar

P_1TonePORT1

Freq=RFfreqP=dbmtow(Pavs)Z=Z_sNum=1

I_ProbeIs_low

V_DCSRC2Vdc=Vlow

MRF9045M_AMPX2

I_ProbeIload

I_ProbeIs_high

S1P_EqnS1S[1,1]=LoadTunerZ[1]=Z0

V_DCSRC1Vdc=Vhigh

ExamplesSearch


LoadPull Contours

m2indep(m2)=Pdel_contours_p=0.914 / 171.170level=44.195857, number=1impedance = 2.265 + j3.852

6

m1indep(m1)=PAE_contours_p=0.914 / 171.180level=47.552308, number=1impedance = 2.265 + j3.848

6

indep(Pdel_contours_p) (0.000 to 46.000)

Pde

l_co

ntou

rs_p

indep(PAE_contours_p) (0.000 to 18.000)

PA

E_c

onto

urs_

p


Matching using Smith Chart Utility


Output Match

DA_SmithChartMatch1_output_match_designDA_SmithChartMatch1

Z0=50 OhmZl=(2.300-j*3.800) OhmZs=50 OhmF=760 MHz

PortP2Num=2

PortP1Num=1

CC3C=27.689016 pF

CC2C=2.307137 pF

TLINTL3

F=760 MHzE=25.92Z=22.85 Ohm

TLINTL2

F=760 MHzE=32.25Z=50 Ohm

TLINTL1

F=760 MHzE=8.891Z=50 Ohm

CC1C=12.975203 pF


SourcePull Contours

indep(PAE_contours_p) (0.000 to 77.000)

PA

E_c

onto

urs_

p

indep(Pdel_contours_p) (0.000 to 66.000)

Pde

l_co

ntou

rs_p

m2indep(m2)=Pdel_contours_p=0.960 / 174.023level=46.038749, number=1impedance = 1.016 + j2.609

4

m1indep(m1)=PAE_contours_p=-0.952 + j0.100level=58.130703, number=1impedance = 1.096 + j2.618

4


Matching Circuits

PortP1Num=1

MLINTL7


MLINTL8


MLINTL9



PortP2Num=2


sc_mrt_MC_GRM40C0G050_C_19960828C21PART_NUM=GRM40C0G020C050 2pF


sc_mrt_MC_GRM40C0G050_C_19960828C25PART_NUM=GRM40C0G020C050 2pF

MLINTL18


MLINTL17


PortP2Num=2

MLINTL16


PortP1Num=1


Output Match

Input Match


Complete Design Power Sweep

Vin

Vloadinput_matchX5 MRF9045M_AMP

X4

output_matchX3

V_DCSRC1Vdc=VDS

I_ProbeIload

RR1R=50 OhmVAR

VAR1

Pin=30VGS =3.8 VVDS =28 V

EqnVarVAR

VAR2fo=760.0 MHz

EqnVar

FSL_TECH_INCLUDEFTI

FSL_TECH_INCLUDEHarmonicBalanceHB1

Step=1Stop=40Start=-30SweepVar="Pin"Order[1]=15Freq[1]=fo

HARMONIC BALANCE

P_1TonePORT1

Vdc=Freq=foP=dbmtow(Pin)Z=50.0 OhmNum=1

I_ProbeIin

V_DCSRC2Vdc=VGS


Power Compression Curve

-20 -10 0 10 20 30-30 40

0

20

40

-20

60

Pin

Pde

l_dB

m

Readout

Output

OutputPin=Pdel_dBm=45.570

30.000


Gain Compression Curve

-20 -10 0 10 20 30-30 40

8

10

12

14

16

6

18

Pin

Gp

Readout

GainComp

-29.00017.341

LinearGain

GainCompind Delta=dep Delta=-1.771 delta mode ON

60.00 LinearGainPin=Gp=17.341

-30.000


Power Added Efficiency

-20 -10 0 10 20 30-30 40

10

20

30

40

50

0

60

Pin

PA

E

Readout

m1 m1Pin=PAE=49.618

30.000


Getting ready to Optimize the PA• The next step is to optimize the design to meet the

requirements.

• The Designer can take the opportunity to see if other requirements, such as layout will require any changes before proceeding to optimize.

• Example: we notice that the transistor pads are rather wide and the Tlines leading up to it are not the same width.

• Since the Tlines are much narrower, we could add a taper so we have a nice transition.

• We included a MTAPER at the input and output side

dBm(Vload[1])

41.549

MTAPERTaper2

L=100.0 milW2=63.670079 milW1=199.971654 milSubst="MSub1"


Optimization Setup

GoalGoal2

RangeMax[1]=RangeMin[1]=RangeVar[1]=Weight=Max=-40Min=SimInstanceName="HB1"Expr="dBm(Vload[2])-dBm(Vload[1])"

GOAL

GoalGoal1

RangeMax[1]=RangeMin[1]=RangeVar[1]=Weight=Max=Min=47.0SimInstanceName="HB1"Expr="dBm(Vload[1])"

GOAL

OptimOptim1

SaveCurrentEF=noUseAllGoals=yesUseAllOptVars=yesSaveAllIterations=noSaveNominal=noUpdateDataset=yesSaveOptimVars=noSaveGoals=yesSaveSolns=yesSetBestValues=yesNormalizeGoals=noFinalAnalysis="None"DesiredError=0.0MaxIters=25OptimType=Gradient

OPTIM


Optimization Results

InitialEF

67.187

FinalEF

0.000

optIter

10

Goal1

47.003

Goal2

-40.017

MLINTL39

L=2194.444882 mil opt{ 250 mil to 3500 mil }W=63.670079 milSubst="MSub1"

MLINTL39

L=551.591 mil opt{ 250 mil to 3500 mil }W=63.670079 milSubst="MSub1"

Before After


Optimization Values

TL39.L*1e5/2.54

551.591

TL10.L*1e5/2.54

244.711

TL15.L*1e5/2.54

247.144

TL30.L*1e5/2.54

814.900

TL31.L*1e5/2.54

202.643

TL32.L*1e5/2.54

184.709

TL7.L*1e5/2.54

320.449

TL8.L*1e5/2.54

622.341

TL9.L*1e5/2.54

248.635


PA Results

-20 -10 0 10 20 30-30 40

0

20

40

-20

60

Pin

Pde

l_dB

m

Readout

m1 m1Pin=Pdel_dBm=47.003

30.000


Power Added Efficiency

-20 -10 0 10 20 30-30 40

20

40

60

0

80

Pin

PA

E

Readout

m3m3Pin=PAE=56.736

30.000


Gain Compression Curve

-20 -10 0 10 20 30-30 40

-8

-6

-4

-2

-10

0

Pin

Gp-

Gp[

0]

Readout

m4m4Pin=Gp-Gp[0]=-0.728

30.000


Complex Modulated Signal

759.75 760.00 760.25759.50 760.50

-80

-60

-40

-20

0

20

-100

40

Frequency (MHz)

16 Q

AM

Spe

ctru

m (dB

m)


16 QAM Modulated Source

SpectrumAnalyzerS9

WindowConstant=0.0Window=noneStop=DefaultTimeStopStart=DefaultTimeStartRLoad=DefaultRLoadPlot=None

QAM_ModQ1

PhaseImbalance=0GainImbalance=0Phase=0VRef=1.0 VPower=PcFCarrier=Fc

LPF_RaisedCosineTimedL4

Delay=16/bit_rateSquareRoot=YesType=Model with pulse equalizationExcessBw=0.5CornerFreq=bit_rate/8Loss=0.0SymbolConverter

S3

CodeOut=pam4OutCodeIn=nrzInDelay=0 secSymbolTime=2/bit_rate

SymbolConverterS4

CodeOut=pam4OutCodeIn=nrzInDelay=0 secSymbolTime=2/bit_rate

LPF_RaisedCosineTimedL5

Delay=16/bit_rateSquareRoot=YesType=Model with pulse equalizationExcessBw=0.5CornerFreq=bit_rate/8Loss=0.0

DataD1

Repeat=YesSequencePattern=23Type=PrbsUserPattern=""BitTime=1/bit_rateTStep=Tstep

SymbolSplitterS1

Delay=-1SymbolTime=1/bit_rate


DSP and Analog Circuits Setup

• Create a subcircuit with your analog design.

• You need to add either Circuit Envelope or Transient controller to the analog circuit.

• We use Circuit Envelope specifically with our PA since we have a Modulated Carrier.

• Circuit Envelope will also allow the use of Fast Cosim (Automatic Verification Modeling – AVM). This will dramatically increase the simulation speed.

• In the DSP schematic we will create the Modulated Carrier, feed it to the PA and collect the signal samples and spectrum.

• The DSP schematic contains a Envelope Output Selector component used for interfacing between circuit subnetwork output and the signal processing components.


TimedSinkRF_out

ControlSimulation=YESStop=DefaultTimeStopStart=DefaultTimeStartPlot=Rectangular

MRF9045M_AMP_CE2X1

SplitterRFS10

TimedSinkRF_in


EnvOutShortO1OutFreq=Fc

TimedSinkIout


TimedSinkQout


MatchedLossM1Loss=17.0

SplitterRFS7

PhaseShiftRFP1PhaseShift=360-168

QAM_DemodQ2

PhaseImbalance=0.0GainImbalance=0.0Phase=0.0Sensitivity=0.1*(10**((25-Pow)/20))RefFreq=Fc

QAM_srcX2Pc=Pow

SpectrumAnalyzerS8


SpectrumAnalyzerS9


Ptolemy Cosim Schematic

QAM Source

PA


Fast Cosim Improvements

Simulation Time Benchmark: Total bits: 1024 bitsAVM disabled : 410 secAVM enabled: 13 secAVM data reuse: 5.5 sec--------------AVM data reuse (16 Kbits): 17.5 sec


Cosimulation Results - Spectrum

759.5 760.0 760.5759.0 761.0

-80

-60

-40

-20

0

-100

20

freq, MHzdB

m(S

8)dB

m(S

9)759.5 760.0 760.5759.0 761.0

-80

-60

-40

-20

0

-100

20

freq, MHz

dBm

(S8)

dBm

(S9)

Carrier Power 30 dBm



Cosimulation Results - Constellation

-1.0 -0.5 0.0 0.5 1.0-1.5 1.5

-1.0

-0.5

0.0

0.5

1.0

-1.5

1.5

indep(Test_const)

Test

_con

st

-1.0 -0.5 0.0 0.5 1.0-1.5 1.5

-1.0

-0.5

0.0

0.5

1.0

-1.5

1.5

indep(Test_const)

Tes

t_co

nst




Cosimulation Results

peakP_out

47.969

peak_avg_out

3.516

avgPout

44.453



peakP_in

32.163

peak_avg_in

4.951

avgPin

27.212

peakP_in

30.000

peak_avg_in

7.788

avgPin

22.212

peakP_out

44.715

peak_avg_out

4.832

avgPout

39.883


Cosimulation Results – CCDF

-6 -4 -2 0 2 4-8 6

1E-4

1E-3

1E-2

1E-1

1E-5

9E-1

dB

pCC

DF_i

npC

CD

F_o

ut

-6 -4 -2 0 2 4-8 6

1E-4

1E-3

1E-2

1E-1

1E-5

9E-1

dB

pCC

DF_i

npC

CD

F_o

ut




EVM vs. Power Measurement

VARVAR3

Pow=30 _dBmFc=760 MHzTstop=num_bits/bit_rateTstep=1/(bit_rate*oversample)

EqnVar VAR

VAR2

num_bits=4096*4oversample=4bit_rate=1.0 MHz

EqnVar

ParamSweepSweep1

Step=1Stop=30Start=18SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="DF1"SweepVar="Pow"

PARAMETER SWEEP

DFDF1

SavedEquationName[1]="Tstep"DefaultTimeStop=TstopDefaultTimeStart=0DefaultNumericStop=100DefaultNumericStart=0

QAM_srcX2Pc=Pow

EVM_WithRefE2

SymbolRate=0.25 MHzMeasType=EVM_rmsNumBursts=2SymDelayBound=-1SampPerSym=16SymBurstLen=1024StartSym=10

Ref

test EVM Ref

RESR2R=50 Ohm

RESR1R=50 Ohm


MRF9045M_AMP_CE2X1

SplitterRFS7


EVM vs. Power Results

20 22 24 26 2818 30

1

2

3

4

0

5

Power (dBm)

EV

M (%

)

EVM vs. Carrier Power


ADS to VSA link

VARVAR3

Pow=30 _dBmFc=760 MHzTstop=num_bits/bit_rateTstep=1/(bit_rate*oversample)

EqnVar

VARVAR2

num_bits=1024*16oversample=4bit_rate=1.0 MHz

EqnVar

FSL_TECH_INCLUDEFTI

FSL_TECH_INCLUDE

DFDF1

SavedEquationName[1]="Tstep"DefaultTimeStop=TstopDefaultTimeStart=0DefaultNumericStop=100DefaultNumericStart=0

RESR1R=50 Ohm

VSA_89600_1_SinkV1

SetFreqProp=Y ESRestoreHW=NOSetupFile="C:\Program Files\Agilent\89600 VSA\Vector\User\PA_demod.set"SamplesPerSymbol=16TStep=TstepVSATitle="Simulation output"

VSA

QAM_srcX2Pc=Pow


MRF9045M_AMP_CE2X1


VSA Spectrum from ADS Cosim


VSA Constellation from ADS CosimCarrier Power 30 dBm


VSA EVM from ADS Cosim



PA Layout

sc_mrt_MC_G RM40C0G 050_J _19960828

C18

PART_NUM=G RM40C0G 220J 050 22pF

MRF9045_art

Q 1

sc_mrt_MC_G RM40C0G 050_J _19960828

C17


Port

P2

Num=2

Port

P1

Num=1

sr_avx_CR_10_K_19960828

R13

PART_NUM=CR10-150K 15 O hm

sc_mrt_MC_G RM40C0G 050_J _19960828

C3

PART_NUM=G RM40C0G 330J 050 33pF sr_avx_CR_10_K_19960828

R12

PART_NUM=CR10-150K 15 O hm

MTAPER

Taper1

L=100. 0 mil

W2=63. 670079 mil

W1=199. 971654 mil

Subst="MSub1"

MTAPER

Taper2

L=100. 0 mil

W2=63. 670079 mil

W1=199. 971654 mil

Subst="MSub1"

sc_mrt_MC_G RM40C0G 050_D_19960828

C26

PART_NUM=G RM40C0G 090D050 9pF

sc_mrt_MC_G RM40C0G 050_J _19960828

C24


sc_mrt_MC_G RM40C0G 050_C_19960828

C28

PART_NUM=G RM40C0G 020C050 2pF

sc_mrt_MC_G RM40C0G 050_D_19960828

C27


MLI N

TL30

L=814. 898 mil opt{ 250 mil to 1000 mil }

W=63. 670079 mil

Subst="MSub1"

MLI N

TL8


W=63. 670079 mil

Subst="MSub1"

MLI N

TL15


W=63. 670079 mil

Subst="MSub1"

MLI N

TL32


W=63. 670079 mil

Subst="MSub1"

MLI N

TL31


W=199. 971654 mil

Subst="MSub1"

MLI N

TL7


W=199. 971654 mil

Subst="MSub1"

MLI N

TL9


W=63. 670079 mil

Subst="MSub1"

MLI N

TL10


W=63. 670079 mil

Subst="MSub1"

MTEE_ADS

Tee1

W3=63. 668898 mil

W2=199. 971654 mil

W1=199. 971654 mil

Subst="MSub1"

MTEE_ADS

Tee2

W3=63. 670079 mil

W2=199. 971654 mil

W1=199. 971654 mil

Subst="MSub1"

MSUB

MSub1

Rough=0 mil

TanD=0. 002

T=2. 8 mil

Hu=3. 9e+034 mil

Cond=5. 8E+08

Mur=1

Er=4. 2

H=33. 6 mil

MSub

SMT_Pad

Pad2

PO =0 mil

SM_Layer="solder_mask"

SMO =5. 0 mil

PadLayer="cond"

L=40. 0 mil

W=70. 0 mil

SMT_ Pad

SMT_Pad

Pad1

PO =0 mil


SMO =5. 0 mil

PadLayer="cond"

L=40. 0 mil

W=50. 0 mil

SMT_ Pad

SMT_Pad

Pad3

PO =0 mil


SMO =5. 0 mil

PadLayer="cond"

L=30. 0 mil

W=30. 0 mil

SMT_ Pad

MLI N

TL39


W=63. 670079 mil

Subst="MSub1"

sc_mrt_MC_G RM40C0G 050_C_19960828

C25

PART_NUM=G RM40C0G 020C050 2pF

MLI N

TL41

L=253. 4234 mil

W=63. 6689 mil

Subst="MSUB1"

MCURVE2

Curve2

Nmode=2

Radius=100. 0 mil

Angle=90

W=63. 668898 mil

Subst="MSub1"

sc_mrt_MC_G RM40C0G 050_D_19960828

C20


MLI N

TL42

L=440 mil

W=63. 668898 mil

Subst="MSub1"

sc_spr_293D_A025_X9_19960828

C19

PART_NUM=293D474X9025A2 0. 47uF

Port

P3

Num=3

MLI N

TL20

L=225 mil

W=63. 668898 mil

Subst="MSub1"

MLI N

TL21

L=200 mil

W=63. 668898 mil

Subst="MSub1"

sl_tok_LL2012-F_J _19960828

L2

PART_NUM=LL2012-F82NJ 82 nH

MLI N

TL43

L=90 mil

W=40 mil

Subst="MSUB1"

MLI N

TL22

L=200 mil

W=63. 668898 mil

Subst="MSub1"

MLI N

TL23

L=350 mil

W=63. 668898 mil

Subst="MSub1"

Port

P4

Num=4

MLI N

TL40

L=200 mil

W=63. 668898 mil

Subst="MSub1"

sc_spr_293D_A025_X9_19960828

C23

PART_NUM=293D474X9025A2 0. 47uF

sc_mrt_MC_G RM40C0G 050_D_19960828

C22


MCURVE2

Curve1

Nmode=2

Radius=100. 0 mil

Angle=90

W=63. 668898 mil

Subst="MSub1"

sc_mrt_MC_G RM40C0G 050_J _19960828

C21


MLI N

TL1

L=100 mil

W=63. 668898 mil

Subst="MSUB1"

MLI N

TL44

L=315. 0248 mil

W=63. 668898 mil

Subst="MSUB1"


PA Layout – Generated from Schematic


PA Layout – Ground Fill


Other Possibilities

• Run an EM Cosimulation – include layout effects in the simulation. Optimize design if necessary.

• Run Loadpull for IP3 or ACPR. The optimum load would then be a compromise between all the requirements.

• Use Connection Manager and real PA to validate design and compare vs. simulated results.

• Create a behavioral data model that can be used to protect you IP yet give access to your design results.

If there is any topic about PA Design and ADS you wish to

discuss email me: [email protected]

page 1 wilfredo rivas-torres technical support application engineer october 12, 2004 power amplifier...

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