Panda PCB for prototype status report

by D Malkevich on behalf of the ITEP group

ITEP

ALICE TOF experience - module based on PCB

- Module design based on multi layer PCB both for mechanical construction and

signal routing

- Minimal Radiation Length, => no cooling and cabling inside module

- Signal transmission lines, HV and L.V. distribution “on board”

PANDA prototype design :

Strip consists of 8 th single cell DRPC

chambers fixed at 6 layers PCB and

merged into common gas volume.

4 gapsR=1010Ω

4 gapsR=1012Ω

4 gapsR=1011Ω

6 gapsR=5*1012Ω

6 gapsR=1010Ω

4 gapsR=5*1010Ω

4 gapsR=5*1011Ω

4 gapsR=5*1012Ω

PCB design (Capture)

R 37

20 0

C 28

10 0 nF

+

C 45

4 . 7 uF

C 53

10 0 nF

+5 V A

C 4 8

1 0n F

J P 3

J U M P E R12

+5 V A

+

-

+

+

-

-

AD 8 1 46 / L F C S P V Q C P 2 4 1

U 4

1 2 3 4 5 6

7

8

9

10

11

12

24

23

22

21

20

19

18 17 16 15 14 13

OP

D

Vs-

_2

-IN

A

+IN

A

Vs-

_5

-OU

T A

+O U TA

Vs + _8

+O U TB

-O U TB

V s +_1 1

+O U TC

V s +_2 4

-IN B

+IN B

V s -_ 21

V o c m A

V o c m B

Voc

mC

Vs+

_17

-IN

C

+IN

C

Vs-

_14

-OU

TC

R 2 0

1 1

TO T1 +

R 3 2

2 00

R 2 5

1 kC 32

10 0 nF

+ 5V D

R 2 320 0

J 4

5 4

1

32

AGND

C 7

1 pF

+5 V A

+

C 57

4.7 u F

-5 V A

R 3 02 00

C 2 78

1n F

-5V A

AGND

C 4 4

10 0 nF

+

C 5 2

4. 7 uF

C 8

10 0 nF

R 8

51

R 1 8

20 0

R 2 6

2 00

C 5 5

10 0 nF

C 3 6

10 0 n

R 1 7

20 0AGND

-5V D

C 2 4

10 n F

TO T2 +

Le m o

-5 V A

C 2 9

10 0 n F

R 1 4

2 00

C 211 nF

+5 V A

R 2 7

20 0

+

C 2 7

4. 7 uF

R 3 5

11

C 11

10 0 nF

DGND

C 2 2

1 0n F

Q 1

2 N 22 2 2

R 4

1k

J 2

54

1

3 2

R 3 620 0

+

C 5 4

4. 7 uF

AGND

J P 1J M P9

132

+5 V A

R 3 120 0

U 5

A D 83 5 0

1

2

8

4

536 7

IN +

E N BL

IN -

O U T+

O U T-+V C CG N D G N D 2

J 1

5

4

1

3

2

Z0=2x100

-5 V A

J P 2

J U M P E R12

U 3 B

A D 80 5 6

75

6

84

O u tI n +

I n -

Vcc

Vee

+5 V A

C 1 3

4. 7 u F

R 3 8

2 00

+

C 16

4.7 u F

C 25

10 0 nF

R 2

1k

1 3

2

TO T2 -

-5 V A

R 3 3

51

J 354

1

3 2

D 1

B Z V 5 5 -B 3 V 3

R 1

51

CH1

C 1 8

10 n F

R 3

2k

R 1 1

33 0

+

C 5 0

4. 7u F

C 58

10 0 nF

C 34

10 n F

C 2

10 0 nF

+

C 6 3

4.7 u F

Threshold

R 2 9

20 0

Z0=2x100

+

C 5

4.7 u F

C 4

10 n F

D 2

BA V 9 9/S O T

3

1 2

R 1 9

1 k

+

C 12

4.7 u F

Le m o

R 6

1k

C 1 5

10 0 nF

R 2 8

2 00

R 3 4

2 00

+

C 3 7

4. 7u F

+5 V A

C 3 11p F

C 46

10 0 nF

C 2 3

10 n F

C 1 7

10 0 nF

R 22

2 00

R 7

20 0

Test

R 5

1k

+

C 9

4 . 7 uF

C 4 7

10 p F

R 1 5

20 0

C 26

10 0 nF

+

C 30

4. 7 uF

C 4 2

10 n F

C 4 01n F

C 3 9

10 n F

CH2

+C 3

4. 7u F

-5 V A

C 5 6

10 0 nF

C 110 0 nF

+5 V A

U 1

A D 9 66 8 7

8

7

9

10

1

2

16

15

413

314

512116

in 1+

in 1-

in 2+

in 2-

ou t 1 +

ou t1 -

ou t 2 +

ou t2 -

E N 1E N 2G N D 1G N D 2

EN I 1EN I 2

V c cV e e

C 43

10 n F

+5 V A

R 1 3

33 0

AGND

C 3 8

10 p F

R 1 0

33 0

+5 V A

U 2

A D 8 3 50

1

2

8

4

536 7

IN +

EN B L

IN -

O U T+

O U T-+V C CG N D G N D 2

R 2 4

2 00

C 6

10 0 nF

AGND

C 1 0

10 n F

U 3 AA D 80 5 6

13

2

84

O u tI n+

I n-

Vcc

Vee

+5V AC 51

10 0 nF

C 4 1

10 n F

PG 1S o lde r J u m pe r

12

+

C 3 3

4. 7 uF

C 4 9

10 n F

R 2 1

20 0-5 V A

TO T1 -

C 2 79

1n F

-5V A

C 6 2

10 0 nF

R 1 2

33 0

C 3 5

10 n F

+

C 59

4.7 u F

R 1 4 5

1 0 0 k

J 1 4S u h n e r 3 / B 2 3 2 U N E F 2 A 1

2 R 1 4 6

1 M

HV

1

R 1 4 7

1 0 k

C 2 6 4

2 n F

C 2 5 8

2 n F

+ H V

C 2 5 5

4 .7 u F

+5V D

C 25 6

1 0n F

+5V D

C 25 3

4 .7 uF

C 25 4

1 0n F

L3

22 u H

DGNDPWRD

J 13

W F 3 R

123

-5V D

C 25 7

4 .7 uF

C 25 01 0n F C 25 2

1 0n F

L4

22 u H

C 25 14 .7 u F

-5V D

We are going to do :

Differential transmission lines quality

Resistive coating optimization

Resolution, efficiency, rate dependence, and streamer fraction

using this prototype

Pre amplifier Main amplifier Amplitude buffers

Amplitude outputs

TOT outputs

Test input

Internal / ExternalThreshold

HV filter

LV filter

Differentialtransmission lines

HV, LV and test line

TOTs, fast “OR” + Amplitude

outputs

Discriminator

PCB design (Layout)

DiscriminatorsAD96687

Main amplifiers AD8146

Buffers AD8056

Fast “OR”

Test 50 Ohm line

H.V. connector

Test input

External Threshold connector

L.V. connectors

Amplitude outputs

TOTs + Fast “OR”

Last updates• Discriminator MAXIM 9600 changed to AD96687. Just to have both amplifier and

discriminator from one vendor.• PCB Stack up parameters for structure with 200 Ohm differential lines preliminary

estimated with respect to reality i.e. available materials of manufacture, compromise between possibility and prices. (We are still discussing with manufacture precision we can achieve)

Conclusion

•6 layers PCB for 8th channels prototype was design in ORCAD.•PCB stackup design parameters for 200 Ohm differential lines preliminary estimated. Calculation based on real available materials for some manufacture.•Transmission lines quality test will be taken ASAP when PCB already done. Test results could give conclusion about signal transmission possibilities up to 1,5 m (we want to produced PCB ASAP but we haven’t funding for the moment)•Schematic and PCB design for real size prototype will be make after confirmation final mechanical design. (PCB will be produced only after DIRC design will be fixed)