Estimation of Analog/Mixed-Mode Circuit Performance Variations Due to the Process Variations

Sedigheh Hashemi

Abstract— in this survey, some innovative methods of estimating the impacts of process variations on the performance of analog/mixed-mode circuits are described. Comparing with digital circuitry, analog/mixed-mode circuits consist of wider variety of devices and are more sensitive to process variations; therefore, simulation and optimization of such circuits, considering process variations, involves a larger number of process parameters and needs higher accuracy resulting in a high computation cost. Hence, the main goal is increasing the efficiency of the estimation method and reaching high accuracy particularly in the case of nano-scale feature sizes below 100 nm. In [1], DC mismatches are modeled as AC pseudo-noise and utilizing the fast periodic noise analysis (PNOISE), impacts on performance are computed efficiently. [2] and [3] propose two novel techniques to reduce the number of parameters while taking the performance orientation into account. [4] and [5] propose methodologies to efficiently capture the impacts of mismatch and process variations on the circuit performance.

I. INTRODUCTION AND MOTIVATION

Automated design and optimization of analog/mixed-mode circuits is usually more complicated than digital circuitry and usually requires many more cycles that results in too much computation cost. There are some aspects of analog/mixed-mode circuit design that make it different from digital circuit design. First, analog circuits deal with all the voltage or current levels and hence are much more sensitive than digital circuits that only deal with a few levels of voltage or current. Therefore, process variations can affect the performance of analog circuits in a more serious way. Process variation can cause mismatches, noise, and undesirable operating regions that can degrade the performance dramatically. Second, in analog/mixed-mode circuits, performance metrics like power consumption, speed, noise, and linearity are strongly dependent on the physics of the devices. For example, the linearity and dynamic range of a flash ADC is directly dependent on the offset of each comparator which is due to the device mismatches and varies strongly with process variations. Third, a wider variety of devices are used in analog/mixed-mode circuits such as digital CMOS, mid-voltage and high-voltage MOS, BJT, MIM capacitors, and resistors [4]. Therefore, to increase the reliability and yield of the design, each device must be characterized accurately over a very large space of the parameters to capture the impacts of the process variation on the circuit performance.

Another motivation for this survey is the observed trend of increase in the process variations as IC technology is scaled to deep sub-micron region [1-5]. As shown in TABLE I. , .These large variations introduce

high uncertainty and makes the design and optimization of the circuits too complicated. Considering merely the worst case scenarios can result in high lost in performance which is not acceptable in many applications. Therefore, iterative algorithms are usually required to accurately capture the impacts of process variations on performance which are computationally too costly. In analog/mixed-mode circuit design, however, due to many 2nd order effects and very large number of parameters, such algorithms are usually impossible to be utilized efficiently. Hence, the main goal is increasing the efficiency of the estimation method and reaching high accuracy particularly in the case nanometer technologies with the feature sizes below 100 nm. In this survey we bring together some ideas and solutions proposed in five different publications. In [1], DC mismatches are modeled as AC pseudo-noise and utilizing the fast periodic noise analysis (PNOISE), impacts on performance are computed efficiently. [2] and [3] propose two novel techniques to reduce the number of parameters while taking the performance orientation into account. Such techniques are very essential since the computation costs of the algorithms are usually exponentially grow up with the number of parameters. [4] and [5] propose methodologies to efficiently capture the impacts of mismatches and process variations on the circuit performance. Finally, a comparison and discussion section ends the report.

TABLE I. PROCESS VARIATIONS (3Σ/NOMINAL) CAPTURED FORM [2]

YearLeff

(nm)W

(%) L (%) Tox (%)

Vth (%)

H (%)

r (%)

1997 250 25.0 32.0 8.0 10.0 25.0 22.2

1999 180 26.2 33.3 8.0 10.0 30.0 24.0

2002 130 28.0 34.6 9.8 10.0 30.0 27.3

2005 100 30.0 40.0 12. 11.4 33.8 31.7

2006 70 33.3 47.1 16. 13.3 35.7 33.3

II. FAST, NON-MONTE-CARLO ESTIMATION OF TRANSIENT PERFORMANCE VARIATION DUE TO DEVICE

MISMATCH

In [1], a noise-based method is proposed to estimate the effects of the device random mismatch on the circuit performance. This method relies on Gaussian distributions of device mismatches and linear perturbation model. It also can be utilized to characterize

the correlation between different performance parameters and also can give the sensitivity of each performance parameter versus any process parameter. These two possibilities are very helpful in the optimization phase of the circuit design.

A. Noise-Based Mismatch AnalysisFlowThe noise-based mismatch analysis flow is depicted

in Figure 1. The key idea is that the random device mismatch and low-frequency AC noise have similar impacts on circuit performance if they are observed over a bounded time period. In the analysis flow, first, the device mismatches in the circuit are converted to an equivalent pseudo-random low-frequency (flicker) noise.

Figure 1. The noise-based mismatch analysis flow

Then in the second step, circuit with the modeled pseudo-noise sources is simulated by periodic noise analysis (PNOISE) available in RF circuit simulators such as SpectreRF, HSPICE-RF, ADS, and eldoRF. To run PNOISE analysis, first a periodic steady-state response is found by doing PSS analysis. However, to run PSS, circuit must have a periodic steady-state response which is not the case in most of the circuits. Therefore, some simulation configuration may be needed to push the circuit in a periodic steady-state behavior. For example, by applying a periodic input, a logic circuit will show a periodic output.

Finally, the noise power spectral density (PSD) must be converted back to performance variations. The output of PNOISE is a cyclostationary noise and has sidebands at DC and at the multiples of fundamental frequencies. According to the desired performance parameter, the proper sideband must be chosen. For example, baseband noise PSD corresponds to variation in DC response (such as offset) whereas passband noise PSD corresponds to variation in AC response (such as phase or delay shifts).

PNOISE simulator also provides information about contribution of each element to the total noise power which can be utilized to determine the sensitivities. This capability is especially very helpful in optimization phase of design flow. Moreover, by analyzing the breakdowns of contributions from the individual independent noise sources, the correlation between performance variations can also be calculated.

B. Simulation ExamplesThe benchmark results of the noise-based mismatch

analysis and 1000-run monte-carlo simulations are compared in TABLE II. in three cases: comparator input offset, logic path delay, and 5-stage ring oscillator. It is evident that the proposed noise-based analysis is much faster than traditional monte-carlo simulations and the results slightly deviate from the actual value that confirms the accuracy of this method.

C. LimitationsWhile the noise-based method is an efficient and

powerful technique, it relies on linear perturbation models. Therefore, it is only valid for small mismatches. For example, it has been shown by authors that the prediction error becomes greater than 10% when the 3σ of drive current mismatch is larger than 38%. Also the PNOISE considers Gaussian distribution only and cannot be employed directly for non-Gaussian distributions. Moreover, as noted earlier, the circuit must have a steady-state response or it must be possible to push it into a steady-state condition. However, there are some circuits (like strobe comparators) that cannot be configured in any way to show steady-state response.

TABLE II. BENCHMARK SUMMARY

Test Case

CPU Time Results (s)

Proposed1000-pt Monte-Carlo

Proposed1000-pt Monte-Carlo

Comparator Input Offset 21.6 sec 24373 sec 28.741 mV 28.775 mV

Logic Path Delay 5.52 sec 1990 sec

A: 1.925 ps

B: 5.518 ps

A: 2.004 ps

B: 5.174 ps

5-stage Ring

Oscillator6.09 sec 652 sec 69.34 MHz 69.96 MHz

III. PERFORMANCE-ORIENTED STATISTICAL PARAMETER REDUCTION OF PARAMETRIZED SYSTEMS

VIA REDUCED RANK REGRESSION

Due to the large number of global and local sources of manufacturing variations, the complexity of the computation is very high. For example, an analog data path delay model in a circuit consisting of several hundred transistors depends on thousands of parameters and the correlations among all of them. This paper ([2]) addresses the challenge of high-dimensional process variations by proposing a performance-oriented parameter dimension reduction technique. Also, by using the reduced rank regression (RRR) technique, they systematically identify the most important reduced parameter sets and compute both reduced-parameter and reduced-parameter-order models which are very efficient.

Principle component analysis (PCA) is the most popular traditional technique that compares parameters without considering their different impacts on the overall performance. PCA obtains parameter reduction by performing variable transformations and comparing a few linear combinations of the original variable to capture the most of statistical variation of the data. This is done by finding the eigenvalues of the covariance matrix of the original parameters. Its physical meaning is to find the principle directions by choosing the parameters with largest variances [3]. However, since it neglects the parameters impacts on performance, it may not be effective or even can result in misleading in some cases. Therefore, it is essential to modify the parameter reduction techniques such that they take the impacts of the parameters on the performance into consideration.

A. Reduced rank regression (RRR)The difference between RRR and PCA is shown in

Figure 2. A reduced rank model is essentially used as a means to reveal the redundancy in the predictor variables (process variations) to perform the parameter reduction. the key idea is that the trend in RRR is minimizing the statistical error in Y where Y does not have to be the circuit performance of interest and can be chosen to be some other easily computed circuit parameters closely related to the performance.

Figure 2. Comparison between PCA and RRR

B. Statistical Circuit Model Generation with Parameter ReductionThe circuit is divided into several regions spatially and the

local variations are introduced to capture spatial process variations. A full account of global and local variations can lead to a large set of variables. However, if we are only interested in analyzing the circuit performances at the output nodes, the effective parameter dimension of a given network may not be very large since the specific circuit structure can hide certain parametric variations and may even introduce canceling effects between multiple variations. In the proposed approach, an easily computable set of variables which have close connection with the performance is chosen. For example, in the case of modeling the delay of interconnect, the transfer function moments are chosen as the dependent variables based on their strong correlation with timing performance. RRR is then utilized to perform parameter reduction.

C. Limitations The proposed technique does the parameter reduction

over canonical terms rather than original parameters than results in less efficiency. Moreover, this technique is limited to circuits with weak nonlinear performance and does not show enough accuracy in highly nonlinear circuits. Since analog/mixed-mode circuits are usually very sensitive and show high nonlinearity as a result of process variations, this technique is not efficient in addressing the application of analog/mixed-mode circuit design and requires more refinement.

IV. PARAMETER REDUCTION FOR VARIABILITY ANALYSIS BY SLICE INVERSE REGRESSION METHOD

As mentioned, earlier, the conventional PCA neglects the impacts of the parameters on performance. For instance, consider two different functions (performance parameters) which have different relations on common process parameters. Using PCA results in the same principle components for both of them while they could

be totally different performance parameters. The performance oriented parameter reduction technique in [3] can be compared with PCA as shown in Figure 3.Where PCA method has functions depending on parameters whereas the performance based approach has functions depending on principle components that are linear combinations of parameters.

(a) (b)

Figure 3. Using a new set of parameters. (a) original function and original set of parameters, (b) a new set of parameters and new function

that approxiamtes the original function.

Principle Hessian direction (PHD) based parameter reduction utilized in this paper, aims nonlinear dependency of circuit performance on process parameters for each device and the correlations between devices. The random parameters are categorized in to three classes: global, local, and correlated parameters. The impacts of these parameters on performance are measured by using a Hessian matrix that contains the information about the sensitivities. According to the definition, given p as process parameter vector, the Hessian matrix of performance, ɸ(p), provides the second order derivatives. Therefore, the Hessian matrix is a symmetric matrix as:

(1)

where n is the length of the parameter vector.

Compared with other performance based parameter reduction, this approach results in a significantly smaller reduced set of parameters. Moreover, despite the previously introduced technique in Section III, it directly reduces the number of parameters rather than the number of canonical terms. An average of 53% of reduction is reported with less than 3% error in the mean value and less than 8% error in the variation while the traditional PCA can only get 30% reduction with similar errors. An example comparing the pdf and cdf of an interconnect delay obtained from MC simulations and PHD is shown in Figure 4.

Figure 4. Numerical examples: interconnect delay

V. CAPTURING DEVICE MISMATCH IN ANALOG AND MIXED-SIGNAL DESIGNS

This paper proposes a new comprehensive methodology to capture device mismatches impact on analog/mixed-mode circuit performance. This methodology includes three aspects: first, a new compact device mismatch model is proposed that provides an accurate correlation matrix including geometric variation, location-dependent variation, and their interactions. This compact, yet accurate and complete, model helps dramatically reducing the computation complexity. Second, a parameter reduction approach based on PHD (discussed in the precious Section) is employed that connects parameters with performance of the circuit and captures high order nonlinearity accurately. Third, a method based on Chebyshev Affine Arithmetic (CAA) is introduced to extract cdf performance bounds (the best/worst case points).

A. The Proposed Design FlowFigure 5. depicts the proposed design flow suitable

for general analog circuit design. Starting from SPICE netlist, first a finite point model provides a new compact device model to support mismatch and correlated devices. This model should have sufficient model-to-silicon matching to capture the underlying mechanisms including primary variation sources and the layout dependence. Moreover, such model should be highly efficient to support large-volume statistical simulations. In the next step, PHD based approach reduces the number of device parameters. After that, CAA is utilized to analyze the circuit with uncertainty and to generate the performance bounds. According to the experimental results, this methodology is able to predict reliable performance bounds for circuits with different complexities in both time domain and frequency domain.

Figure 5. The proposed design flow

B. Experimental ResultsTo demonstrate the efficiency of the proposed

technique, some experimental results are reported. As an example, a complicated, high gain, rail to rail output, CMOS operational amplifier implemented in 90 nm technology is considered. Gaussian distributions for random variables are considered. In frequency domain analysis on open-loop amplifier, the results are compared with the results obtained from Monte-Carlo simulations as shown in Figure 6. As displayed by Bode plots, even at high frequencies, the estimated bounds are close to bounds found by MC simulations. Moreover, a time domain analysis shown in is also provided. The proposed method shows less than 2% error.

These results demonstrate the effectiveness and comprehensive feature of the proposed methodology that addresses different issues including: accurate compact mismatch model, efficient parameter reduction, and accurate cdf extraction to determine the upper and lower bounds.

Figure 6. Frequency response comparison between the bounds from the new methodology and MC bounds for the opamp circuit

Figure 7. Transient response comparison between the new bounds and MC bounds for the opamp circuit.

VI. ASYMPTOTIC PROBABILITY EXTRACTION FOR NON-NORMAL DISTRIBUTIONS OF CIRCUIT

PERFORMANCE

This paper ([5]) addresses the non-normal distributions for circuit performance resulting from nonlinear response surface modeling which is used to accurately model the performance uncertainty due to the parameter variations. A novel asymptotic probability extraction methodology named APEX is proposed to estimate the pdf/cdf functions using nonlinear response surface modeling.

APEX applies moment matching to characterize the characteristic function of the performance parameter that is the Fourier transform of the probability density function. This is done by approximating the characteristic function by a rational function H. By converting the problem to a problem in system area, H is considered as the transfer function of e linear time-

invariant (LTI) system. Therefore, the pdf and cdf of the performance parameter are approximated by the impulse response and the step response of the LTI system H.

A. Methodology Flow APEX shows three main contributions that

significantly reduces the computation cost and improves the approximation accuracy. First, a binomial evaluation scheme to recursively compute the high order moments for a given quadratic response surface model is proposed. The binomial moment evaluation is obtained from statistical independence theory and principle component analysis (introduced in Section II). Shown in Figure 8. , it consists of two steps: model diagonalization and moment evaluation. It is shown that it can achieve more than 106 x speed-ups compared with direct moment matching.

In the second step, APEX approximates the unknown probability distribution function by the impulse response of an LTI system that is conceptually shown in Figure 9.Therefore, the performance f corresponds to time and the pdf and cdf of performance, pdf(f) and cdf(f) are corresponding to h(t) and s(t), which are the impulse response and the step response of the system with transfer function H, respectively. Moreover, since an LTI system is a casual system (it has zero values for negative variable), APEX applies a generalized Chebyshev inequality for pdf/cdf shifting to determine the correct value for amount of shift. Finally, the best-case and worst case performance metrics are extracted based on a reverse evaluation technique that can give accurate estimation for both upper and lower bounds.

Figure 8. The proposed binomial moment evaluation

Figure 9. Converting the problem to system theory domain

B. Numerical ExamplesAn implementation of APEX for a complex

operational amplifier implemented in IBM 0.25 um process is reported. After PCA, 49 principle random factors are identified to represent the process variations and device mismatches. TABLE III. summarizes the

error of the linear and regression modeling for different performance parameters. Also a comparison with linear regression for best/worst case points estimation is summarized in TABLE IV. It is demonstrated that APEX can achieve a 100 times speed-up in comparison with Monte-Carlo simulations with a million samples while it shows much more accuracy than linear regression.

TABLE III. REGRESSION MODELING ERROR FOR OPAMP

PERFORMANCE LINEAR APEX

Gain 3.92% 1.57%

Offset 21.80% 7.49%

UGF 1.14% 0.45%

GM 0.96% 0.52%

PM 1.11% 0.41%

SR (P) 0.82% 0.66%

SR (N) 1.27% 0.44%

SW (P) 0.38% 0.16%

SW (N) 0.36% 0.12%

Power 1.00% 0.64%

TABLE IV. COMPARISON OF ESTIMATION ERROR

PERFORMANCE

LINEAR APEX

1% 99% 1% 99%

Gain 22.7% 10.4% 1.45% 0.32%Offset 11.5% 74.7% 0.58% 3.20%

UGF 3.78% 4.30% 0.03% 0.18%

GM 2.72% 2.46% 0.08% 0.04%

PM 4.41% 3.79% 0.13% 0.02%

SR (P) 0.81% 0.97% 0.11% 0.07%

SR (N) 3.83% 4.31% 0.13% 0.24%

SW (P) 0.13% 0.03% 0.16% 0.06%

SW (N) 0.06% 0.03% 0.09% 0.01%

Power 0.69% 0.65% 0.11% 0.00%

VII. SUMMARY AND CONCLUSION

In this brief, some innovative methods of estimating the impacts of process variations on the performance of analog/mixed-mode circuits are described. The main issues addressed by these papers include: large number

of variation sources particularly in nano scaled technologies, high sensitivity of analog circuits to process variations requiring more accurate nonlinear techniques, high computation cost, and accurate estimation of cdf bounds.

In [1], DC mismatches are modeled as AC pseudo-noise and utilizing the fast periodic noise analysis (PNOISE) tool embedded in RF simulators, impacts on performance are computed efficiently. While the noise-based method is efficient and powerful technique providing valuable information about the performance variation as well as sensitivities and correlations, it relies on linear perturbation models. Hence, it is only valid for small mismatches. Moreover, the circuit must have a steady-state response or it must be possible to push it into a steady-state condition. However, there are some circuits (like strobe comparators) that cannot be configured in any way to show steady-state response.

[2] and [3] propose two novel techniques to reduce the number of parameters while taking the performance orientation into account. These techniques are especially important in analog/mixed-mode circuit design where the number of variation sources is very high but they don’t cause the same impacts on circuit performance. Therefore, performance oriented parameter reduction techniques are very helpful to reduce the order and the dimension of process parameters more efficiently.

[4] and [5] propose methodologies to efficiently capture the impacts of mismatch and process variations on the circuit performance. The methodology proposed in [4] is a good example of a comprehensive design flow dealing with different issues (accurate and efficient compact mismatch modeling, parameter reduction, and cdf bound estimation) in the design and optimization phases of analog/mixed-mode circuit design. The methodology proposed in [5] is a novel technique that converts the problem to a known system theory problem and demonstrates accurate results. However, it doesn’t give a clear solution for high number of parameters and it is doubtful to be computationally efficient and accurate in such cases.

References[1] J. Kim, K. Jones, and M. Horowitz, “Fast, non-monte-carlo

estimation of transient performance variation due to device mismatch,” in DAC 2007.

[2] Z.Feng and P. Li, “Performance-oriented statistical parameter reduction of parametrized systems via reduced rank regression,” in ICCAD 2006.

[3] A. Mitev, M. Marefat, D. Ma, and J. Wang, “Parameter reduction for variability analysis by slice inverse regression method” in ASPDAC 2007.

[4] J. Wang, Y. Cao, and M. Chen, “Capturing device mismatch in analog and mixed-signal designs,” in IEEE Circuits and Systems magazine.

[5] X. Li, J. Le, P. Gopalakrishnan, and L. Pieleggi, “Asymptotic probability extraction for non-normal distributions of circuit performance,” in ICCAD 2004.