Parallel Parallel compressing system compressing system

for satellite for satellite on programmable on programmable

chipchip

Yifat Manzor Yifat Manzor & & Reshef Dahan Reshef Dahan

Supervisor: Eran SegevSupervisor: Eran Segev

Part Part BB

SatelliteSatellite image Input image Input Data rateData rate

from one sensor linefrom one sensor line B/W Picture Range – 2.5 km width Velocity - 8 km/sec 4 Pixels per 1m²

Rate = 80 Mpix/sec

Streaming Data 12-bit per pixel

5,000 pix

16,0

00 li

nes/

sec

80 Mpixel image

System demands:System demands: »» 80Mpix/sec input data rate.80Mpix/sec input data rate.»» Image width – 5000 pixel Image width – 5000 pixel

ADV202ADV202Single compressing chip Single compressing chip capabilities:capabilities: »» 27 Mpix/sec maximum input 27 Mpix/sec maximum input data ratedata rate» 25 MByte/sec maximum output » 25 MByte/sec maximum output rate rate »» Maximum image width – 4096 Maximum image width – 4096 pixel pixel » Maximum image length – infinity» Maximum image length – infinity

Solution Solution MAIN IDEAMAIN IDEA

To generate parallel

processing by separating the

picture to 3 compressors

1667pix 1667pix 1666pix

3

16,0

00 li

nes

/sec

Tile

Memory

ADV202ADV202

Data in

System DescriptionSystem Description

camera

XILINX

Virtex2Pro

ADV202modelmodel model

Checksum Generator

Data Generator

RESET

LED

Compressor Compressor Compressor

ControllerSystem

CONTROLLERCONTROLLER

CONTROLLER CONTROLLER block diagramblock diagram

Compressed data

Input DataDIVIDER

Compression Unit

Compression Unit

Compression Unit

MERGER

DividerDivider

DIVIDER

Compression Unit

Compression Unit

MERGER

Compression Unit

Divider Simulation Divider Simulation ResultsResults

compression compression unitunit

DIVIDER

Compression Unit

Compression Unit

Compression Unit

MERGER

25MHz

Compression unitCompression unit - - ArchitectureArchitecture

27MHz

funnel adv_202model

comp_databuff

Interrupt_generator

From divider

80MHz

8 bits12 bitsTo/from merger

To merger

80MHz

Compression unit Simulation Compression unit Simulation ResultsResults

mergermerger

DIVIDER

Compression Unit

Compression Unit

Compression Unit

MERGER

compressed data

package

header

OutputOutput:

MergerMerger - Architecture - Architecture

headergenerator

calculator

80MHz

To/from unit 0

To/from unit 2

To/from unit 1 Compressed output

25MHz

MergerMerger – Architecture cont – Architecture cont..calculatorcalculator

Interrupt from unit 0

outputgenerator

queuegenerator queue

To\from header generator

Data to/from unit 0

Data to/from unit 1

Data to/from unit 2

80MHz

Interrupt from unit 2

Interrupt from unit 1

25MHz

Compressed output

Merger Simulation Merger Simulation ResultsResults

ControllerControllerSimulation ResultsSimulation Results

Testing EnvironmentTesting Environment

DIVIDER MERGER

Comp.

UnitComp.

UnitComp.

Unit

Virtex2Pro

Generator

Check Results

Memory

Data inSystemSystem

DIVIDER MERGER

Comp.

UnitComp.

UnitComp.

Unit

Controller

Data Generator

ChecksumGenerator

RESET LED

Virtex2Pro

DCM

Testing EnvironmentTesting Environment

SystemSystem

Simulation ResultsSimulation Results

SummarySummary

Summary ContSummary Cont..