parascale : exploiting parametric timing analysis for real-time schedulers and dynamic voltage...
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ParaScale : Exploiting Parametric Timing Analysis for Real-Time
Schedulers and Dynamic Voltage Scaling
Sibin Mohan1
Frank Mueller1,William Hawkins2, Michael Root3, Christopher
Healy3, David Whalley4
1 : North Carolina State University, Centre for Embedded Systems Research
2 : University of Illinois, Urbana-Champaign, 3 : Furman University,
4 : Florida State University
Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 2
Outline
Motivation Static Timing Analysis Parametric Timing Analysis Using Parametric Timing Analysis Framework Experiments and Results Conclusion
Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 3
Motivation
Worst-case execution time (wcet) obtained by Static timing analysis Dynamic timing methods (proven unsafe)
Static Timing Analysis Upper limits on loop bounds known at compile
time Results in large overestimations Provides single numeric value
Places limits on real-time designersType of code that may be used in tasks
Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 4
Static Timing Analysis
for( i = 0 ; i < n ; ++i )Loop Body ;
Consider the following piece of code…
Value must be known at compile time
Result : WCET = 1000 cycles (say)
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Parametric Timing Analysis
Calculate : formula /closed form for WCET
Formula depends on number of loop iterations
Evaluated at run-time
Results used for… scheduling decisions power savings etc.
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Parametric Timing Analysis (contd.)
For the previous example…
for( i = 0 ; i < n ; ++i )Loop Body ;
Result : WCET = 102 * n (say)
Number of cyclesto execute Loop Bodyfor above example
Value must be known prior to loop entry
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Parametric Timing Analysis (contd.)
In practice…
for( i = 0 ; i < n ; ++i ) Loop Body ;
Call IntraTaskScheduler(evaluate_loop_k(n)) ;
int evaluate_loop_k( int loop_bound){
return ( 102 * loop_bound ) ;
}
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Flow of Parametric Timing Analysis
C source file
Parametric Timing Analyzer
C source file annotated with
Parametric Evaluation functions
Has Parametric formula changed?
YES
Send Annotated C source file to Parametric Timing Analyzer
NO
Use Annotated C source file for execution on Simulator
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Insert Parametric Formulae into Task Code
Timing analysis of function with parametric loop Loop analyzed and parametric evaluation function generated
Numerical Analysis of generated function complete Timing analysis if function with parametric loop complete
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Use of Parametric Timing Analysis
Evaluate parametric expressions at run-time Based on actual loop bounds at run-time
Transfer control to dynamic scheduler
Newly-calculated WCET sent to scheduler Calculate savings in execution time
Savings exploited by scheduler to… admit additional tasks reduce operating frequency/voltage save
power
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Unique advantages of our work
Exploit early knowledge of execution of tasks Especially knowledge about future execution of loops
Tightly bound execution for remainder of task
Intra-task DVS algorithm slows down processorAs execution proceeds processor slowed down furtherSaves power!
Other DVS algorithms:Task execution sped up as deadlines approach
Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 12
Framework
C Source FilesC Source
FilesC Source Files
gcc PISA Compiler
Numeric WCET Bound
Numeric Timing
Analyzer
Instruction/data info
p-compiler
assembly
Parametric Timing
Analyzer
C Source Files & Parametric
Functions
C Source Files & Parametric
Functions
C Source Files & Parametric
Functions
Scheduler
Energy/power values
Wattch Power Model
SimpleScalar Simulator
Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 13
Framework (contd.)
p-compiler Works on assembly files as input Extracts information about instructions and data
Timing Analyzers Numeric : provides constant, numeric WCET bound Parametric : provides parametric formulae as WCET
Schedulers Frequency/Voltage lowered during execution Set to levels for last executing task instance
SimpleScalar simulation framework Capable of handling multiple threads of execution Can be configured for simple processor, SMT, CMP, etc.
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Experiments
Energy measurement techniques…Perfect Clock Gating (PCG)Perfect Clock Gating with Leakage (PCGL)
ParaScaleOur combined intra-task and static inter-task DVS
Parameter Range of Values
Utilization 20%, 50%, 80%
Ratio WCET/PET* 1x, 2x, 5x, 10x, 15x, 20x
Base
DVS Algorithms Static DVS
Parametric
ParaScale
* Parametric Execution Time
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Energy Consumption : 2x, PCG
0
50
100
150
200
250
300
350
400
450
500
base static DVS parametric ParaScaleUtilization
En
erg
y C
on
su
mp
tio
n(m
J) 20%
50%
80%
Energy consumptions, assuming no leakage, for various utilizationsDVS Schemes
Least consumption: ParaScale (for all cases)
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Energy Consumption : 2x, PCGL
0
500
1000
1500
2000
2500
3000
base static DVS parametric ParaScaleUtilization
En
erg
y C
on
su
mp
tio
n(m
J) 20%
50%
80%
Energy consumptions, leakage considered, for various utilizationsDVS Schemes
Least consumption: ParaScale (for all cases)
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Energy Consumption: 10x, PCG
0
20
40
60
80
100
120
140
base static DVS parametric ParaScale
Energ
y C
onsu
mpti
on(m
J)
20%
50%
80%
Energy consumptions, assuming no leakage, for various utilizations and DVS Schemes for 10xLeast Consumption : ParaScale
Overall savings are lower due to greater slack
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Energy Consumption: 10x, PCGL
0
500
1000
1500
2000
2500
3000
base static DVS parametric ParaScaleUtilization
Energ
y C
onsu
mpti
on(m
J)
20%
50%
80%
Energy consumptions, leakage considered, for various utilizations and DVS Schemes for 10xLeast Consumption : ParaScale
Overall savings are lower due to greater slack
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Energy Consumption trends (PCG)
0
50
100
150
200
250
1x 2x 5x 10x 15x 20xWCET Factor
Ene
rgy
Con
sum
ptio
n(m
J)20%
50%
80%
Energy consumption (hence savings) for ParaScale:Drops as ratio of WCET/PET is increasedDue to greater slack available in the system
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Energy Consumption trends (PCGL)
0
50
100
150
200
250
300
350
400
1x 2x 5x 10x 15x 20xWCET Factor
En
erg
y C
on
sum
pti
on
(mJ)
20%
50%
80%
Energy consumption affected byLeakage power prevalent in systemRelative savings lower
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Scheduler Overhead: Utilization 50%
0
500
1000
1500
2000
2500
3000
1x 2x 5x 10x 15x 20x
Ex
ecu
tio
n T
ime u
sed
by
Sch
ed
ule
r (
ns)
base static DVS
parametric ParaScale
Scheduler overheads greatest for ParaScale Power savings still significant
Due to lowering of voltage/frequency for schedulers
22
Conclusion
Fixed-point approach To embed parametric formulae Bounds WCET of application + parametric code
Provide lower WCET bounds during execution Prior to entry into loops
Quantify savings in terms of Power savings ParaScale: combined inter and intra-task DVS
Savings of 66-80% ! Power savings over DVS-oblivious techniques.
Mainly due to knowledge about: Past execution Future execution due to parametric formulae
Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 23
Thank You !
Questions ?