pcim 2011 current

8/12/2019 Pcim 2011 Current

http://slidepdf.com/reader/full/pcim-2011-current 1/7

PCIM Europe 2011, 17.-19. May 2011, Nuremberg, Germany Paper 28

PCIM 2011 182 Klarenbach, Schmirgel, Krah

Fi g. 1. Ideal current control loop with simple PI-

controller and motor time constant T e

Fi g. 2. PWM carrier signal with continuous trajectory

of reference values and latched (discrete) refer-

ence values showing the sample & hold behav-

ior.

Design of Fast and Robust Current Controllers for Servo Drives

based on Space Vector Modulation

Christoph Klarenbach, Heiko Schmirgel, Jens Onno Krah ([email protected])

Cologne University of Applied Sciences, Betzdorfer Str. 2, 50679 Köln, Germany

Abstract

The traditional discrete current control for servo drives is compared with two different predictive current

control approaches – Smith Predictor and Luenberger Observer. The achievable closed loop control

bandwidth and the robustness against model parameter uncertainties as a function of the switching

frequency are discussed, as well as the current measurement method and the algorithm computing

technology for different applications in conjunction with several sampling techniques.

1 Introduction

Highly dynamic machine tool applications require the fastest possible response to velocity and/or

position commands. To meet these requirements with limited resources, the respective control loops in

turn rely on a fast current control loop. Small current rise times can only be achieved with low electrical

motor time constants. Since the plant of the controller can be represented by a first order lag element

and the electrical motor time constant as in (1),

e = s s (1)

current control can be designed utilizing a simple PI-controller, fi g. 1 . However, in a real system the

current measurement, the discrete control in conjunction with the pulse width modulation (PWM) and

the algorithm processing time add dead times to the loop and limit the achievable bandwidth.

High PWM frequencies generate a smaller current ripple and enable high current loop bandwidth, butalso increase switching losses. The heat dissi-

pation results in a nominal current derating.

Carrierless PWM methods are often associat-

ed with special predictive control algorithms

[1]. Until now the high demand on computing

power limits the switching frequency to approx-

imately 5 kHz which is on the other hand too

low for high performance applications. Today

most of the servo drives on the market use a

cascaded control structure in combination with

field oriented control (FOC). FOC is mostlyused with carrier based PWM methods. The

bandwidth of the (inner) current loop limits the

bandwidths of all superposed control loops

and therefore the dynamic of the entire drive

[9].

The goal of the discussed predictive control

methods is to provide high current loop band-

width with medium switching frequencies.





Fi g. 3. Open loop crossover frequency to PWM

frequency ratio f co/ f PWM depending on the to-

tal dead time T dΣ and the allowed closed loop

peaking

2 Pulse Width Modulation

Most FOC implementations use carrier based PWM methods, fig 2 . Where the voltage command in

space vector representation can be used directly as input to the modulator, it is referred to as Space

Vector Modulation (SVM). Existing modulation schemes differ in the achievable modulation index and

the harmonic spectrum in relation to implementation effort and cost. Inside an FPGA the implementa-

tion of the SVM combined with continuous transition to block commutation is possible with medium

effort on FPGA resources (logic elements) [11].

The gate signals of the inverter are handled by the PWM for all carrier based modulation schemes in a

similar way. They are generated through comparison of the reference signals with the PWM carrier

signal. Afterwards the gate signals of the individual inverter switches are calculated with additional

dead times to prevent short circuits.

The reference values are traditionally latched by the PWM at the reversal points of the carrier signal,

twice during each carrier signal period. This leads to the common current loop sub-cycle frequency of

f s = 2 f PWM (and T s = ½ T PWM).

In control theory, the behavior of the carrier based PWM sub-cycle is equal to that of a sample & hold

(S&H) element. The current ripple (harmonic content) is ignored. Therefore, the phase lag introducedinto the current loop by the PWM can be determined from the Laplace transfer function of the hold

element GH( s):

= e (2)

With s = jω, equation (2) can be written as (3).

= (3)

It can be seen from (3) that the S&H element introduces a dead time of T s/2 into the current loop [8].

3 Current ControllerThe current controller is updated with twice the PWM carrier frequency. The industrial standard known

limit for any kind of control response time is

one sampling time T s. For current control this

means that the actual value of the motor cur-

rent reaches the command value within only

one calculation sub-cycle T s. In discrete control

theory this goal can be described by the closed

loop discrete transfer function of a single delay

Gcl( z ) = z -1

for first order systems. The definition

of this resulting transfer function is the origin of

the well known dead beat controller approach

[7].

If the S&H element is approximated by a pure

dead time of T s/2, without consideration of its

gain response, the gain crossover frequency f co

of the current loop is 2.547 kHz at 8 kHz

switching frequency. In the current loop bode

plot these settings produce a closed loop gain

response with 0 dB peaking.





Fi g. 4. Current loop block diagram for a traditional

µC/DSP implementation. The dead time amount of

one sub-cycle due to the algorithm calculation and

a half sub-cycle due to the PWM.

With more aggressive parameters that

lead to 3 dB peaking in the closed loop

bode plot, a gain crossover frequency of

f co = 4 kHz can be achieved [12]. A com-

parison of achievable open loop crosso-

ver frequencies for varying effective totaldead times T dΣ is shown in fi g. 3 .

The described controller characteristics

require an ideal controller environment

which is rarely available in reality. Usual-

ly, there is at least an EMI filter in the

feedback path that introduces an addi-

tional phase lag into the current feedback

signal. Also the control algorithm is performed with a certain processing time which is greater than

zero and adds an additional dead time. Both effects decrease the achievable control loop bandwidth.

Traditionally, the algorithm of the current controller is implemented in an interrupt service routine (ISR)

of a µC or DSP. The actual values of the phase currents are usually measured by 12 bit successiveapproximation (SAR) ADCs. Sampling should be carried out at the harmonic-free time instances of the

reversal points of the PWM carrier signal to avoid additional anti-aliasing filtering [2]. Subsequently the

voltage command values for the PWM are calculated before they are latched at the next reversal point

of the carrier signal, fi g. 5 . For that reason the processing time is increased to one full sub-cycle T s.

This leads to a total dead time T dΣ = 1.5 T s (ADC conversion time + controller processing time + PWM)

[4] that reduces the achievable gain crossover frequency to f co ≈ 1.3 kHz at 8 kHz PWM frequency,

fi g. 3, 4 .

Fi g. 5. Sequence of sampling, calculations and PWM activity for a µC/DSP implementation in relation to the

PWM carrier signal and resulting phase current.

3.1 Smith Predictor A Smith Predictor is an algorithm that was invented for systems with significant time delays [6]. It was

shown in [5] that this control strategy is also suitable for a digital current control loop. The great ad-

vantages of a Smith Predictor enhanced control loop is the applicability to virtually any plant with sig-

nificant delay time that can be modeled with sufficient accuracy and the possible implementation pure-

ly in software algorithms. The idea behind the algorithm is to use the output of the current controller

(the voltage command vS), which is available before all dead times take effect, and predict the result-

ing current i by means of a model before the feedback measurement can deliver the value.

The plant of the current control loop (the windings of the motor) is well known and can be modeled in a

fairly simple way (first order lag element defined by the time constant T e (1)). The back EMF is





Fig. 6. Current loop block diagram including

processing dead time T s ( ADC conversion

time + controller processing time) and

smith predictor

changing slowly with respect to the current and can therefore be neglected in this model. This leads toa smith predictor structure with limited complexity that only depends on parameters that are usually

already known.

The predicted current signal (the effect of the voltage command on the L- R-model) is made available

to the feedback loop before the delay time simply by adding the predicted current to the feedback sig-

nal, fi g. 6 . The feedback loop then “sees” the predicted value of the current at the same time, when it is

actually generated. However, the predicted signal has to be subtracted from the feedback signal again

after the dead time has elapsed, because at that time the regular feedback signal contains the infor-

mation of the real effect of the voltage command. Therefore, in the predictor branch of the current con-

trol loop, the L- R first order lag and the dead time are interchanged and the delayed predicted current

is subtracted. The subtraction in combination with the dead time leads to a pulse function of the length

of the dead time as described in [6].

The complete current control loop including the smith predictor is shown in fi g. 6 . In digital motion con-

trol systems this structure is easily implemented. Equation (4) shows the transfer function of the smith

predictor branch.

= (4)

The first part of (4) is the describing model of the controller plant and the second part is the pulse func-

tion, mentioned above. Provided that the model parameters are accurate the dead time resulting from

ADC conversion time & controller processing time is completely eliminated inside the feedback –loop

of the resulting system and only appears outside of it, thus having no effect on the system dynamics

with respect to command response [5].

In practice this means that concerning the command response the controller task is reduced to com-

pensating the prediction error and the dead time only affects disturbance rejection. Due to the higher

gain also disturbances are reduced more effectively. Of course, this also means that the control en-

hancement greatly depends on the accuracy of the model, however experience shows that the predic-

tion algorithm is robust enough to improve performance even with coarsely tuned model parameters.

Fig. 7 illustrates the step responses of the system and the individual elements in fi g. 6 . A voltage com-

mand step at t = 0 is shown in black. The step response including the dead time as seen in the feed-

back signal is shown in red. The green line represents the predicted response without dead time (=

response of the plant model). As explained above the fact that the feedback signal will contain the

measured value of the current after the dead time is accounted for by multiplying the model transfer

Fi g. 7. Step responses of the Smith Predictor ele-

ments: delayed feedback signal (red ), result-

ing prediction signal (blue) and predicted re-

sponse ( green)

0 t0

1





function with a pulse function of the length of the dead time. The resulting prediction signal of the smith

predictor is shown in blue.

This improvement raises the limit of possible performance to values that can normally only be reached

with significantly (about 70%) higher PWM frequencies.

3.2 FPGA based Current ControlHowever, an approach with higher dynamic capability is the implementation of the current control algo-

rithms inside an FPGA. Massive parallel processing reduces dead times added by the algorithm pro-

cessing to nanoseconds. This remaining dead time is insignificant in comparison to that of the PWM

[12].

ΔΣ - Phase Current Measurement

In motor control applications, ΔΣ-AD conversion is done by a hardware ΔΣ modulator that converts

the analog voltage input into a one bit data stream. Common frequencies of ΔΣ modulators for motor

control applications are f dΣ = 10…20 MHz [3]. In the FPGA, the bit stream is converted into a digital

word by a decimation filter.

Fi g. 8. Step responses of the classic (red ) and the pseudo interlaced sinc³-filter (violet ).

As decimation filter a sinc³-filter is a good compromise, because it provides the required performance

at low hardware effort (logic elements). Its discrete transfer function is given by (5) where M is the

decimation ratio of the filter.

=

(5)

With the use of few more logic elements a pseudo interlaced sinc³-Filter can be built, which delivers a

nearly continuous output signal [11]. Due to the anti aliasing effect of the sinc³-filter no additional EMI

Filter is necessary. The step response of the classic and the pseudo interlaced sinc³-filter are shown in

fi g. 8 . The relevant time constant of the filter can be determined graphically from the linear controlplane [8]. It can also be calculated from the transformation of the discrete transfer function to the fre-

quency domain.

= s( )

s( )

⏟

( )⏟

(6)

Respecting equation (6) the time constant of a sinc³-filter can be approximated by (7).

s (7)

0 16 32 48

100%

75%

50%

25%

Step Function

σ (t )

Step ResponseIdeal

g (t )

Step ResponseClassic Sinc³ - Filter

g (k T )sinc³ sinc³ ΔΣ

Weighting Function

h (t )sinc³

0 64 128 192T sinc³

T ΔΣ

k

M = 64

0%

Step Response PseudoInterlaced Sinc³ - Filter

g (k T )sinc³ ΔΣ





Fi g. 9. Block diagram of the Luenberger current

Observer which compensates the sinc³-filter

delay and suppresses EMI noise

Fig.10. Dual-feedback current control scheme [13]

The modulator bit stream is filtered by three parallel sinc³-Filters with different decimation ratios: Cur-

rently available ΔΣ modulators provide modulator frequencies up to 20 MHz. For this modulator fre-

quency, the following configuration reasonable [11]:

1. Fast decimation filtering for over-current detection with low precision (≈ 8 bit)

M = 16, T sinc³ = 1.2 µs

2. Fast decimation filtering for the proportional component of the current controller with medium

precision (≈ 12 bit) M = 64, T sinc³ = 4.8 µs

3. High precision acquisition in combination with integrating the signal over the specified PWM

period = ⁄ (≈ 14 bit) M = 128, T sinc³ = 9.6 µs

The ΔΣ modulator generates the bit stream with negligible delay. Therefore, the dead time of the cur-

rent measurement depends on the ΔΣ modulator frequency and on the decimation ratio, the filter or-

der of the decimation filter (7).

Luenberger Observer

Utilizing an FPGA based current observer, the delay time of the sinc³-filters can be fully compensated.

Its output delivers a continuous current signal with suppressed EMI, no gain attenuation and no phase

lag in relation to the real motor current.

The observer relies on a simplified machine model with the electrical parameters of the motor wind-

ings, Rs and Ls, fi g. 9 . Parameter uncertainties can cause the delay time compensation to lose preci-

sion and increased noise content in the output signal. However, the quality of the output signal would

still be good enough to serve as feedback for a normally tuned current controller.

Dual feedback current control

The dual feedback current control combines the

advantages of two common sampling methods:

The slower, high-precision integrated current

signal is used as feedback value for the inte-gral part of the PI-controller.

The fast feedback signal from the observer is

used for the proportional component of the PI

current controller, enabling high system band-

width, fi g 10 .

Because stationary accuracy is achieved with the

integral part and the maximum current ripple is

small enough, the actual sample time instance of

the feedback signal used for the proportional com-

ponent is not important any more. For that reason

the actual value of the current can be latched bythe current controller for the algorithm calculation

time T alg at any time before the voltage command

value is latched by the PWM.

Due to the massive parallel algorithm calculation

the current controller relates to an analog control-

ler. (quasi-analog algorithm calculation) with negli-

gible calculation time (T alg < 200 ns). A dc current

error caused by aliasing (phase shift between

sampling and carrier) is not possible due to the

integrated current control structure. The delay of





the current measurement is fully compensated by the current observer. Considering the achievable

bandwidth only the S&H behavior of the PWM remains as limiting factor and introduces a phase lag.

Therefore ideal deadbeat behavior can be achieved with this control approach. Due to the negligible

algorithm processing time it is also suitable for high PWM frequencies.

4 Summary

Since the control plant of standard microcontroller based drive systems contains the electrical motor

time constant T e and the EMI-Filter time constant T m it can be modeled as second order system. In

addition the S&H behavior of the PWM (0.5 T s) and the controller processing time (1.0 T s) introduce a

total dead time of 1.5 T s into the current control loop.

In a microcontroller based current control loop it is possible to compensate the dead time T s by utilizing

the Smith Predictor. In a current control scheme with massive parallel processing inside the FPGA in

conjunction with fast ADCs this dead time does not exist.

Only with the additional use of an FPGA based current observer, the time constant of the EMI-Filter T m

(Sinc³-filter time constant) can be fully compensated, reducing the control plant to a first order system.

Therefore with an FPGA based current observer a nearly ideal deadbeat behavior can be achieved:

S&H Processing

T dΣ

(Total Delay)

T m

(EMI) Plant Order

Max. BW

f PWM = 8kHz

µC / DSP 0.5 T s 1.0 T s 1.5 T s Yes 2 1.5 kHz

µC / DSP + Pred. 0.5 T s - 0.5 T s Yes 2 2.5 kHz

FPGA 0.5 T s - 0.5 T s Yes 2 2.5 kHz

FPGA + Obs. 0.5 T s - 0.5 T s No 1 4 kHz

Because the current measurement and the algorithm calculation has to be accomplished within one

control sub-cycle T s, the microcontroller approach is limited in its PWM frequencies. The negligible

processing time with parallel algorithm calculation makes this restriction not applicable when using

FPGA based current control.

Literature[1] F. Morel, X. Lin-Shi, J.-M. Rétif, B. Allard, C. Buttay: “A Comparative Study of Predictive Current Control

Schemes for a Permanent-Magnet Synchronous Machine Drive”, IEEE Trans. Ind. El. Vol. 56, No. 7, 2009.

[2] J. Holtz: “Pulsewidth Modulation for Power Converters”, Proceedings of the IEEE, Vol. 82, No. 8, 1994, pp.

1194-1214.

[3] Avago Tech. Datasheet: HCPL 796J,AD converter

[4] J. Böcker, S. Beineke, A. Bähr: “On the Control Bandwidth of Servo Drives”, 13th European Conference on

Power Electronics and Applications (EPE2009), Barcelona, Spain, 2009

[5] H. Schmirgel, J. O. Krah, R. Berger: “Delay Time Compensation in the Current Control Loop of Servo Drives

– Higher Bandwidth at no Trade-off”, PCIM Conference, Nürnberg, 2006 pp. 541-546.

[6] O. J. M. Smith: “Closer Control of Loops with Dead Time”, Chemical Eng. Progress, Vol. 53, No. 5, 1957[7] S. Buso, S. Fasolo, L. Malesani, P. Mattavelli: ”A Dead-Beat Adaptive Hysteresis Current Control”, IEEE

Trans. Ind. App. Vol.36, No. 4, 2000

[8] S. Zacher, M. Reuter: “Regelungstechnik für Ingenieure”, 13th Ed., Vieweg + Teubner, Wiesbaden, 2011

[9] W. Leonhard: „Regelung elektrischer Antriebe“, 2nd

Ed., Springer 2000, ISBN: 3-540-67179-X

[10] B. E. Boser, B. A. Wooley: “The Design of Sigma-Delta Modulation Analog-to-Digital Converters”, IEEE

Journal of solid-state circuits, vol. 23, No. 6, 1988.

[11] J. O. Krah, C. Klarenbach: “Fast and High Precision Motor Control for High Performance Servo Drives”,

PCIM Conference, Nürnberg, 2010

[12] J. O. Krah, C. Klarenbach: “FPGA based Field Oriented Current Controller for High Performance Servo

Drives”, PCIM Conference, Nürnberg, 2008

[13] J. O. Krah, „Regelverfahren und Regelvorrichtung mit mehrkanaliger Rückführung“, Internationale Patent-

anmeldung EP2008/058948, DE102007032484A1

pcim 2011 current

Documents