peering into moore’s crystal ball:crystal...

Peering into Moore’s Crystal Ball:Crystal Ball:

Transistor Scaling beyondbeyond

the 15nm node

Kelin J. KuhnIntel Fellow

Director of Advanced Device TechnologygyPortland Technology Development

Intel Corporation

Kelin Kuhn / Int’l Symp. on Adv. Gate Stack Technology/ Sept. 29th, 2010 1

AGENDA• Scaling • Gate control• Mobility• Resistance• CapacitanceCapacitance• Summary


Consistent 2-year scaling

22nm WIDE

90nm – TALL

65nm – WIDE - 0.57 m245nm – WIDE

0.346 m2

32nm – WIDE 0.171 m2

22nm – WIDE0.092 m2

90nm TALL1.0 m2 90 nm

200390 nm2003

45 nm200745 nm2007

65 nm200565 nm2005

22 nm2011

projected

22 nm2011

projected

32 nm200932 nm2009

90: 765: 8

32: 945: 9


Changes in ScalingTHEN

• Scaling drove down costNOW

• Scaling drives down costScaling drove down cost• Scaling drove performance• Performance constrained

Scaling drives down cost• Materials drive performance• Power constrained

• Active power dominates• Independent design-process

• Standby power dominates• Collaborative design-process

Kelin Kuhn / Int’l Symp. on Adv. Gate Stack Technology/ Sept. 29th, 2010

130nm 90nm 65nm 45nm 32nm

3

Consistent SRAM Density Scaling

10.00

m2 )

rea

(m

1.00

tcel

l Ar

2X bitcell area

0.10

Bit 2X bitcell area

scaling

90nm 65nm 45nm 32nm

Process generation22nm


K. Zhang, ISCC, 2009; M. Bohr IDF 2010

g

4

AGENDA• Scaling

G l• Gate control• Mobility• Resistance• CapacitanceCapacitance• Summary


Short Channel Control: HiK-MG

45 nm High-k/MG enabled 0.7X T E li hil d iHK+MG ToxE scaling while reducing Ig >> 25X for NMOS and 1000X for PMOS

e 2 02 0

1000X for PMOS

0 1

1

10

100

te L

eaka

ge SiON/Poly 65nm

SiON/Poly 1.5

2.0

1.5

2.01.0 V, 100 nA IOFF

45nm32nm

65nm

mA

/um

)0 0001

0.001

0.01

0.1

mal

ized

Gat

HiK+MG 45nm

HiK+MG45nm

65nm

0.5

1.0

0.5

1.090nm

NMOS

130nme

curr

ent (

65nm: Bai 2004 IEDM

0.00001

0.0001

-1.2 -0.8 -0.4 0 0.4 0.8 1.2

VGS (V)

Nor

m NMOS PMOS

0.0

0.5

1001000 Gate Pitch (nm)

0.0

0.5

PMOSDriv

e


VGS (V) Gate Pitch (nm)

6

Ultra-thin bodyith RSD

Benefitswith RSD

Extension of l t h lplanar technology

(less disruptive to manufacturing)

Improved RDF (low doped

channel)

C tibl

channel)

Compatible with RSD

technology

Excellent channel

Potential for body bias


controly

7

ChallengesUltra-thin bodyith RSD

V i ti

with RSDCapacitance

(Increased fringe to Variation:(film thickness changes affect VT and DIBL)

(Increased fringe to contact/facet)

Rext: (Xj/Tsi

limitations)

VT and DIBL)

limitations)

Strain:(strain transfer from

Manufacturing:

(strain transfer from S/D into the channel) Performance:

(transport challenges with thin Tsi)


g(requires both thin Tsi and thin BOX)

with thin Tsi)

8

Ultra-thin bodyBarral – CEA-LETI / L2MP / SOITEC – IEDM 2007

Ch IBM VLSI 2009Cheng – IBM – VLSI 2009

Lg=25nmTsi=6nm


MuGFET Benefits

Nearly ideal sub-th h ld l

Double-gate relaxes Tsi requirementsFin Wsi > UTB Tsi

threshold slope (gates tied together)

(less scattering, improved VT shift)


channel)channel)

Excellent channel controlCan be on


controlCan be on bulk or SOI

10

MuGFET with RSD

Benefitswith RSD






channel)channel)

Compatible with RSD

technology

Excellent channel control


gy control

10A

MuGFET Benefits

Possibility for i d d t t


independent gate operation



channel)channel)



control

10B

MuGFET ChallengesVariation

(Mitigating RDF but acquiring Gate wraparound

(Endcap coverage)Capacitance Hsi/Wsi/epi) (Endcap coverage)Capacitance (fringe to contact/facet)(Plus, additional “dead

space” elements)

Small fin pitch

space elements)

Small fin pitch (2 generation scale?)

Fin/gate fidelity on 3’D(Patterning/etch)

Rext: (Xj/Wsi

Topology(Polish / etch challenges)

Fin Strain engr.(Effective strain

t f f fi


( jlimitations)

challenges)transfer from a fin into the channel)

11

Kawasaki – Toshiba / IBM – IEDM 2009 MuGFET

Sim

Jurczak – IMEC - SOI 2009


Nanowire Benefits


Nanowire further


Nanowire further relaxes Tsi / Wsi

requirementsImproved RDF

(low doped channel)channel)



control

13

BenefitsNanowire


Nanowire further


Nanowire further relaxes Tsi / Wsi

requirementsImproved RDF

(low doped channel)channel)

Compatible with RSD

technology



gy control

13A

Nanowire ChallengesGate conformality

Capacitance (fringe to contact/facet)

Gate conformality(dielectric and metal)

(Plus, additional “dead space” elements)

Integrated wire fabrication

Wire stability(bending/warping)

Variation(Mitigating RDF but

wire fabrication (Epitaxy? Other?)

(bending/warping)

acquiring a myriad of new sources)Mobility degradation

(scattering)

Fi / t fid lit 3’D

Rext:

Fin Strain engr.(Effective strain

transfer from wire

Fin/gate fidelity on 3’D(Patterning/etch)

Topology


(Xj/Wsi limitations)

into the channel)Topology

(Polish / etch challenges) 14

Nanowire FETsDupre – CEA-LETI – IEDM 2008

Bangsaruntip – IBM – IEDM 2009


Nanowire FETsHashemi/Hoyt – MIT IEDM 2008 EDL/ESSDRC 2009IEDM 2008 EDL/ESSDRC 2009

Moselund – Ecole Polytechnique, SwitzerlandIEDM 2007


Vertical Architectures

BenefitsArchitectures

Vertical orientation50% reduction in

“plan view” density

Vertical orientation may enable new circuit concepts

Reduced vertical i t t

Possibility for different N/P materials/orientations

interconnect capacitance


Vertical Architectures

ChallengesArchitectures

Rext: (Xj/Wsi

Thermal processing (Top layer may need to

Gate conformality(dielectric and metal)(Xj/Wsi

limitations)(Top layer may need to

be processed over existing bottom layer)

(dielectric and metal)

Fin/gate fidelity on 3’DContacts

(Diffusion-diffusion,Gate gate contactsTopology

Fin/gate fidelity on 3 D(Patterning/etch)

Gate-gate contacts extremely challenging)

Topology(Polish / etch challenges)

Lithography(May double the number

of FE critical layers) Capacitance (fringe to contact/facet)

Strain engineering(more challenging

Variation(Mitigating RDF but

(fringe to contact/facet)(Plus, additional “dead

space” elements)


(more challenging than single layer)

( g gacquiring a myriad

of new sources) 18

VerticalBatude – CEA LETI - IEDM 2009 – stacked 110/100

Jung – Samsung - IEEE TED 2010 – 3‘D stacked 6T


TFET (Tunneling Field-Effect Transistor)

Vd

VgPrinciple of operation• Band-to-band- tunneling through source

barrier, modulated by gate field

Gate

Source Drain

Vd

P+ i-InAs Nbarrier, modulated by gate field

Advantages• Steep (< 60 mV/dec) sub-threshold slope

L I /I ff ti• Large Ion/Ioff ratio

Disadvantages• Low drive currentsLow drive currents• Ambipolar conduction• Unidirectional conduction• Potentially high hot-e- effects

Technology Intercept• Unlikely candidate for Si, Ge, or Si1-xGex

systems (drive currents too low)Tunneling barrierssystems (drive currents too low)

• Probably needs III-V band-gap engineering, perhaps with “broken-gap”

Courtsey M. Luisier (Purdue) M. Luisier and G. Klimeck, EDL, 2009


M. Luisier and G. Klimeck, EDL, 2009

Sensitivity to Source Doping VariationTFET Source Doping Gradient

1E+20

1E+21

G

TFETTSi = 5nm, Lg = 20nm, Vds = 0.5V

1E-071E-061E-05

TFET behavior is very

1E+16

1E+17

1E+18

1E+19Grad 0Grad 1Grad 2

1E-131E-121E-111E-101E-091E-08

Ids

(A/u

m)

Grad0

TFET behavior is very sensitive to the source

doping “shape”

1E+14

1E+15

1E 16

-4 -2 0 2 4 6X (nm)

1E-171E-161E-151E-141E 13

0.0 0.2 0.4 0.6 0.8 1.0

Grad0Grad1Grad2

Vgs (V)

MOSTSi = 5nm, Lg = 20nm, Vds = 0.5V

1E-02MOS Source Doping Gradient

1E+21

1E-05

1E-04

1E-03

(A/u

m)

1E+19

1E+20 Grad0Grad1Grad2

MOS behavior has little sensitive to the source

doping “shape”

1E 09

1E-08

1E-07

1E-06

Ids

Grad0Grad1Grad21E+17

1E+18

-4 -2 0 2 4 6

p g p


1E-090.0 0.2 0.4 0.6 0.8 1.0

Vgs (V)

-4 -2 0 2 4 6X (nm)

21

Best Demonstrated TFETs• Still MUCH lower drive currents

than conventional MOSR i b d i i

1 .0 0 E -0 4

1 .0 0 E -0 3

1 .0 0 E -0 2

32nm MOS@ Vds = 0.8V

• Require band-gap engineering with hetero-junction layers

• Sub-threshold slope still poor1 .0 0 E -0 7

1 .0 0 E -0 6

1 .0 0 E -0 5

[1]

1 .0 0 E -0 8

0 0 .2 0 .4 0 .6 0 .8 1

S. Mookerjea et al., IEDM ‘09

[1] K. Jeon, et al., VLSI (11.4.1.-1) 2010 [2] W. Choi et al., IEEE-EDL vol.28, no.8, p.743 (2007)


[ ] , , , p ( )[3] F. Mayer et al., IEDM Tech Dig., p.163 (2008)[4] T. Krishnamohan et al., IEDM Tech Dig., p.947 (2008)

22

AGENDA• Scaling



Transistor Performance Trend1.5

1.0 V, 100 nA I OFF32nm

Strain

Drive1.0

45nm

65nm

Strain

Hi-k-MG

OtherDrive Current (mA/um) 0.5

65nm

90nm

130nm

“Classic” scaling

0.0

PMOS

St i i iti l i di t i d t i t li

1001000Gate Pitch (nm)

Strain is a critical ingredient in modern transistor scalingStrain was first introduced at 90nm, and its contribution has

increased in each subsequent generation


q g

24

Strain in modern d i

Stress memorization

devices

Wei, VLSI 2007

Ghani, IEDM 2003

Mayuzumi, IEDM 2007Mayuzumi, IEDM 2007

Auth VLSI 2008


Yang, IEDM 2008Auth, VLSI 2008

25

ORIENTATION(110) surface – top down(100) surface – top down

Non standard<110> <100>

Non-standard

(110) Surface<100> <111>

Standard wafer / direction(100) Surface / <110> channel

(100) Surface / <100>Three possible channel directions<110> <111> and <100>

<110>(100)<110>(110)

(100) Surface / 100 (a “45 degree” wafer)

Both <110> directions are the samesame.

<100><110>


ORIENTATION(110) surface – top down(100) surface – top down

Non standard<110> <100>

Non-standard

(110) Surface<100> <111>

Standard wafer / direction(100) Surface / <110> channel

(100) Surface / <100>Three possible channel directions<110> <111> and <100>

<110>(100)<110>(110)

(100) Surface / 100 (a “45 degree” wafer)

Both <110> directions are the samesame.

<100><110>(100) BEST NMOS (110) <110> BEST PMOS

YangAMD/IBM EDST 2007

Kelin Kuhn / Int’l Symp. on Adv. Gate Stack Technology/ Sept. 29th, 2010 26A

Orientation and Strain:More complex for non-(100) orientations

(001) Surface (k=0) (001) Surface Vg=-1V(001) Surface

Vg=-1V, Sxx=-1GPa(100)

More complex for non (100) orientations

<110>

(110) Surface (k=0) (110) Surface Vg=-1V(110) Surface

Vg=-1V, Sxx=-1GPa(110)

<110>


BULK 1’D CONFINED 1’D CONFINEDSTRAINED

Kuhn/Packan, Intel, IEDM 2008 27

Si vs Ge MOSFETs

Gate

Drainn-Ge

Gate

Drainn-GeSource

DrainSource

Drain

The introduction of manufacturable HiK-MG

Intel 45nm HiK-MG Si device [43] Intel HiK-MG Ge device

transistors has led to the reconsideration of Ge channels


Ge Historical Issues: Still critical today

(eV)

Still critical today

4

5

n A

ffini

ty

150

200

V/c

m

Si (no strain)Ge 100%Ge 55%SiGe 25%

2

3

d El

ectr

on

100

ITY

@1M

cm2/

V.s)

SiGe 25%

0

1

ndga

p an

d

0

50

MO

BIL (c

0Si Ge InP GaAs InSbB

an

010 15 20

TOXE (A)

Narrow Bandgap Poor Quality Dielectric


Narrow Bandgap

1.2

V)

100000

V.s)

BTBTSourceAdapted from Fischetti [7], Krishnamohan [60]

Adapted from Saraswat [59], Krishnamohan [60]

0.6

0.8

1

andg

ap (e

V

10000

ity (c

m^2

/V

Eg

||h

e

Krishnamohan [60]

1 E 05

1.E-04

1.E-03

m]0.2

0.4

0.6

Ener

gy B

a

1000

Hol

e m

obiliEg

Eg

Drain

DRAIN

1.E-07

1.E-06

1.E-05

Id, I

s [A

/um DRAIN

High Junction Leakage

00 20 40 60 80 100

SiGe (PERCENTAGE)

100

HSource

1.E-09

1.E-08

-1.5 -0.5 0.5 1.5Vg - Vt [V]

SourceS Ge ( C G )

Band-to-band tunneling: challenge for low Eg materials


Dielectric Quality

GeGe to

GeGe/GeGeOO22

GeGeOO22(110)

sub‐oxide oxide transition

GeGe(111)

Heynes, 2008 [9]

Since HiK-MG dielectrics typically form with a bilayer (the HiK + yp y y (an interface layer) the challenge of germanium oxide still exists.Germanium oxide exists in several morphologies, unfortunately,

most are hydroscopic and/or volatile


most are hydroscopic and/or volatile.

31

Ge Benchmarking

B t il

Irisawa2005

Romanjek2008

1.E-04

1.E-03Yamamoto

2007

Batail2009

Nicholas 2007

1.E-06

1.E-05

ff (A

/um

)

Wang

1.E-08

1.E-07IofWang

2007 Zimmerman2006

1.E-090 200 400 600 800 1000

Ion (mA/um)

Tezuka2006

A d i

Hellings2009

Andrieu2005

Harris2007

Mitard2009

Liao2008


2007

32

III-V: The Lure of High Mobility

nd

ty (

eV)

ctro

n2-

V.s)

4

5 1000000

ndga

pa

on A

ffini

and

Elec

ity (c

m2

2

3

4

1000

Ban

Elec

tro

Hol

e a

Mob

il

0

1

Si Ge InP GaAs InSb1

Ad t d f J K li I t l VLSI SC 2007


Adapted from J. Kavalieros – Intel - VLSI SC 2007K. Kuhn – ECS 2010

33

III-V MOSFETs:“D it f t t b ttl k”

From R. Kim

“Density-of-states bottleneck”

O t f MOSFET• On-current of a MOSFET

• Velocity υ

I Q

y– Diffusive : mobility μ, υ = μE– Ballistic: injection velocity υinj

– Light m* → high μ, high υinj

• Charge Q G hQ C V V g Q– MOS limit (CQ » Cox), C ≈ Cox

– Light m* → less D (CQ), less C, less QM i f hi id (l )

1 1 1

G th

Q

Q C V V

C C C

– More important for thin oxide (large Cox),

“DOS bottleneck”2

ox Q

Q

C C C

C q D


Use of L-valleys: GaAs From R. Kim

• GaAs 4 nmkyy

[001][011]

single band from Γ

Small DOS with high vinjHigh DOS with low vinj

8 L-valleys

kx[010]

Γ

(100)

ky[ 1 12]

( )

[-1-12][-211] Multiple bands from

Γ and LMore DOS with high vinj

kx[-110]

(111)


( )

35

Different body thicknesses (EOT=1.0 nm)

4 nm2 nm 8 nm

GaAs>InGaAs>GaSb>Ge>Si GaSb,InGaAs>Ge,GaAs>Si InGaAs>GaSb>Ge,GaAs>Si

Diff t b d thi k (EOT 0 5 )Different body thicknesses (EOT=0.5 nm)

42 84 nm2 nm 8 nm


GaSb>GaAs>Ge>Si>InGaAs GaSb>Ge>GaAs>Si,InGaAs GaSb>Ge>GaAs, InGaAs>Si

From R. Kim

AGENDA• Scaling



Planar Resistive Elements

RCONTACTRCONTACTRCONTACT

RSILICIDE

RCONTACT

RSILICIDE

RINTERFACERINTERFACE

RACCUMULATION

R

REPI RACCUMULATION

R

REPI

RSPREADINGRSPREADING


Planar Resistive ElementsRacc: Sub-melt Laser Anneal

1E+19

1E+20

1E+21

1E+22

trat

ion

(ato

ms/

cm3)

#0 - No Laser#4 - 91%, 60us#5 - 88%, 60us#6 - 85%, 60us#7 - 54%, 200us

q

RCONTACTRCONTACT

1E+17

1E+18

0 10 20 30 40 50 60

Depth (nm)

Con

cent

Phosphorus

Depth (nm)

Kuhn IWJT 20010RCONTACT

RSILICIDE

RCONTACT

RSILICIDE

Kuhn, IWJT 20010

RINTERFACERINTERFACE1E+20

1E+21

(cm

-3)

Racc: Solid-phase Epi Regrowth

RACCUMULATION

R

REPI RACCUMULATION

R

REPI

1E+17

1E+18

1E+19

Con

cent

ratio

n

B in Si

RSPREADINGRSPREADINGKuhn, IWJT 20010

0 40 80 120Depth (nm)

Kelin Kuhn / Int’l Symp. on Adv. Gate Stack Technology/ Sept. 29th, 2010 38A

Planar Resistive ElementsRacc: Sub-melt Laser AnnealRinterface: Reduction inS h ttk B i H i ht

B

NqR expinterface

1E+19

1E+20

1E+21

1E+22

trat

ion

(ato

ms/

cm3)

#0 - No Laser#4 - 91%, 60us#5 - 88%, 60us#6 - 85%, 60us#7 - 54%, 200us

q

1.1

1.3Schottky theoryExperiment

4th period transition 6th period transition 5th period transition metals

Pt78;6

Ir

Schottky Barrier Height

DNinterface

RCONTACTRCONTACT

1E+17

1E+18

0 10 20 30 40 50 60

Depth (nm)

Con

cent

Phosphorus

Depth (nm)

Kuhn IWJT 20010i(e.

v.)

0.7

0.9

metals metalsmetals

Ti22;4

V23;4

Cr

Nb41;5

Ni28;4

Co27;4Fe

26;4Mn25;4

Ir77;6

Os76;4

Re75;6

W74;6

Ta

Pd46;5

Rh45;5Ru

44;5Mo42;5

Desired for PMOS

RCONTACT

RSILICIDE

RCONTACT

RSILICIDE

Kuhn, IWJT 20010

nS

Si Mid-Gap

0.3

0.5Lanthanides

Cr24;4 Zr

40;5

Y39;5

73;6Hf72;6

Er68;6

Dy66;6

Gd64;6

Yb70;6

RINTERFACERINTERFACE1E+20

1E+21

(cm

-3)

Racc: Solid-phase Epi Regrowth

0.1

0.1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Desired for NMOS

RACCUMULATION

R

REPI RACCUMULATION

R

REPI

1E+17

1E+18

1E+19

Con

cent

ratio

n

B in Si

Schottky Barrier Height Reduction is a critical area for development. Techniques under investigation include

exotic alloys, implants, and Fermi-unpinning layersRSPREADINGRSPREADING

Kuhn, IWJT 20010

0 40 80 120Depth (nm)

y , p , p g y

Kelin Kuhn / Int’l Symp. on Adv. Gate Stack Technology/ Sept. 29th, 2010 38B

Planar Resistive Elements

Rcontact: Decreased Resistance of the Contact Metal

RCONTACTRCONTACT Kuhn IWJT 20010

of the Contact Metal

RCONTACT

RSILICIDE

RCONTACT

RSILICIDE

Kuhn, IWJT 20010

RINTERFACERINTERFACE

RACCUMULATION

R

REPI RACCUMULATION

R

REPI Topol, VLSI 2006Copper Contacts

RSPREADINGRSPREADINGKuhn, IWJT 20010

Kelin Kuhn / Int’l Symp. on Adv. Gate Stack Technology/ Sept. 29th, 2010 38C

Schottky barrier S/D – an option? Electron leakage set by Eg-SBH • In a metal SB MOS S/D• In a metal SB-MOS, S/D

forms an atomically abrupt Schottky-barrier having the height bheight b.

• The extreme limit for metal in the S/D regions (with

i t d i t iassociated improvements in Rext)

• Unconventional operation

Metallic SD Conventional

p(field emission device in the ON state)

• Needs complementaryLarson – Spinnaker

TED 2006Hole barrier set by SBH

Needs complementary devices (midgap silicide or two silicides)


y

39

Schottky barrier S/D – an option? Zh IEEE TED M 2009

• In a metal SB MOS S/D

Electron leakage set by Eg-SBH

Zhu IEEE TED May 2009

• In a metal SB-MOS, S/D forms an atomically abrupt Schottky-barrier having the height bheight b.

• The extreme limit for metal in the S/D regions (with

i t d i t i Two possible conduction paths:

Thermionic over the barrier good SS slopeassociated improvements in Rext)

• Unconventional operation

Thermionic – over the barrier – good SS slope Tunneling – through the barrier – poor SS slope

p(field emission device in the ON state)

• Needs complementaryMetallic SD Conventional

Needs complementary devices (midgap silicide or two silicides)

Larson – SpinnakerTED 2006Hole barrier

set by SBH


y

39A

Schottky barrier S/D – an option? Electron leakage set by Eg-SBH

Benefits

• Low bulk resistance contacts to the channelLow bulk resistance contacts to the channel• Very abrupt junctions • No random s/d dopant fluctuation effects• Minimize s/d carrier-carrier scattering effects

Challenges

g

• Poor experimental drive currents• Requires bandedge Schottky barriers • Ambipolar conduction

Metallic SD Conventional

Ambipolar conduction (high drain-body leakage for bulk devices)

• Early contact formation limits midsection process temperatures

Larson – SpinnakerTED 2006Hole barrier

set by SBH

p p• Need alternative approach for s/d stressors


y

39B

AGENDA• Scaling



Planar Capacitive Elements

Cfringe to Contact

CjunctionCfringe to

facet

Cfringe to diffusion (of/if)

Gated-edge junction Cxud - device

component of Cov

( )

Cchannel component

(XUD-based)


Area junction of Cgate

Kuhn, Intel, IEDM SC 2008 41

Planar Capacitive Elements

Cfringe to Contact

CjunctionCfringe to

facet SiBCN (Low-K) SPACERKo –TSMC

Cfringe to diffusion (of/if)

VLSI 2008

Gated-edge junction Cxud - device

component of Cov

( )

Cchannel component

(XUD-based)


Area junction of Cgate

Kuhn, Intel, IEDM SC 2008 41A

SPACER REMOVALLiow – NUS Singapore

EDL 2008

AGENDA• Scaling



Looking ForwardLooking ForwardLow risk

E h t i t i t h lEnhancements in strain technologyEnhancements in HiK/MG technology

Medium RiskOptimized substrate and channel orientation

Reduction in MOS parasitic resistanceReduction in MOS parasitic resistanceReduction in MOS parasitic capacitance

High riskUTB devices / MuGFETS

NanowiresNanowires3’D Stacked Devices

Advanced materials (Ge/III-V)


Q&AQ&A


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