pentek analog & digital i/o catalog

Analog & Digital I/O

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MODEL DESCRIPTION

Cobalt 71630 1 GHz A/D and D/A, Virtex-6 FPGA - XMCCobalt 78630 1 GHz A/D and D/A, Virtex-6 FPGA - x8 PCIeCobalt 53630 1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX - Format 1Cobalt 52630 1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX - Format 2Cobalt 57630 & 58630 1-/2-Ch 1 GHz A/D and 1-/2-Ch 1 GHz D/A, Virtex-6 FPGA - 6U VPXCobalt 72630, 73630, 74630 1-/2-Ch 1 GHz A/D and 1-/2-Ch 1 GHz D/A, Virtex-6 FPGA - 6U/3U cPCICobalt 56630 1 GHz A/D and D/A, Virtex-6 FPGA - AMCCobalt 71640 1-Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - XMCCobalt 78640 1-Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - x8 PCIeCobalt 53640 1-Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 3U VPX - Format 1Cobalt 52640 1-Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 3U VPX - Format 2Cobalt 57640 & 58640 1-/2-Ch 3.6 GHz or 2-/4-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 6U VPXCobalt 72640, 73640, 74640 1-/2-Ch 3.6 GHz or 2-/4-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 6U/3U cPCICobalt 56640 1-Ch 3.6 GHz or 2-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - AMCCobalt 71660 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - XMCCobalt 78660 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - x8 PCIeCobalt 53660 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 3U VPX - Format 1Cobalt 52660 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 3U VPX - Format 2Cobalt 57660 & 58660 4-/8-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 6U VPXCobalt 72660, 73660, 74660 4-/8-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 6U/3U cPCICobalt 56660 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - AMCCobalt 71663 1100 GSM Channelizer with Quad A/D - XMCCobalt 78663 1100 GSM Channelizer with Quad A/D - x8 PCIeCobalt 53663 1100 GSM Channelizer with Quad A/D - 3U VPX - Format 1Cobalt 52663 1100 GSM Channelizer with Quad A/D - 3U VPX - Format 2Cobalt 57663 & 58663 1100/2200 GSM Channelizer with Quad/Octal A/D - 6U VPXCobalt 72663, 73663, 74663 1100/2200 GSM Channelizer with Quad/Octal A/D - 6U/3U cPCICobalt 56663 1100 GSM Channelizer with Quad A/D - AMCCobalt 71670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - XMCCobalt 78670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - x8 PCIeCobalt 53670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U VPX - Format 1Cobalt 52670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U VPX - Format 2Cobalt 57670 & 58670 4-/8-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 6U VPXCobalt 72670, 73670, 74670 4-/8-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 6U/3U cPCICobalt 56670 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - AMCCobalt 71690 L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - XMCCobalt 78690 L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - x8 PCIeCobalt 53690 L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - 3U VPX - Format 1Cobalt 52690 L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - 3U VPX - Format 2

ANALOG & DIGITANALOG & DIGITANALOG & DIGITANALOG & DIGITANALOG & DIGITAL I/OAL I/OAL I/OAL I/OAL I/O

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MODEL DESCRIPTION


Cobalt 57690 & 58690 1-/2-Ch L-Band RF Tuner, 2-/4-Ch 200 MHz A/D, Virtex-6 FPGA - 6U VPXCobalt 72690, 73690, 74690 1-/2-Ch L-Band RF Tuner, 2-/4-Ch 200 MHz A/D, Virtex-6 FPGA - 6U/3U cPCICobalt 56690 L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - AMCOnyx 71760 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - XMCOnyx 78760 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - x8 PCIeOnyx 53760 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 3U VPX - Format 1Onyx 52760 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 3U VPX - Format 2Onyx 57760 & 58760 4-/8-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 6U VPXOnyx 72760, 73760, 74760 4-/8-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 6U/3U cPCIOnyx 56760Onyx 56760 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - AMCOnyx 71730 1 GHz A/D and D/A, Virtex-7 FPGA - XMCOnyx 78730 1 GHz A/D and D/A, Virtex-7 FPGA - x8 PCIeOnyx 53730 1 GHz A/D and D/A, Virtex-7 FPGA - 3U VPX - Format 1Onyx 52730 1 GHz A/D and D/A, Virtex-7 FPGA - 3U VPX - Format 2Onyx 57730 & 58730 1-/2-Ch 1 GHz A/D and 1-/2-Ch 1 GHz D/A, Virtex-7 FPGAs - 6U VPXOnyx 72730, 73730, 74730 1-/2-Ch 1 GHz A/D and 1-/2-Ch 1 GHz D/A, Virtex-7 FPGAs - 6U/3U cPCIOnyx 56730 1 GHz A/D and D/A, Virtex-7 FPGA - AMCOnyx 71741 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit A/D, DDC,Virtex-7 FPGA - XMCOnyx 78741 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit A/D, DDC,Virtex-7 FPGA - x8 PCIeOnyx 53741 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, DDC,Virtex-7 FPGA - 3U VPX - Format 1Onyx 52741 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, DDC,Virtex-7 FPGA - 3U VPX - Format 2Onyx 57741 & 58741 1/2-Ch. 3.6 GHz or 2/4-Ch. 1.8 GHz, 12-bit A/D, DDC,Virtex-7 FPGA - 6U VPXOnyx 72741, 73741, 74741 1/2-Ch. 3.6 GHz or 2/4-Ch. 1.8 GHz, 12-bit A/D, DDC,Virtex-7 FPGA - 6U/3U cPCIOnyx 56741 1-Channel 3.6 GHz or 2-Channel 1.8 GHz, 12-bit A/D, DDC,Virtex-7 FPGA - AMCCobalt 71610 LVDS Digital I/O with Virtex-6 FPGA - XMCCobalt 78610 LVDS Digital I/O with Virtex-6 FPGA - x8 PCIeCobalt 53610 LVDS Digital I/O with Virtex-6 FPGA - 3U VPX - Format 1Cobalt 52610 LVDS Digital I/O with Virtex-6 FPGA - 3U VPX - Format 2Cobalt 57610 & 58610 Single or Dual LVDS Digital I/O with Virtex-6 FPGAs - 6U VPXCobalt 72610, 73610, 74610 Single or Dual LVDS Digital I/O with Virtex-6 FPGAs - 6U/3U cPCICobalt 56610 LVDS Digital I/O with Virtex-6 FPGA - AMCCobalt 7811 Quad Serial FPDP Interface with Virtex-6 FPGA - x8 PCIeCobalt 71611 Quad Serial FPDP Interface with Virtex-6 FPGA - XMCCobalt 78611 Quad Serial FPDP Interface with Virtex-6 FPGA - x8 PCIeCobalt 53611 Quad Serial FPDP Interface with Virtex-6 FPGA - 3U VPX - Format 1Cobalt 52611 Quad Serial FPDP Interface with Virtex-6 FPGA - 3U VPX - Format 2Cobalt 57611 & 58611 Quad or Octal Serial FPDP Interface with Virtex-6 FPGAs - 6U VPXCobalt 72611, 73611, 74611 Quad or Octal Serial FPDP Interface with Virtex-6 FPGAs - 6U/3U cPCICobalt 56611 Quad Serial FPDP Interface with Virtex-6 FPGA - AMC

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Last updated: December 2017

MODEL DESCRIPTION

Jade 71141 1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch. 6.4 GHz D/A, Kintex FPGA - XMCJade 78141 1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch. 6.4 GHz D/A, Kintex FPGA - x8 PCIeJade 53141 1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch. 6.4 GHz D/A, Kintex FPGA - 3U VPXJade 52141 1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch. 6.4 GHz D/A, Kintex FPGA - 3U VPXJade 57141 & 58141 1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch. 6.4 GHz D/A, Kintex FPGA - 6U VPXJade 72141, 73141, 74141 1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch. 6.4 GHz D/A, Kintex FPGA - 6U/3U cPCIJade 56141 1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch. 6.4 GHz D/A, Kintex FPGA - AMCFlexor 5973 Virtex-7 Processor and FMC Carrier - 3U VPXFlexor 7070 Virtex-7 Processor and FMC Carrier - x8 PCIeFlexor 3312 4-Channel 250 MHz, 16-bit A/D, 2-Channel 800 MHz, 16-bit D/A - FMCFlexorSet 5973-312 4-Channel 250 MHz 16-bit A/D, 2-Channel800 MHz 16-bit D/A - 3U VPXFlexorSet 7070-312 4-Channel 250 MHz 16-bit A/D, 2-Channel800 MHz 16-bit D/A - x8 PCIeFlexor 3316 8-Channel 250 MHz, 16-bit A/D - FMCFlexorSet 5973-316 8-Channel 250 MHz 16-bit A/D with Virtex-7 FPGA - 3U VPXFlexorSet 7070-316 8-Channel 250 MHz 16-bit A/D with Virtex-7 FPGA - x8 PCIeFlexor 3320 2-Channel 3.0 GHz A/D, 2-Channel 2.8 GHz D/A wth Virtex-7 - FMCFlexorSet 5973-320 2-Channel 3.0 GHz A/D, 2-Channel 2.8 GHz D/A wth Virtex-7 - 3U VPXFlexorSet 7070-320 2-Channel 3.0 GHz A/D, 2-Channel 2.8 GHz D/A wth Virtex-7 - x8 PCIeFlexor 3324 4-Channel 500 MHz, 16-bit A/D, 4-Channel 1.5 GHz, 16-bit D/A - FMCFlexorSet 5973-324 4-Channel 500 MHz, 16-bit A/D, 4-Channel 1.5 GHz, 16-bit D/A - 3U VPXFlexorSet 7070-324 4-Channel 500 MHz, 16-bit A/D, 4-Channel 1.5 GHz, 16-bit D/A - x8 PCIeBandit 7120 Two-Channel Analog RF Wideband Downconverter - PMC/XMCBandit 7820 Two-Channel Analog RF Wideband Downconverter - PCIeBandit 5220 Two-Channel Analog RF Wideband Downconverter - 3U VPXBandit 5720 & 5820 Two- or Four-Channel Analog RF Wideband Downconverter - 6U OpenVPXBandit 7220, 7320, 7420 Two- or Four-Channel Analog RF Wideband Downconverter - 6U/3U cPCIBandit 5620 Two-Channel Analog RF Wideband Downconverter - AMCBandit 8111 Modular Analog RF Slot Downconverter Series8264 6U OpenVPX Development System for Cobalt and Onyx Boards8266 PC Development System for PCIe Cobalt and Onyx Boards8267 3U VPX Development System for Cobalt, Onyx and Flexor Boards

Customer Information


www.pentek.comOne Park Way ◆ Upper Saddle River ◆ New Jersey 07458Tel: 201.818.5900 ◆ Fax: 201.818.5904 ◆ Email: [email protected]

Pentek, Inc.

1 GHz A/D and 1 GHz D/A, Virtex-6 FPGA - XMCModel 71630

General InformationModel 71630 is a member of the Cobalt®

family of high performance XMC modulesbased on the Xilinx Virtex-6 FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communica-tions or radar system. Its built-in data captureand playback features offer an ideal turnkeysolution as well as a platform for developingand deploying custom FPGA processing IP.

It includes 1 GHz A/D and D/A convert-ers and four banks of memory. In additionto supporting PCI Express Gen. 2 as a nativeinterface, the Model 71630 includes optionalgeneral purpose and gigabit serial cardconnectors for application-specific I/O.

The Cobalt ArchitectureThe Pentek Cobalt architecture features

a Virtex-6 FPGA. All of the board’s data andcontrol paths are accessible by the FPGA,enabling factory installed functions includ-ing data multiplexing, channel selection,data packing, gating, triggering and memorycontrol. The Cobalt architecture organizesthe FPGA as a container for data processingapplications where each function exists asan intellectual property (IP) module.

Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 71630 factory-installed functionsinclude an A/D acquisition and a D/A wave-form playback IP module. In addition, IPmodules for either DDR3 or QDRII+ memo-ries, a controller for all data clocking and

synchronization functions, a test signalgenerator and a PCIe interface completethe factory-installed functions and enablethe 71630 to operate as a complete turnkeysolution, without the need to develop anyFPGA IP.

Extendable IP DesignFor applications that require specialized

functions, users can install their own customIP for data processing. Pentek GateFlowFPGA Design Kits include all of the factoryinstalled modules as documented source code.Developers can integrate their own IP withthe Pentek factory-installed functions or usethe GateFlow Design Kit to completely replacethe Pentek IP with their own.

Xilinx Virtex-6 FPGAThe Virtex-6 FPGA site can be populated

with a variety of different FPGAs to matchthe specific requirements of the processingtask. Supported FPGAs include: LX130T,LX240T, or SX315T. The SXT part features1344 DSP48E slices and is ideal for modula-tion/demodulation, encoding/decoding,encryption/decryption, and channel-ization of the signals between transmissionand reception. For applications not requiringlarge DSP resources, one of the lower-costLXT FPGAs can be installed.

Option -104 installs the P14 PMC connec-tor with 20 pairs of LVDS connections tothe FPGA for custom I/O.

Option -105 installs the P16 XMC connec-tor with one 8X or two 4X gigabit links tothe FPGA to support serial protocols. ➤

Features■ Complete radar and software

radio interface solution■ Supports Xilinx Virtex-6

LXT and SXT FPGAs■ One 1 GHz 12-bit A/D

■ One 1 GHz 16-bit D/A■ Up to 2 GB of DDR3 SDRAM

or 16 MB of QDRII+ SRAM■ Sample clock synchronization to

an external system reference■ Dual-µSync clock/sync bus

for multimodule synchronization■ PCI Express (Gen. 1 & 2)

interface up to x8■ Optional user-configurable

gigabit serial interface■ Optional LVDS connections

to the Virtex-6 FPGA forcustom I/O

TIMING BUSGENERATOR

Clock / Sync /Gate / PPS D/A Clock/Sync Bus

VCXO

16

QDRII+SRAM8 MB

Gate InSync In

A/D Sync Bus

Sample Clk /Reference Clk In

A/D Clock/Sync Bus

16

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

RF Out

RFXFORMR

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16 1616 16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

1 GHz12-BIT A/D

12

Memory Banks 1 & 2 Memory Banks 3 & 4DDR3 option 155 DDR3 option 165

Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

40

GigabitSerial I/O

(option 105)

4X4X

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

GTXGTX LVDSGTX

VIRTEX-6 FPGA

LX130T, LX240T or SX315T


Pentek, Inc.


➤➤➤➤➤ A/D Converter StageThe front end accepts an analog HF or

IF input on a front panel SSMC connectorwith transformer coupling into a TexasInstruments ADS5400 1 GHz, 12-bit A/Dconverter.

The digital outputs are delivered intothe Virtex-6 FPGA for signal processing,data capture or for routing to other moduleresources.

D/A Converter StageThe 71630 features a TI DAC5681Z 1 GHz,

16-bit D/A. The converter has an inputsample rate of 1 GSPS, allowing it to aceptfull rate data from the FPGA. Additionally,the D/A includes a 2x or 4x interpolationfilter for applications that provide 1/2 or 1/4rate input data. Analog output is through afront panel SSMC connector.

Clocking and SynchronizationTwo internal timing buses provide either

a single clock or two different clock rates tothe A/D and D/A signal paths.

Each timing bus includes a clock, syncand a gate or trigger signal. An on-boardclock generator receives a sample clock eitherfrom the front panel SSMC connector orfrom an on-board programmable VCXO(Voltage-Controlled Crystal Oscillator). Inthis latter mode, the front panel SSMC con-nector can be used to provide a 10 MHzreference clock to phase-lock the VCXO.

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A

GigabitSerial I/OPCIe

FPGAGPIO

(supports user installed IP)

D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4

VIRTEX-6 FPGA DATAFLOW DETAILVIRTEX-6 FPGA DATAFLOW DETAIL

A/D

ACQUISITION

IP MODULE

LINKED-LISTDMA ENGINE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

8X 4X 4X 40

Either clock source (front panel or VCXO)can be used directly or can be dividedindependently by 2, 4, 8, or 16 to providedifferent lower frequency A/D and D/Aclocks.

A pair of front panel µSync connectorsallows multiple modules to be synchronized.They accept CML inputs that drive theboard’s sync and gate/trigger signals.

The Pentek Model 7192 and Model 9192Cobalt Synchronizers can drive multiple71630 µSync connectors enabling large,multichannel synchronous configurations.Also, an LVTTL external gate/trigger inputis accepted on a front panel SSMC connector.

Memory ResourcesThe 71630 architecture supports up to

four independent memory banks whichcan be configured with all QDRII+ SRAM,DDR3 SDRAM, or as combination of twobanks of each type of memory. Each QDRII+SRAM bank can be up to 8 MB deep and isan integral part of the module’s DMA capa-bilities, providing FIFO memory space forcreating DMA packets. For applicationsrequiring deep memory resources, DDR3SDRAM banks can each be up to 512 MBdeep. Built-in memory functions include anA/D data transient capture mode and D/Awaveform playback mode.

In addition to the factory-installedfunctions, custom user-installed IP withinthe FPGA can take advantage of the memo-ries for many other purposes. ➤

A/D Acquisition IP ModuleThe 71630 features an A/D

Acquisition IP Module for easycapture and data moving. The IPmodule can receive data fromthe A/D, a test signal generator,or from the D/A Waveform Play-back IP Module in loopbackmode. The IP module has associ-ated memory banks for bufferingdata in FIFO mode or for storingdata in transient capture mode.The memory banks are supportedwith a DMA engine for movingA/D data through the PCIeinterface.

This powerful linked-list DMAengine is capable of a uniqueAcquisition Gate Driven mode.In this mode, the length of atransfer performed by a linkdefinition need not be knownprior to data acquisition; rather,it is governed by the length ofthe acquisition gate. This isextremely useful in applicationswhere an external gate drivesacquisition and the exact lengthof that gate is not known or islikely to vary.

For each transfer, the DMAengine can automatically constructmetadata packets containing asample-accurate time stamp, anddata length information. Theseactions simplify the hostprocessor’s job of identifyingand executing on the data.

D/A Waveform PlaybackIP Module

The Model 71630 factory-installed functions include asophisticated D/A WaveformPlayback IP module. A linked-list controller allows users toeasily play back waveformsstored in either on-boardmemory or off- board hostmemory to the D/A.

Parameters including length ofwaveform, delay from playbacktrigger, waveform repetition,etc. can be programmed for eachwaveform.

Up to 64 individual linkentries can be chained together tocreate complex waveforms witha minimum of programming.


Pentek, Inc.


Ordering InformationModel Description

71630 1 GHz A/D and D/A,Virtex-6 FPGA - XMC

Options:

-002* -2 FPGA speed grade

-062 XC6VLX240T FPGA

-064 XC6VSX315T FPGA

-104 LVDS FPGA I/O throughP14 connector

-105 Gigabit serial FPGA I/Othrough P16 connector

-150 Two 8 MB QDRII+ SRAMMemory Banks(Banks 1 and 2)

-155 Two 512 MB DDR3SDRAM Memory Banks(Banks 1 and 2)


* This option is always required

Contact Pentek for availabilityof rugged and conduction-cooled

versions

Model Description

8266 PC Development SystemSee 8266 Datasheet forOptions

➤➤➤➤➤ XMC InterfaceThe Model 71630 complies with the

VITA 42.0 XMC specification. Two connectorseach provide dual 4X links or a single 8Xlink with up to a 6 GHz bit clock. Withdual XMC connectors, the 71630 supportsx8 PCIe on the first XMC connector leavingthe second connector free to support user-installed transfer protocols specific to thetarget application.

PCI Express InterfaceThe Model 71630 includes an industry-

standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the module.

SpecificationsFront Panel Analog Signal Inputs

Input Type: Transformer-coupled, frontpanel female SSMC connectors

A/D ConverterType: Texas Instruments ADS5400Sampling Rate: 100 MHz to 1 GHzResolution: 12 bits

D/A ConverterType: Texas Instruments DAC5681ZInput Data Rate: 1 GHz max.Interpolation Filter: bypass, 2x or 4xOutput Sampling Rate: 1 GHz max.Resolution: 16 bits

Front Panel Analog Signal OutputsOutput Type: Transformer-coupled,front panel female SSMC connectors

Sample Clock Sources: On-board clocksynthesizer generates two clocks: oneA/D clock and one D/A clock

Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO or front panel ex-ternal clockVCXO Frequency Ranges: 10 to 945MHz, 970 to 1134 MHz, and 1213 to1417 MHzSynchronization: VCXO can be phase-locked to an external 4 to 200 MHz systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16, inde-pendently for the A/D clock and D/Aclock

External ClockType: Front panel female SSMC connector,sine wave, 0 to +10 dBm, AC-coupled,50 ohms, accepts 100 MHz to 1 GHzdivider input clock, or PLL systemreference

Timing Bus: 19-pin µSync bus connectorincludes sync and gate/trigger inputs,CML

External Trigger InputType: Front panel female SSMC connector,LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Field Programmable Gate ArrayStandard: Xilinx Virtex-6 XC6VLX130T-2Optional: Xilinx Virtex-6 XC6VLX240T-2or XC6VSX315T-2

Custom I/OOption -104: Installs the PMC P14 con-nector with 20 LVDS pairs to the FPGAOption -105: Installs the XMC P16 con-nector configurable as one 8X or two 4Xgigabit serial links to the FPGA

MemoryOption 150: Two 8 MB QDRII+ SRAMmemory banks, 400 MHz DDROption 155 or 165: Two 512 MB DDR3SDRAM memory banks, 400 MHz DDR

PCI-Express InterfacePCI Express Bus: Gen.1: x4 or x8;Gen 2: x4

EnvironmentalOperating Temp: 0° to 50° CStorage Temp: –20° to 90° CRelative Humidity: 0 to 95%, non-cond.

Size: Standard XMC module, 2.91 in. x 5.87 in.

Model 8266The Model 8266 is a fully-

integrated PC developmentsystem for Pentek Cobalt andOnyx PCI Express boards (Mod-els 78xxx). It was created to saveengineers and system integratorsthe time and expense associatedwith building and testing a devel-opment system that ensuresoptimum performance ofPentek boards.


Pentek, Inc.

1 GHz A/D and 1 GHz D/A with Virtex-6 FPGA - x8 PCIeModel 78630


family of high performance PCIe boardsbased on the Xilinx Virtex-6 FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communica-tions or radar system. Its built-in data captureand playback features offer an ideal turnkeysolution as well as a platform for developingand deploying custom FPGA processing IP.

It includes 1 GHz A/D and 1 GHz D/Aconverters and four banks of memory. In addi-tion to supporting PCI Express Gen. 2 as anative interface, the Model 78630 includesoptional general-purpose and gigabit serial cardconnectors for application specific I/Oprotocols.



Each member of the Cobalt family isdelivered with factory installed applicationsideally matched to the board’s analog inter-faces. The 78630 factory-installed functionsinclude an A/D acquisition and a D/A wave-form playback IP module. In addition, IPmodules for either DDR3 or QDRII+memories, a controller for all data clockingand synchronization functions, a test signal

generator and a PCIe interface completethe factory-installed functions and enablethe 78630 to operate as a complete turnkeysolution, without the need to develop anyFPGA IP.





Option -104 connects 20 pairs of LVDSsignals from the FPGA on PMC P14 to a68-pin DIL ribbon-cable header on the PCIeboard for custom I/O.

Option -105 connects two 4X gigabitserial links from the FPGA on XMC P16 totwo 4X gigabit serial connectors along thetop edge of the PCIe board. ➤











TIMING BUSGENERATOR


VCXO

16

QDRII+SRAM8 MB

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

RF Out

RFXFORMR

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16 1616 16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

1 GHz12-BIT A/D

12


Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

40 4X

GTX

4X

GTXLVDS GTX

OptionalFPGAGPIO

OptionalSerialI/O

8X

68-pinHeader

x8 PCI Express

Dual 4XSerialConn

x8 PCIe

VIRTEX-6 FPGA



Pentek, Inc.




The digital outputs are delivered intothe Virtex-6 FPGA for signal processing,data capture or for routing to other boardresources.

D/A Converter StageThe 78630 features a TI DAC5681Z 1

GHz, 16-bit D/A. The converter has an in-put sample rate of 1 GSPS, allowing it toacept full rate data from the FPGA. Addi-tionally, the D/A includes a 2x or 4xinterpolation filter for applications that pro-vide 1/2 or 1/4 rate input data. Analogoutput is through a front panel SSMC con-nector.




PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A


FPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

8X 4X 4X 40


A pair of front panel µSync connectorsallows multiple boards to be synchronized.They accept CML inputs that drive theboard’s sync and gate/trigger signals.



four independent memory banks whichcan be configured with all QDRII+ SRAM,DDR3 SDRAM, or as combination of twobanks of each type of memory. Each QDRII+SRAM bank can be up to 8 MB deep and isan integral part of the board’s DMA capa-bilities, providing FIFO memory space forcreating DMA packets. For applicationsrequiring deep memory resources, DDR3SDRAM banks can each be up to 512 MBdeep. Built-in memory functions include anA/D data transient capture mode and D/Awaveform playback mode.

In addition to the factory installed func-tions, custom user-installed IP within theFPGA can take advantage of the memoriesfor many other purposes. ➤










Pentek, Inc.



78630 1 GHz A/D and D/A,Virtex-6 FPGA - x8 PCIe

Options:


-062 XC6VLX240T

-064 XC6VSX315T

-104 LVDS FPGA I/O through68-pin ribbon cableconnector

-105 Gigabit serial FPGA I/Othrough two 4X top edgeconnectors

-150 Two 8 MB QDRII+SRAM Memory Banks(Banks 1 and 2)




Model Description


➤➤➤➤➤ PCI Express InterfaceThe Model 78630 includes an industry-

standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the board.











Field Programmable Gate ArrayStandard: Xilinx Virtex-6 XC6VLX130T-2Optional: Xilinx Virtex-6 XC6VLX240T-2,or XC6VSX315T-2

Custom I/OOption -104: Connects 20 pairs of LVDSsignals from the FPGA on PMC P14 toa 68-pin DIL ribbon-cable header on thePCIe board for custom I/O.Option -105: Connects two 4X gigabitserial links from the FPGA on XMC P16to two 4X gigabit serial connectorsalong the top edge of the PCIe board


PCI-Express InterfacePCI Express Bus: Gen.1: x4 or x8Gen. 2: x4


Size: Half length PCIe card, 4.38 in. x 7.13 in.


integrated PC developmentsystem for Pentek Cobalt andOnyx PCI Express boards. It wascreated to save engineers andsystem integrators the time andexpense associated with buildingand testing a development systemthat ensures optimum perfor-mance of Pentek boards.


Pentek, Inc.

1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPXModel 53630


family of high performance 3U VPX boardsbased on the Xilinx Virtex-6 FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communica-tions or radar system. Its built-in data captureand playback features offer an ideal turnkeysolution.

It includes 1 GHz A/D and D/A convert-ers and four banks of memory. It featuresbuilt-in support for PCI Express over the3U VPX backplane.


a Virtex-6 FPGA. All of the board’s data andcontrol paths are accessible by the FPGA,enabling factory-installed functions includ-ing data multiplexing, channel selection,data packing, gating, triggering and memorycontrol. The Cobalt architecture organizesthe FPGA as a container for data processingapplications where each function exists asan intellectual property (IP) module.

Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 53630 factory-installed functionsinclude an A/D acquisition and a D/A wave-form playback IP module. In addition, IPmodules for either DDR3 or QDRII+memories, a controller for all data clockingand synchronization functions, a test signalgenerator and a PCIe interface complete the

factory-installed functions and enable the53630 to operate as a complete turnkey solu-tion, without the need to develop any FPGA IP.





Option -104 provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/O.

Option -105 provides one 8X or two 4Xgigabit links between the FPGA and the VPXP1 connector to support serial protocols. ➤

TIMING BUSGENERATOR


VCXO

16

QDRII+SRAM8 MB

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

RF Out

RFXFORMR

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16 1616 16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

1 GHz12-BIT A/D

12


Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTX

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

Option -105

4X8X 4X

x8PCIe

VIRTEX-6 FPGA




LXT and SXT FPGAs■ Supports gigabit serial fabrics

including PCI Express, SerialRapidIO and Xilinx Aurora

■ One 1 GHz 12-bit A/D■ One 1 GHz 16-bit D/A■ Up to 2 GB of DDR3 SDRAM



for multiboard synchronization■ Optional LVDS connections


■ 3U VPX form factor providesa compact, rugged platform

■ Compatible with several VITAstandards including:VITA-46, VITA-48 andVITA-65 (OpenVPXTM

System Specification)■ Ruggedized and conduction-

cooled versions available

Model 53630 COTS (left)and rugged version


Pentek, Inc.






16-bit D/A. The converter has an inputsample rate of 1 GSPS, allowing it to aceptfull rate data from the FPGA. Additionally,the D/A includes a 2x or 4x interpolationfilter for applications that provide 1/2 or 1/4rate input data. Analog output is througha front panel SSMC connector.




PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A


FPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

8X 4X 4X 40
















Pentek, Inc.



53630 1 GHz A/D and D/A,Virtex-6 FPGA - 3U VPX

Options:




-104 LVDS FPGA I/O to VPXP2

-105 Gigabit serial FPGA I/Oto VPX P1






versions

Model Description

8267 VPX Development System.See 8267 Datasheet forOptions



Fabric-Transparent Crossbar SwitchThe 53630 features a unique high-speed

switching configuration. A fabric-transpar-ent crossbar switch bridges numerousinterfaces and components on the boardusing gigabit serial data paths with no latency.Programmable signal input equalizationand output pre-emphasis settings enableoptimization. Data paths can be selected assingle (1X) lanes, or groups of four lanes (4X).












Custom I/OOption -104: Provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/OOption -105: Provides one 8X or two4X gigabit links between the FPGA andthe VPX P1 connector to support serialprotocols




Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

VPX FamiliesPentek offers two families of 3U VPX

products: the 53xxx and the 52xxx. For moreinformation on a 52xxx product, pleaserefer to the product datasheet. The table belowprovides a comparison of their main features.

VPX Family Comparison

52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8

on VPX P1 on VPX P1 or P2

20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No


integrated VPX developmentsystem for Pentek Cobalt andOnyx VPX boards. It was createdto save engineers and systemintegrators the time and expenseassociated with building and test-ing a development system thatensures optimum performanceof Pentek boards.


Pentek, Inc.







Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 52630 factory-installed functionsinclude an A/D acquisition and a D/A wave-form playback IP module. In addition, IPmodules for either DDR3 or QDRII+memories, a controller for all data clockingand synchronization functions, a test signalgenerator and a PCIe interface complete the

factory-installed functions and enable the52630 to operate as a complete turnkey solu-tion, without the need to develop any FPGA IP.







TIMING BUSGENERATOR


VCXO

16

QDRII+SRAM8 MB

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

RF Out

RFXFORMR

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16 1616 16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

1 GHz12-BIT A/D

12


Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2 VPX-P1

VIRTEX-6 FPGA


GTXGTXGTX

GigabitSerial I/O

Option -105

4X4X 4X

x4PCIe





■ One 1 GHz 12-bit A/D■ One 1 GHz 16-bit D/A■ Up to 2 GB of DDR3 SDRAM



for multiboard synchronization■ Optional LVDS connections








Pentek, Inc.






16-bit D/A. The converter has an inputsample rate of 1 GSPS, allowing it to aceptfull rate data from the FPGA. Additionally,the D/A includes a 2x or 4x interpolationfilter for applications that provide 1/2 or 1/4rate input data. Analog output is througha front panel SSMC connector.




PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A


FPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

4X 4X 4X 40
















Pentek, Inc.




Options:











versions

Model Description

















PCI-Express InterfacePCI Express Bus: Gen. 1 or Gen 2: x4


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.

1- or 2-Channel 1 GHz A/D, 1- or 2-Channel 1 GHz D/Awith Virtex-6 FPGA - 6U OpenVPX

Models57630 & 58630

General InformationModels 57630 and 58630 are members

of the Cobalt® family of high-performance6U OpenVPX boards based on the XilinxVirtex-6 FPGA. They consist of one ortwo Model 71630 XMC modules mountedon a VPX carrier board.

Model 57630 is a 6U board with oneModel 71630 module while the Model58630 is a 6U board with two XMC modulesrather than one.

These models include one or two 1 GHzA/D and D/A converters and four or eightbanks of memory



Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The factory-installed functions of thesemodels include one or two A/D acquisitionand one or two D/A waveform playbackIP modules. IP modules for either DDR3or QDRII+ memories, controllers for all dataclocking and synchronization functions, atest signal generator and a PCIe interfacecomplete the factory-installed functions

and enable these models to operate as com-plete turnkey solutions, without the need todevelop any FPGA IP.





Option -104 provides 20 LVDS pairsbetween the FPGA and the VPX P3 connec-tor, Model 57630; P3 and P5, Model 58630.

Option -105 supports serial protocallsby providing a 4X gigabit link between theFPGA and VPX P2, Model 57630; or one 4Xlink from each FPGA to P2 and an additional4X link between the FPGAs, Model 58630. ➤

New!

New!

New!

New!

New!


radio interface solution

■ Supports Xilinx Virtex-6LXT and SXT FPGAs

■ One or two 1 GHz 12-bit A/D■ One or two 1 GHz 16-bit D/A■ Up to 2 or 4 GB of DDR3

SDRAM; or: 16 MB or 32 MBof QDRII+ SRAM

■ PCI Express (Gen. 1 & 2)interface up to x8

■ Sample clock synchronization toan external system reference

■ Dual-µSync clock/sync busfor multiboard synchronization

■ Optional user-configurablegigabit serial interface

■ Optional LVDS connectionsto the Virtex-6 FPGA forcustom I/O

■ Ruggedized and conduction-cooled versions available

VIRTEX-6 FPGA


16

QDRII+SRAM8 MB

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

Memory Banks 1 & 2 Memory Banks 3 & 4

DDR3 option 155

QDRII+ option 160

DDR3 option 165

LVDS GTX

40 8X

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P3

GTXGTX

PCIeGen. 2 x8

4X4X

PCIeGen. 2 x8

VPX-P2VPX-P1

PCIe-to PCIeSWITCH

From/To

Other XMC

Module of

Model 58630

Option -105

Gigabit Serial I/O

Block Diagram, Model 57630.

Model 58630 doubles all

resources except the

PCIe-to-PCIe Switch and

provides 20 LVDS pairs

from the 2nd FPGA to VPX-P5

TIMING BUSGENERATOR


VCXO

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

RF In

RFXFORMR

1 GHz12-BIT A/D

12Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

Model 58630


Pentek, Inc.


Models57630 & 58630

4630 ➤➤➤➤➤ A/D Converter StageThe front end accepts one or two ana-

log HF or IF inputs on front panel SSMCconnectors with transformer couplinginto one or two Texas InstrumentsADS5400 1 GHz, 12-bit A/D converters.


D/A Converter StageThe 71630 features one or two TI

DAC5681Z 1 GHz, 16-bit D/As. The con-verters have an input sample rate of 1 GSPS,allowing them to acept full rate data fromthe FPGA. Additionally, the D/As includea 2x or 4x interpolation filter for applicationsthat provide 1/2 or 1/4 rate input data.Analog output is through front panelSSMC connectors.




PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A


FPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

8X 4X 4X 40



The Pentek Model 9192 Cobalt Synchro-nizer can drive multiple µSync connectorsenabling large, multichannel synchronousconfigurations. Also, an LVTTL externalgate/trigger input is accepted on a frontpanel SSMC connector.

Memory ResourcesThe Cobalt architecture supports up to

four or eight independent memory bankswhich can be configured with all QDRII+SRAM, DDR3 SDRAM, or as combinationof two banks of each type of memory. EachQDRII+ SRAM bank can be up to 8 MBdeep and is an integral part of the module’sDMA capabilities, providing FIFO memoryspace for creating DMA packets. For appli-cations requiring deep memory resources,DDR3 SDRAM banks can each be up to512 MB deep. Built-in memory functionsinclude an A/D data transient capturemode and D/A waveform playback mode.


A/D Acquisition IP ModuleThese models feature one or

two A/D Acquisition IP Mod-ules for easy capture and datamoving. The IP module canreceive data from the A/D, atest signal generator, or from theD/A Waveform Playback IPModule in loopback mode. TheIP module has associated memorybanks for buffering data in FIFOmode or for storing data in tran-sient capture mode. The memorybanks are supported with a DMAengine for moving A/D datathrough the PCIe interface.



D/A Waveform PlaybackIP Modules

The factory-installed functionsinclude one or two sophisti-cated D/A Waveform PlaybackIP modules. A linked-list con-troller allows users to easilyplay back waveforms stored ineither on-board memory or off-board host memory to the D/A.


Up to 64 or 128 individuallink entries can be chainedtogether to create complexwaveforms with a minimum ofprogramming.


Pentek, Inc.


Models57630 & 58630

4630


57630 1 GHz A/D and D/A withVirtex-6 FPGA - 6U VPX

58630 Two 1 GHz A/D and D/A,with two Virtex-6 FPGAs -6U VPX

Options:




-104 LVDS I/O between theFPGA and P3 connector,Model 57630; P3 and P5connectors, Model 58630

-105 Gigabit link between theFPGA and P2 connector,Model 57630; gigabit linksfrom each FPGA to P2connector, Model 78630






versions

Model Description


➤➤➤➤➤ PCI Express InterfaceThese models include an industry-

standard interface fully compliant with PCIExpress Gen. 1 and 2 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the board.

SpecificationsModel 57630: 1 A/D, 1 D/AModel 58630: 2 A/Ds, 2 D/AsFront Panel Analog Signal Inputs (1 or 2)


A/D Converters (1 or 2)Type: Texas Instruments ADS5400Sampling Rate: 100 MHz to 1 GHzResolution: 12 bits

D/A Converters (1 or 2)Type: Texas Instruments DAC5681ZInput Data Rate: 1 GHz max.Interpolation Filter: bypass, 2x or 4xOutput Sampling Rate: 1 GHz max.Resolution: 16 bits

Front Panel Analog Signal Outputs (1 or 2)Output Type: Transformer-coupled,front panel female SSMC connectors

Sample Clock Sources (1 or 2)On-board clock synthesizer generatestwo clocks: one A/D clock and one D/Aclock

Clock Synthesizers (1 or 2)Clock Source: Selectable from on-boardprogrammable VCXO or front panel ex-ternal clockVCXO Frequency Ranges: 10 to 945MHz, 970 to 1134 MHz, and 1213 to1417 MHzSynchronization: VCXO can be phase-locked to an external 4 to 200 MHz systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16, inde-pendently for the A/D clock and D/Aclock

External Clocks (1 or 2)Type: Front panel female SSMC connector,sine wave, 0 to +10 dBm, AC-coupled,50 ohms, accepts 100 MHz to 1 GHzdivider input clock, or PLL systemreference

Timing Bus (1 or 2): 19-pin µSync bus con-nector includes sync and gate/triggerinputs, CML

External Trigger Input (1 or 2)Type: Front panel female SSMC connector,LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Field Programmable Gate Arrays (1 or 2)Standard: Xilinx Virtex-6 XC6VLX130T-2Optional: Xilinx Virtex-6 XC6VLX240T-2or XC6VSX315T-2

Custom I/OOption -104: Provides 20 LVDS pairsbetween the FPGA and the VPX P3connector, Model 57630; P3 and P5,Model 58630Option -105: Supports serial protocolsby providing a 4X gigabit link betweenthe FPGA and VPX P2, Model 57630; orone 4X link from each FPGA to P2 andan additional 4X link between the FPGAs,Model 58630

Memory Banks (1 or 2)Option 150: Two 8 MB QDRII+ SRAMmemory banks, 400 MHz DDROption 155 or 165: Two 512 MB DDR3SDRAM memory banks, 400 MHz DDR

PCI-Express InterfacePCI Express Bus: Gen. 1 or 2: x4 or x8

Environmental: Level L1 & L2 air-cooled;Level L3 ruggedized, conduction-cooled

Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)


integrated development systemfor Pentek Cobalt and Onyx6U VPX boards. It was createdto save engineers and systemintegrators the time and expenseassociated with building andtesting a development systemthat ensures optimum perfor-mance of Pentek boards.


Pentek, Inc.

1- or 2-Channel 1 GHz A/D, 1- or 2-Channel 1 GHz D/Awith Virtex-6 FPGA - cPCI

Models 72630,73630 and 74630

General InformationModels 72630, 73630 and 74630 are

members of the Cobalt® family of high per-formance CompactPCI boards based onthe Xilinx Virtex-6 FPGA. They consist ofone or two Model 71630 XMC modulesmounted on a cPCI carrier board.

Model 72630 is a 6U cPCI board whilethe Model 73630 is a 3U cPCI board; bothare equipped with one Model 71630 XMC.Model 74630 is a 6U cPCI board with twoXMC modules rather than one.




Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The factory-installed functions of thesemodels include one or two A/D acquisitionand one or two D/A waveform playbackIP module. IP modules for either DDR3 orQDRII+ memories, controllers for all data

clocking and synchronization functions, atest signal generator and a PCIe interfacecomplete the factory-installed functionsand enable these modles to operate as com-plete turnkey solutions, without the need todevelop any FPGA IP.





Option -104 provides 20 LVDS pairsbetween the FPGA and the J2 connector,Model 73630; J3 connector, Model 72630;J3 and J5 connectors, Model 74630. ➤



LXT and SXT FPGAs■ One or two 1 GHz 12-bit A/D

■ One or two 1 GHz 16-bit D/A■ Up to 2 or 4 GB of DDR3

SDRAM; or: 16 MB or 32 MBof QDRII+ SRAM


■ Dual-µSync clock/sync busfor multiboard synchronization


TIMING BUSGENERATOR


VCXO

16

QDRII+SRAM8 MB

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

RF Out

RFXFORMR

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16 1616 16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

1 GHz12-BIT A/D

12


Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

VIRTEX-6 FPGA

MODEL 73630

INTERFACES ONLY

PCIeto PCI

BRIDGE

40

LVDS GTX

OptionalFPGA I/O(Option -104)

PCI/PCI-X BUS32-bit, 33/66 MHz

J2

PCIeto PCI

BRIDGE

PCIto PCI

BRIDGE

From/To Other

XMC Module of

MODEL 74630

GTX

x4 PCIe

PCI/PCI-X BUS32/64-bit, 33/66 MHz

4X

Block Diagram, Model 72630

Model 74630 doubles all resources

except the PCI-to-PCI Bridge

40

LVDS


J3

VIRTEX-6 FPGA


Model 73630Model 74630


Pentek, Inc.


Models 72630,73630 and 74630

➤➤➤➤➤ A/D Converter StageThe front end accepts one or two ana-

log HF or IF input on front panel SSMCconnectors with transformer couplinginto one or two Texas InstrumentsADS5400 1 GHz, 12-bit A/D converters.


D/A Converter StageThe 71630 features one or two TI

DAC5681Z 1 GHz, 16-bit D/As. The con-verters have an input sample rate of 1 GSPS,allowing them to acept full rate data fromthe FPGA. Additionally, the D/As includea 2x or 4x interpolation filter for applica-tions that provide 1/2 or 1/4 rate input data.Analog output is through front panelSSMC connectors.




PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A

PCIeFPGA

I/O


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

4X 40



The Pentek Model 7292 and Model 9192Cobalt Synchronizers can drive multipleµSync connectors enabling large, multi-channel synchronous configurations. Also,an LVTTL external gate/trigger input isaccepted on a front panel SSMC connector.


four or eight independent memory bankswhich can be configured with all QDRII+SRAM, DDR3 SDRAM, or as combinationof two banks of each type of memory. EachQDRII+ SRAM bank can be up to 8 MBdeep and is an integral part of the module’sDMA capabilities, providing FIFO memoryspace for creating DMA packets. For appli-cations requiring deep memory resources,DDR3 SDRAM banks can each be up to512 MB deep. Built-in memory functionsinclude an A/D data transient capturemode and D/A waveform playback mode.











Pentek, Inc.


Models 72630,73630 and 74630


72630 1 GHz A/D and D/A,Virtex-6 FPGA - 6U cPCI


74630 Two 1 GHz A/D and D/A,Virtex-6 FPGA - 6U cPCI

Options:




-104 LVDS I/O between theFPGA and J2 connector,Model 73630; J3 connector,Model 72630; J3 and J5connectors, Model 74630





➤➤➤➤➤ PCI-X InterfaceThese models include an industry-stan-

dard interface fully compliant with PCI-Xbus specifications. The interface includesmultiple DMA controllers for efficient trans-fers to and from the board. Data widths of32 or 64 bits and data rates of 33 and 66 MHzare supported. Model 73630: 32 bits only.

SpecificationsModel 72630 or Model 73630: 1 A/D, 1 D/AModel 74630: 2 A/Ds, 2 D/AsFront Panel Analog Signal Inputs (1 or 2)











Custom I/OOption -104: Provides 20 LVDS pairsbetween the FPGA and the J2 connector,Model 73630; J3 connector, Model 72630;J3 and J5 connectors, Model 74630

Memory Banks (1 or 2)Option 150: Two 8 MB QDRII+ SRAMmemory banks, 400 MHz DDROption 155 or 165: Two 512 MB DDR3SDRAM memory banks, 400 MHz DDR

PCI-X InterfacePCI-X Bus: 32 or 64 bits at 33 or 66 MHzModel 73630: 32 bits only


Size: Standard 6U or 3U cPCI board


Pentek, Inc.

1 GHz A/D and 1 GHz D/A, Virtex-6 FPGA - AMCModel 56630


family of high performance AMC modulesbased on the Xilinx Virtex-6 FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communi-cations or radar system. Its built-in datacapture and playback features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGAprocessing IP.

It includes 1 GHz A/D and D/A convert-ers and four banks of memory. In additionto supporting PCI Express Gen. 2 as a nativeinterface, the Model 56630 includes a frontpanel general-purpose connector for appli-cation-specific I/O .



Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 56630 factory-installed functionsinclude an A/D acquisition and a D/Awaveform playback IP module. In addition,IP modules for either DDR3 or QDRII+







for multiboard synchronization■ PCI Express (Gen. 1 & 2)

interface up to x8■ AMC.1 compliant■ IPMI 2.0 compliant MMC

(Module ManagementController)

■ Optional front panel LVDSconnections to the Virtex-6FPGA for custom I/O

TIMING BUSGENERATOR


VCXO

16

QDRII+SRAM8 MB

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

RF Out

RFXFORMR

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16 1616 16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

1 GHz12-BIT A/D

12


Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

40

FPGAGPIO

(option 104)

LVDS

VIRTEX-6 FPGA


GTX

x8 PCIe

8X

FrontPanel

FrontPanel

AMCPorts 4 to 11

IPMICONTROLLER

RS-232

memories, a controller for all data clockingand synchronization functions, a test signalgenerator and a PCIe interface completethe factory-installed functions and enablethe 56630 to operate as a complete turnkeysolution, without the need to develop anyFPGA IP.


functions, users can install their own customIP for data processing. Pentek GateFlowFPGA Design Kits include all of the factoryinstalled modules as documented sourcecode. Developers can integrate their own IPwith the Pentek factory-installed functions oruse the GateFlow Design Kit to completelyreplace the Pentek IP with their own.



Option -104 installs a front panel connec-tor with 20 pairs of LVDS connections tothe FPGA for custom I/O. ➤


Pentek, Inc.






GHz, 16-bit D/A. The converter has aninput sample rate of 1 GSPS, allowing it toacept full rate data from the FPGA. Addi-tionally, the D/A includes a 2x or 4xinterpolation filter for applications that pro-vide 1/2 or 1/4 rate input data. Analogoutput is through a front panel SSMC con-nector.




PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A

PCIeFPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

8X 40

Either clock source (front panel or VCXO)can be used directly or can be divided inde-pendently by 2, 4, 8, or 16 to provide differentlower frequency A/D and D/A clocks.




four independent memory banks whichcan be configured with all QDRII+ SRAM,DDR3 SDRAM, or as combination of twobanks of each type of memory. Each QDRII+SRAM bank can be up to 8 MB deep and isan integral part of the module’s DMA capa-bilities, providing FIFO memory space forcreating DMA packets. For applicationsrequiring deep memory resources, DDR3SDRAM banks can each be up to 512 MBdeep. Built-in memory functions include anA/D data transient capture mode and D/Awaveform playback mode.











Pentek, Inc.



56630 1 GHz A/D and D/A,Virtex-6 FPGA - AMC

Options:




-104 LVDS FPGA I/O throughfront panel connector






versions

➤➤➤➤➤ AMC InterfaceThe Model 56630 complies with the

AMC.1 specification by providing an x8PCIe connection to AdvancedTCA carriersor µTCA chassis. Module management isprovided by an IPMI 2.0 MMC (ModuleManagement Controller).


standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the module.












Custom I/OOption -104: Installs a front panel connec-tor with 20 LVDS pairs to the FPGA



AMC InterfaceType: AMC.1Module Management: IPMI Version 2.0


Size: Single-width, full-height AMC mod-ule, 2.89 in. x 7.11 in.


Pentek, Inc.

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMCModel 71640


family of high performance XMC modulesbased on the Xilinx Virtex-6 FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communi-cations or radar system. Its built-in datacapture features offer an ideal turnkey solu-tion as well as a platform for developing anddeploying custom FPGA processing IP.

It includes a 3.6 GHz, 12-bit A/D con-verter and four banks of memory. In additionto supporting PCI Express Gen. 2 as a nativeinterface, the Model 71640 includes optionalgeneral purpose and gigabit serial connectorsfor application-specific I/O.



Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 71640 factory-installed functionsinclude an A/D acquisition IP module. Inaddition, IP modules for DDR3 memories, acontroller for all data clocking and synchro-nization functions, a test signal generator

and a PCIe interface complete the factory-installed functions and enable the 71640 tooperate as a complete turnkey solution,without the need to develop any FPGA IP.


functions, users can install their own customIP for data processing. Pentek GateFlow®

FPGA Design Kits include all of the factoryinstalled modules as documented sourcecode. Developers can integrate their ownIP with the Pentek factory-installed functionsor use the GateFlow Design Kit to completelyreplace the Pentek IP with their own.




Option -105 installs the P16 XMC connec-tor with dual 4X gigabit links to the FPGAto support other serial protocols. ➤

Features■ Ideal radar and software


LXT and SXT FPGAs■ One-channel mode with

3.6 GHz, 12-bit A/D■ Two-channel mode with

1.8 GHz, 12-bit A/Ds■ 2 GB of DDR3 SDRAM

■ Sync bus for multimodulesynchronization

■ PCI Express Gen. 2 interfacex8 wide



TIMING BUSGENERATOR

Clock / Sync /Gate / PPS

32

Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

3.6 GHz (1 Channel)or

1.8 GHz (2 Channel)12-Bit A/D

12


TTLPPS/Gate/Sync

40

GigabitSerial I/O

(option 105)

4X4X

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

GTXGTX LVDSGTX

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

VIRTEX-6 FPGA



Pentek, Inc.


➤➤➤➤➤ A/D Converter StageThe front end accepts analog HF or IF

inputs on a pair of front panel SSMC con-nectors with transformer coupling into aTexas Instruments ADC12D1800 12-bit A/D.The converter operates in single-channelinterleaved mode with a sampling rate of3.6 GHz and an input bandwidth of 1.75 GHz;or, in dual-channel mode with a samplingrate of 1.8 GHz and input bandwidth of2.8 GHz.

The ADC12D1800 provides a program-mable 15-bit gain adjustment allowing the71640 to have a full scale input range of+2 dBm to +4 dBm. A built-in AutoSync fea-ture supports A/D synchronization acrossmultiple modules.

The A/D digital outputs are deliveredinto the Virtex-6 FPGA for signal process-ing, data capture or for routing to othermodule resources.

Clocking and SynchronizationThe 71640 accepts a 1.8 GHz dual-edge

sample clock via a front panel SSMC con-nector. A second front panel SSMC acceptsa TTL signal that can function as Gate, PPSor Sync.

A front panel multi-pin sync bus con-nector allows multiple modules to besynchronized, ideal for larger multichanel

systems. The sync bus includes gate, resetand in and out reference clock signals.Multiple 71640s can be synchronized usingthe Cobalt high speed sync module todrive the sync bus.

Memory ResourcesThe 71640 architecture supports four

independent memory banks of DDR3SDRAM. Each bank is 512 MB deep and isan integral part of the module’s DMA anddata capture capabilities. Built-in memoryfunctions include an A/D data transientcapture mode for taking snapshots of datafor transfer to a host computer.

In addition to the factory-installedfunctions, custom user-installed IP withinthe FPGA can take advantage of the memo-ries for many other purposes.

XMC InterfaceThe Model 71640 complies with the

VITA 42.0 XMC specification. Two connec-tors each provide dual 4X links or a single8X link with up to a 5 GHz bit clock. Withdual XMC connectors, the 71640 supportsx8 PCIe on the first XMC connector leavingthe optional second connector free to supportuser-installed transfer protocols specific tothe target application. ➤


Acquisition IP Module for easycapture and data moving. The IPmodule can receive data fromthe A/D, or a test signal generator.The IP module has associatedmemory banks for buffering datain FIFO mode or for storing datain transient capture mode. Insingle-channel mode, all fourbanks are used to store thesingle-channel of input data. Indual-channel mode, memorybanks 1 and 2 store data frominput channel 1 and memorybanks 3 and 4 store data frominput channel 2. In both modes,continuous, full-rate transientcapture of 12-bit data is supported.

The memory banks are sup-ported with a DMA engine formoving A/D data through thePCIe interface. This powerfullinked-list DMA engine is capableof a unique Acquisition GateDriven mode. In this mode, thelength of a transfer performedby a link definition need not beknown prior to data acquisition;rather, it is governed by thelength of the acquisition gate.This is extremely useful in appli-cations where an external gatedrives acquisition and the exactlength of that gate is not knownor is likely to vary.


PCIe INTERFACE

fromA/D


FPGAGPIO



A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

TESTSIGNAL

GENERATOR

MEMORYCONTROLLER

8X 4X 4X 40toMem

Bank 2

toMem

Bank 1

fromA/D


A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

(Two channel mode shown)


Pentek, Inc.



71640 1-Ch. 3.6 GHz or 2-Ch.1.8 GHz, 12-bit A/D,Virtex-6 FPGA - XMC

Options:


-062 XC6VLX240T

-064 XC6VSX315T



-155* Two 512 MB DDR3SDRAM Memory Banks(Banks 1 and 2)


* These options are always required


versions

Model Description



standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications. Thex8 lane interface includes multiple DMAcontrollers for efficient transfers to and fromthe module.



A/D ConverterType: Texas Instruments ADC12D1800Sampling Rate: Single-channel mode:500 MHz to 3.6 GHz; dual-channelmode: 150 MHz to 1.8 GHzResolution: 12 bitsInput Bandwidth: single-channel mode:1.75 GHz; dual-channel mode: 2.8 GHzFull Scale Input: +2 dBm to +4 dBm,programmable

Sample Clock Sources: Front panel SSMCconnector

Sync Bus: Multi-pin connectors, busincludes gate, reset and in and out refclock

External Trigger InputType: Front panel female SSMC connec-tor, TTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS


Custom I/OOption -104: Installs the PMC P14connector with 20 LVDS pairs to theFPGAOption -105: Installs the XMC P16connector configurable as one 8X or two4X gigabit serial links to the FPGA

Memory: Four 512 MB DDR3 SDRAMmemory banks, 400 MHz DDR

PCI-Express InterfacePCI Express Bus: Gen. 1 or Gen. 2: x4 orx8






Pentek, Inc.

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - x8 PCIeModel 78640


family of high performance XMC modulesbased on the Xilinx Virtex-6 FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communi-cations or radar system. Its built-in datacapture features offer an ideal turnkey solu-tion as well as a platform for developing anddeploying custom FPGA processing IP.

The 78640 includes a 3.6 GHz, 12-bitA/D converter and four banks of memory.In addition to supporting PCI Express Gen. 2as a native interface, the Model 78640includes optional general-purpose and giga-bit serial connectors for application-specificI/O protocols.



Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 78640 factory-installed functionsinclude an A/D acquisition IP module. Inaddition, IP modules for DDR3 memories, acontroller for all data clocking and synchro-nization functions, a test signal generator

and a PCIe interface complete the factory-installed functions and enable the 78640 tooperate as a complete turnkey solution,without the need to develop any FPGA IP.












1.8 GHz, 12-bit A/Ds■ 2 GB of DDR3 SDRAM

■ Sync bus for multiboardsynchronization

■ PCI Express (Gen. 1 & 2)interface, up to x8

■ Clock/sync bus for multiboardsynchronization



TIMING BUSGENERATOR


32

Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR



12


TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

40 4X

GTX

4X

GTXLVDS GTX

OptionalFPGAGPIO

OptionalSerialI/O

8X

68-pinHeader

x8 PCI Express

Dual 4XSerialConn

x8 PCIe

VIRTEX-6 FPGA



Pentek, Inc.




The ADC12D1800 provides a program-mable 15-bit gain adjustment allowing the78640 to have a full scale input range of+2 dBm to +4 dBm. A built-in AutoSync fea-ture supports A/D synchronization acrossmultiple boards.

The A/D digital outputs are deliveredinto the Virtex-6 FPGA for signal processing,data capture or for routing to other moduleresources.



A front panel multi-pin sync busconnector allows multiple boards to be

synchronized, ideal for larger multichanelsystems. The sync bus includes gate, resetand in and out reference clock signals.Multiple 78640s can be synchronized usingthe Cobalt high speed sync board to drivethe sync bus.


independent memory banks of DDR3SDRAM. Each bank is 512 MB deep and isan integral part of the board’s DMA anddata capture capabilities. Built-in memoryfunctions include an A/D data transientcapture mode for taking snapshots of datafor transfer to a host computer.


PCI Express InterfaceThe Model 78640 includes an industry

standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications.Supporting PCIe links of x4 or x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the board. ➤





PCIe INTERFACE

fromA/D


FPGAGPIO



A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

TESTSIGNAL

GENERATOR

MEMORYCONTROLLER

8X 4X 4X 40toMem

Bank 2

toMem

Bank 1

fromA/D


A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3



Pentek, Inc.



78640 1-Ch. 3.6 GHz or 2-Ch.1.8 GHz, 12-bit A/D,Virtex-6 FPGA - x8 PCIe

Options:









Model Description


➤➤➤➤➤ SpecificationsFront Panel Analog Signal Inputs






Field Programmable Gate ArrayStandard: Xilinx Virtex-6 XC6VLX130T-2Optional: Xilinx Virtex-6 XC6VLX240T-2XC6VSX315T-2



PCI-Express InterfacePCI Express Bus: Gen. 1or Gen. 2: x4 orx8


Size: Half-length PCIe card, 4.38 in. x 7.13 in.




Pentek, Inc.

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - 3U VPXModel 53640


family of high-performance XMC modulesbased on the Xilinx Virtex-6 FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communi-cations or radar system. Its built-in datacapture features offer an ideal turnkey solu-tion as well as a platform for developing anddeploying custom FPGA processing IP.

The 53640 includes a 3.6 GHz, 12-bitA/D converter and four banks of memory.It features built-in support for PCI Expressover the 3U VPX backplane.



Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 53640 factory-installed functionsinclude an A/D acquisition IP module. Inaddition, IP modules for DDR3 memories, acontroller for all data clocking and synchro-nization functions, a test signal generatorand a PCIe interface complete the factory-

installed functions and enable the 53640 tooperate as a complete turnkey solution,without the need to develop any FPGA IP.







Option -105 provides dual 4X gigabitlinks between the FPGA and the VPX P1connector to support serial protocols. ➤





1.8 GHz, 12-bit A/Ds■ 2 GB of DDR3 SDRAM■ Sync bus for multiboard

synchronization■ Optional LVDS connections






TIMING BUSGENERATOR


32

Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR



12


TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTX

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

Option -105

4X8X 4X

x8PCIe

VIRTEX-6 FPGA




Pentek, Inc.








A front panel multipin sync busconnector allows multiple boards to be

synchronized, ideal for larger multichanelsystems. The sync bus includes gate, resetand in and out reference clock signals.Multiple 53640’s can be synchronized usingthe Cobalt high-speed sync board to drivethe sync bus.





standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications.Supporting PCIe links of x4 or x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the board. ➤





PCIe INTERFACE

fromA/D


FPGAGPIO



A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

TESTSIGNAL

GENERATOR

MEMORYCONTROLLER

8X 4X 4X 40toMem

Bank 2

toMem

Bank 1

fromA/D


A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3



Pentek, Inc.



53640 1-Ch. 3.6 GHz or 2-Ch.1.8 GHz, 12-bit A/D,Virtex-6 FPGA - 3U VPX

Options:










versions

Model Description


➤➤➤➤➤ Fabric-Transparent Crossbar SwitchThe 53640 features a unique high-speed

switching configuration. A fabric-transparentcrossbar switch bridges numerous interfacesand components on the board using gigabitserial data paths with no latency.

Programmable signal input equalizationand output pre-emphasis settings enableoptimization. Data paths can be selected assingle (1X) lanes, or groups of four lanes (4X).





Sync Bus: Multi-pin connectors, busincludes gate, reset and in and out ref-erence clock





PCI-Express InterfacePCI Express Bus: Gen. 1or Gen. 2: x4 orx8


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.



family of high-performance XMC modulesbased on the Xilinx Virtex-6 FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communi-cations or radar system. Its built-in datacapture features offer an ideal turnkey solu-tion as well as a platform for developing anddeploying custom FPGA processing IP.

The 52640 includes a 3.6 GHz, 12-bitA/D converter and four banks of memory.It features built-in support for PCI Expressover the 3U VPX backplane.



Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 52640 factory-installed functionsinclude an A/D acquisition IP module. Inaddition, IP modules for DDR3 memories, acontroller for all data clocking and synchro-nization functions, a test signal generatorand a PCIe interface complete the factory-

installed functions and enable the 52640 tooperate as a complete turnkey solution,without the need to develop any FPGA IP.







Option -105 provides dual 4X gigabitlinks between the FPGA and the VPX P1connector to support serial protocols. ➤Features

■ Ideal radar and softwareradio interface solution


■ One-channel mode with3.6 GHz, 12-bit A/D

■ Two-channel mode with1.8 GHz, 12-bit A/Ds

■ 2 GB of DDR3 SDRAM■ Sync bus for multiboard







TIMING BUSGENERATOR


32

Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR



12


TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2 VPX-P1

VIRTEX-6 FPGA


GTXGTXGTX

GigabitSerial I/O

Option -105

4X4X 4X

x4PCIe



Pentek, Inc.






Clocking and SynchronizationThe 52640 accepts an 1.8 GHz dual-edge


A front panel multipin sync busconnector allows multiple boards to be

synchronized, ideal for larger multichanelsystems. The sync bus includes gate, resetand in and out reference clock signals.Multiple 52640’s can be synchronized usingthe Cobalt high-speed sync board to drivethe sync bus.





standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications.Supporting PCIe links up to x4, the inter-face includes multiple DMA controllers forefficient transfers to and from the board. ➤





PCIe INTERFACE

fromA/D


FPGAGPIO



A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

TESTSIGNAL

GENERATOR

MEMORYCONTROLLER

4X 4X 4X 40toMem

Bank 2

toMem

Bank 1

fromA/D


A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3



Pentek, Inc.




Options:










versions

Model Description






Sync Bus: Multi-pin connectors, busincludes gate, reset and in and out ref-erence clock





PCI-Express InterfacePCI Express Bus: Gen. 1 or Gen. 2: x4


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm).




52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.

1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bitA/D, Virtex-6 FPGA - 6U OpenVPX

Models57640 & 58640




These models include one or two 3.6 GHz,12-bit A/D converters and four or eightbanks of memory.



Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The factory-installed functions of thesemodels include one or two A/D acquisitionIP modules. In addition, IP modules for DDR3memories, controllers for all data clockingand synchronization functions, a test signalgenerator and a PCIe interface completethe factory-installed functions and enable

these models to operate as complete turn-key solutions, without the need to developany FPGA IP.








New!

New!

New!

New!

New!

VIRTEX-6 FPGA


16

ConfigFLASH64 MB

LVDS GTX

40 8X

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P3

GTXGTX

PCIeGen. 2 x8

4X4X

PCIeGen. 2 x8

VPX-P2VPX-P1

PCIe-to PCIeSWITCH

From/To

Other XMC

Module of

Model 58640

Option -105

Gigabit Serial I/O







TIMING BUSGENERATOR


Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

RF In

RFXFORMR



12

TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB


Model 58640




■ One or two 1-channel modewith 3.6 GHz, 12-bit A/Ds

■ Two or four 2-channel modewith 1.8 GHz, 12-bit A/Ds

■ 2 or 4 GB of DDR3 SDRAM■ PCI Express (Gen. 1 & 2)

interface up to x8■ µSync clock/sync bus for

multiboard synchronization■ Optional user-configurable





Pentek, Inc.


Models57640 & 58640



The ADC12D1800 provides a program-mable 15-bit gain adjustment allowing thesemodels to have a full scale input range of+2 dBm to +4 dBm. A built-in AutoSync fea-ture supports A/D synchronization acrossmultiple boards.


Clocking and SynchronizationThese models accept a 1.8 GHz dual-

edge sample clock via front panel SSMCconnectors. A second front panel SSMCaccepts a TTL signal that can function asGate, PPS or Sync.


synchronized, ideal for larger multichanelsystems. The sync bus includes gate, resetand in and out reference clock signals.Multiple boards can be synchronized usingthe Cobalt high speed sync board to drivethe sync bus.

Memory ResourcesThe Cobalt architecture supports four

or eight independent memory banks ofDDR3 SDRAM. Each bank is 512 MB deepand is an integral part of the board’s DMAand data capture capabilities. Built-inmemory functions include an A/D datatransient capture mode for taking snapshotsof data for transfer to a host computer.


PCI Express InterfaceThese models include an industry-

standard interface fully compliant with PCIExpress Gen. 1 and 2 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the board. ➤

A/D Acquisition IP ModulesThese models feature one or

two A/D Acquisition IP Mod-ules for easy capture and datamoving. The IP modules canreceive data from the A/Ds, or atest signal generator. The IP mod-ules have associated memorybanks for buffering data in FIFOmode or for storing data in tran-sient capture mode.In single-channel mode, all banksare used to store the single-channelof input data. In dual-channelmode, memory banks 1 and 2store data from input channel 1and memory banks 3 and 4store data from input channel 2.In both modes, continuous,full-rate transient capture of 12-bitdata is supported.



PCIe INTERFACE

fromA/D


FPGAGPIO



A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

TESTSIGNAL

GENERATOR

MEMORYCONTROLLER

8X 4X 4X 40toMem

Bank 2

toMem

Bank 1

fromA/D


A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3



Pentek, Inc.


Models57640 & 58640



58640 2-Ch. 3.6 GHz or 4-Ch.1.8 GHz, 12-bit A/D withtwo Virtex-6 FPGAs - 6UVPX

Options:


-062 XC6VLX240T

-064 XC6VSX315T







versions

Model Description


➤➤➤➤➤ SpecificationsModel 57640: One A/DModel 58640: Two A/DsFront Panel Analog Signal Inputs (2 or 4)


A/D Converter (1 or 2)Type: Texas Instruments ADC12D1800Sampling Rate: Single-channel mode:500 MHz to 3.6 GHz; dual-channelmode: 150 MHz to 1.8 GHzResolution: 12 bitsInput Bandwidth: single-channel mode:1.75 GHz; dual-channel mode: 2.8 GHzFull Scale Input: +2 dBm to +4 dBm,programmable

Sample Clock Sources (1 or 2)Front panel SSMC connector

Sync Bus (1 or 2)Multi-pin connectors, bus includes gate,reset and in and out ref clock

External Trigger Input (1 or 2)Type: Front panel female SSMC connec-tor, TTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Field Programmable Gate Array (1 or 2)Standard: Xilinx Virtex-6 XC6VLX130T-2Optional: Xilinx Virtex-6 XC6VLX240T-2or XC6VSX315T-2


Memory Banks (1 or 2)Four 512 MB DDR3 SDRAM memorybanks, 400 MHz DDR



Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




Pentek, Inc.

1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bitA/D, Virtex-6 FPGA - cPCI

Models 72640,73640 and 74640




These models include one or two 3.6 GHz,12-bit A/D converters and four or eightbanks of memory.



Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The factory-installed functions of thesemodels include one or two A/D acquisitionIP modules. In addition, IP modules for DDR3memories, controllers for all data clockingand synchronization functions, a test signal

generator and a PCIe interface completethe factory-installed functions and enablethese models to operate as complete turn-key solutions, without the need to developany FPGA IP.










■ One or two 1-channel modewith 3.6 GHz, 12-bit A/Ds

■ Two or four 2-channel modewith 1.8 GHz, 12-bit A/Ds

■ 2 or 4 GB of DDR3 SDRAM■ Sync bus for multiboard



TIMING BUSGENERATOR


32

Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR


1.8 GHz (2 Channel)12-bit A/D

12


TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12




VIRTEX-6 FPGA

MODEL 73640

INTERFACES ONLY

PCIeto PCI

BRIDGE

40

LVDS GTX



J2

PCIeto PCI

BRIDGE

PCIto PCI

BRIDGE

From/To Other

XMC Module of

MODEL 74640

GTX

x4 PCIe


4X40

LVDS


J3

VIRTEX-6 FPGA




Pentek, Inc.


Models 72640,73640 and 74640



The ADC12D1800 provides a program-mable 15-bit gain adjustment allowing thesemodels to have a full scale input range of+2 dBm to +4 dBm. A built-in AutoSync fea-ture supports A/D synchronization acrossmultiple boards.



edge sample clock via front panel SSMCconnectors. A second front panel SSMCaccepts a TTL signal that can function asGate, PPS or Sync.


synchronized, ideal for larger multichanelsystems. The sync bus includes gate, resetand in and out reference clock signals.Multiple boards can be synchronized usingthe Cobalt high speed sync board to drivethe sync bus.

Memory ResourcesThe Cobalt architecture supports four

or eight independent memory banks ofDDR3 SDRAM. Each bank is 512 MB deepand is an integral part of the board’s DMAand data capture capabilities. Built-inmemory functions include an A/D datatransient capture mode for taking snapshotsof data for transfer to a host computer.


PCI-X InterfaceThese models include an industry-stan-

dard interface fully compliant with PCI-Xbus specifications. The interface includesmultiple DMA controllers for efficient trans-fers to and from the board. Data widths of32 or 64 bits and data rates of 33 and 66 MHzare supported. Model 73640: 32 bits only. ➤

A/D Acquisition IP ModulesThese models feature one or

two A/D Acquisition IP Mod-ules for easy capture and datamoving. The IP modules canreceive data from the A/Ds, or atest signal generator. The IP mod-ules have associated memorybanks for buffering data in FIFOmode or for storing data in tran-sient capture mode.In single-channel mode, all banksare used to store the single-channelof input data. In dual-channelmode, memory banks 1 and 2store data from input channel 1and memory banks 3 and 4store data from input channel 2.In both modes, continuous,full-rate transient capture of 12-bitdata is supported.



PCIe INTERFACE

fromA/D

PCIeFPGA

I/O



A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

TESTSIGNAL

GENERATOR

MEMORYCONTROLLER

4X 40toMem

Bank 2

toMem

Bank 1

fromA/D


A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3



Pentek, Inc.


Models 72640,73640 and 74640


72640 1-Ch. 3.6 GHz or 2-Ch.1.8 GHz, 12-bit A/D,Virtex-6 FPGA - 6U cPCI



Options:


-062 XC6VLX240T

-064 XC6VSX315T





➤➤➤➤➤ SpecificationsModel 72640 or Model 73640: One A/DModel 74640: Two A/DsFront Panel Analog Signal Inputs (2 or 4)


A/D Converter (1 or 2)Type: Texas Instruments ADC12D1800Sampling Rate: Single-channel mode:500 MHz to 3.6 GHz; dual-channelmode: 150 MHz to 1.8 GHzResolution: 12 bitsInput Bandwidth: single-channel mode:1.75 GHz; dual-channel mode: 2.8 GHzFull Scale Input: +2 dBm to +4 dBm,programmable


Sync Bus (1 or 2)Multi-pin connectors, bus includes gate,reset and in and out ref clock

External Trigger Input (1 or 2)Type: Front panel female SSMC connec-tor, TTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Field Programmable Gate Array (1 or 2)Standard: Xilinx Virtex-6 XC6VLX130T-2Optional: Xilinx Virtex-6 XC6VLX240T-2or XC6VSX315T-2


Memory Banks (1 or 2)Four 512 MB DDR3 SDRAM memorybanks, 400 MHz DDR





Pentek, Inc.

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - AMCModel 56640


family of high-performance AMC modulesbased on the Xilinx Virtex-6 FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communi-cations or radar system. Its built-in datacapture features offer an ideal turnkey solu-tion as well as a platform for developing anddeploying custom FPGA processing IP.

It includes a 3.6 GHz, 12-bit A/D con-verter and four banks of memory. In additionto supporting PCI Express Gen. 2 as a nativeinterface, the Model 56640 includes a frontpanel general-purpose connector for appli-cation-specific I/O .



Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 56640 factory-installed functionsinclude an A/D acquisition IP module. Inaddition, IP modules for DDR3 memories, a

controller for all data clocking and synchro-nization functions, a test signal generatorand a PCIe interface complete the factory-installed functions and enable the 56640 tooperate as a complete turnkey solution,without the need to develop any FPGA IP.






Option -104 installs a front panel connec-tor with 20 pairs of LVDS connections tothe FPGA for custom I/O. ➤Features

■ Ideal radar and softwareradio interface solution




■ 2 GB of DDR3 SDRAM


■ Sync bus for multimodulesynchronization


■ AMC.1 compliant■ IPMI 2.0 compliant MMC



TIMING BUSGENERATOR


32

Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR



12


TTLPPS/Gate/Sync

40

FPGAGPIO

(option 104)

LVDS

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

VIRTEX-6 FPGA


GTX

x8 PCIe

8X

FrontPanel

FrontPanel

AMCPorts 4 to 11

IPMICONTROLLER

RS-232


Pentek, Inc.




The ADC12D1800 provides a program-mable 15-bit gain adjustment allowing the56640 to have a full scale input range of+2 dBm to +4 dBm. A built-in AutoSync fea-ture supports A/D synchronization acrossmultiple modules.




A front panel multi-pin sync busconnector allows multiple modules to be

synchronized, ideal for larger multichanelsystems. The sync bus includes gate, resetand in and out reference clock signals.Multiple 56640’s can be synchronized us-ing the Cobalt high speed sync module todrive the sync bus.


independent memory banks of DDR3SDRAM. Each bank is 512 MB deep and isan integral part of the module’s DMA anddata capture capabilities. Built-in memoryfunctions include an A/D data transientcapture mode for taking snapshots of datafor transfer to a host computer.


AMC InterfaceThe Model 56640 complies with the

AMC.1 specification by providing an x8PCIe connection to AdvancedTCA carriersor µTCA chassis. Module management isprovided by an IPMI 2.0 MMC (ModuleManagement Controller). ➤





PCIe INTERFACE

fromA/D

PCIeFPGAGPIO



A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

TESTSIGNAL

GENERATOR

MEMORYCONTROLLER

8X 40toMem

Bank 2

toMem

Bank 1

fromA/D


A/D

ACQUISITION

IP MODULE

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3



Pentek, Inc.



56640 1-Ch. 3.6 GHz or 2-Ch.1.8 GHz, 12-bit A/D,Virtex-6 FPGA - AMC

Options:


-062 XC6VLX240T

-064 XC6VSX315T






versions


standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications. Thex8 lane interface includes multiple DMAcontrollers for efficient transfers to and fromthe module.








Custom I/OOption -104: Installs a front panel con-nector with 20 LVDS pairs to the FPGA


PCI-Express InterfacePCI Express Bus: Gen. 1 or Gen. 2: x4 orx8





Pentek, Inc.

4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - XMCModel 71660


family of high performance XMC modulesbased on the Xilinx Virtex-6 FPGA. A multi-channel, high-speed data converter, it issuitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capture features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGAprocessing IP.

It includes four A/Ds and four banks ofmemory. In addition to supporting PCI Ex-press Gen. 2 as a native interface, the Model71660 includes general purpose and gigabitserial connectors for application-specific I/O .

The Cobalt ArchitectureThe Pentek Cobalt Architecture features

a Virtex-6 FPGA. All of the board’s data andcontrol paths are accessible by the FPGA,enabling factory-installed functions includingdata multiplexing, channel selection, datapacking, gating, triggering and memorycontrol. The Cobalt Architecture organizesthe FPGA as a container for data processingapplications where each function exists as anintellectual property (IP) module.

Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analoginterfaces. The 71660 factory-installedfunctions include four A/D acquisition IPmodules.

IP modules for either DDR3 or QDRII+memories, a controller for all data clockingand synchronization functions, a test signal

generator, and a PCIe interface complete thefactory-installed functions and enable the71660 to operate as a complete turnkeysolution without the need to develop anyFPGA IP.


function, users can install their own customIP for data processing. Pentek GateFlowFPGA Design Kits include all of the factory-installed modules as documented sourcecode. Developers can integrate their ownIP with the Pentek factory-installed functionsor use the GateFlow kit to completely replacethe Pentek IP with their own.







LXT and SXT FPGAs■ Four 200 MHz 16-bit A/Ds■ Up to 2 GB of DDR3 SDRAM


an external system reference■ LVPECL clock/sync bus for

multimodule synchronization■ PCI Express (Gen. 1 & 2)

interface up to x8■ VITA 42.0 XMC compatible

with switched fabric interfaces■ Optional user-configurable



TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

16

QDRII+SRAM8 MB

TTL Gate / TrigTTL Sync / PPS

Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

200 MHz16-BIT A/D

16


DDR3 option 155

QDRII+ option 160

DDR3 option 165

RF In

RFXFORMR

200 MHz16-BIT A/D

16

Gate / Trigger /Sync / PPS

40

GigabitSerial I/O

(option 105)

4X

GTX

4X

GTX LVDSGTX

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

VIRTEX-6 FPGA



Pentek, Inc.


➤ ➤ ➤ ➤ ➤ A/D Converter StageThe front end accepts four full-scale

analog HF or IF inputs on front panel SSMCconnectors at +8 dBm into 50 ohms withtransformer coupling into four TexasInstruments ADS5485 200 MHz, 16-bitA/D converters.


Clocking and SynchronizationAn internal timing bus provides all

timing and synchronization required bythe A/D converters. It includes a clock, twosync and two gate or trigger signals. An on-board clock generator receives an externalsample clock from the front panel SSMCconnector. This clock can be used directlyby the A/D or divided by a built-in clocksynthesizer circuit. In an alternate mode,the sample clock can be sourced from anon-board programmable voltage-controlledcrystal oscillator. In this mode, the frontpanel SSMC connector can be used toprovide a 10 MHz reference clock for synchro-nizing the internal oscillator.

A front panel 26-pin LVPECL Clock/Syncconnector allows multiple modules to besynchronized. In the slave mode, it acceptsLVPECL inputs that drive the clock, syncand gate signals. In the master mode, the

LVPECL bus can drive the timing signalsfor synchronizing multiple modules.

Multiple 71660’s can be driven from theLVPECL bus master, supporting synchro-nous sampling and sync functions acrossall connected modules.


four independent memory banks whichcan be configured with all QDRII+ SRAM,DDR3 SDRAM, or as combination of twobanks of each type of memory.

Each QDRII+ SRAM bank can be up to8 MB deep and is an integral part of themodule’s DMA capabilities, providingFIFO memory space for creating DMApackets. For applications requiring deepermemory resources, DDR3 SDRAM bankscan each be up to 512 MB deep. Built-inmemory functions include multichannelA/D data capture, tagging and streaming.



VITA 42.0 XMC specification. Two connec-tors each provide dual 4X links or a single8X link with up to a 6 GHz bit clock. Withdual XMC connectors, the 71660 ➤

A/D Acquisition IP ModulesThe 71660 features four A/D

Acquisition IP Modules for eas-ily capturing and moving data.Each IP module can receive datafrom any of the four A/Ds or atest signal generator

Each IP module has an asso-ciated memory bank for bufferingdata in FIFO mode or for storingdata in transient capture mode.All memory banks are supportedwith DMA engines for easilymoving A/D data through thePCIe interface. These powerfullinked-list DMA engines arecapable of a unique AcquisitionGate Driven mode. In this mode,the length of a transfer performedby a link definition need not beknown prior to data acquisition;rather, it is governed by the lengthof the acquisition gate. This isextremely useful in applicationswhere an external gate drivesacquisition and the exact lengthof that gate is not known or islikely to vary.

For each transfer, the DMAengine can automatically constructmetadata packets containingA/D channel ID, a sample-accu-rate time stamp and data lengthinformation. These actions sim-plify the host processor’s job ofidentifying and executing on thedata.

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX

INPUT MULTIPLEXERTEST

SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40


Pentek, Inc.



71660 4-Channel 200 MHz A/Dwith Virtex-6 FPGA - XMC

Options:










versions

Model Description


➤ supports x8 PCIe on the first XMC con-nector leaving the second connector free tosupport user-installed transfer protocolsspecific to the target application.


standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllersfor efficient transfers to and from themodule.


Input Type: Transformer-coupled, frontpanel female SSMC connectorsTransformer Type: Coil CraftWBC4-6TLBFull Scale Input: +8 dBm into 50 ohms3 dB Passband: 300 kHz to 700 MHz

A/D ConvertersType: Texas Instruments ADS5485Sampling Rate: 10 MHz to 200 MHzResolution: 16 bits

Sample Clock Sources: On-board clocksynthesizer

Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO (10 to 810 MHz),front panel external clock or LVPECLtiming busSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLL systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16 for theA/D clock

External ClockType: Front panel female SSMC connec-tor, sine wave, 0 to +10 dBm, AC-coupled,50 ohms, accepts 10 to 800 MHz dividerinput clock or PLL system reference

Timing Bus: 26-pin front panel connector;LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal forgate/trigger and sync/PPS inputs

External Trigger InputType: Front panel female SSMC connec-tor, LVTTLFunction: Programmable functions in-clude: trigger, gate, sync and PPS

Field Programmable Gate ArrayStandard: Xilinx Virtex-6 XC6VLX130TOptional: Xilinx Virtex-6 XC6VLX240T,or XC6VSX315T


MemoryOption 150 or 160: Two 8 MB QDRII+SRAM memory banks, 400 MHz DDROption 155 or 165: Two 512 MB DDR3SDRAM memory banks, 400 MHz DDR

PCI-Express InterfacePCI Express Bus: Gen. 1: x4 or x8;Gen. 2: x4






Pentek, Inc.

Model 78660 4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - x8 PCIe


family of high performance PCIe boardsbased on the Xilinx Virtex-6 FPGA. A mul-tichannel, high-speed data converter, it issuitable for connection to HF or IF ports of acommunications or radar system. Its built-indata capture features offer an ideal turnkeysolution.

It includes four A/Ds and four banks ofmemory. In addition to supporting PCI Ex-press Gen. 2 as a native interface, the Model78660 includes optional general-purposeand gigabit serial connectors for application-specific I/O protocols.



Each member of the Cobalt family is deliv-ered with factory installed applications ideallymatched to the board’s analog interfaces.The 78660 factory-installed functions includefour A/D acquisition IP modules.

IP modules for either DDR3 or QDRII+memories, a controller for all data clockingand synchronization functions, a test signalgenerator, and a PCIe interface complete thefactory- installed functions and enable the

78660 to operate as a complete turnkeysolution without the need to develop anyFPGA IP.


function, users can install their own customIP for data processing. Pentek GateFlowFPGA Design Kits include all of the factoryinstalled modules as documented sourcecode. Developers can integrate their ownIP with the Pentek factory-installed functionsor use the GateFlow kit to completely replacethe Pentek IP with their own.








or 32 MB of QDRII+ SRAM■ Sample clock synchronization

to an external system reference■ LVPECL clock/sync bus for

multiboard synchronization■ PCI Express (Gen. 1 & 2)




TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

16

QDRII+SRAM8 MB


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

200 MHz16-BIT A/D

16


DDR3 option 155

QDRII+ option 160

DDR3 option 165

RF In

RFXFORMR

200 MHz16-BIT A/D

16


40 4X

GTX

4X

GTXLVDS GTX

OptionalFPGAGPIO

OptionalSerialI/O

8X

68-pinHeader

x8 PCI Express

Dual 4XSerialConn

x8 PCIe

VIRTEX-6 FPGA



Pentek, Inc.





Clocking and SynchronizationAn internal timing bus provides all tim-

ing and synchronization required by theA/D converters. It includes a clock, twosync and two gate or trigger signals. Anon-board clock generator receives an externalsample clock from the front panel SSMCconnector. This clock can be used directlyby the A/D or divided by a built-in clocksynthesizer circuit.

In an alternate mode, the sample clockcan be sourced from an on-board program-mable voltage-controlled crystal oscillator.In this mode, the front panel SSMC connectorcan be used to provide a 10 MHz referenceclock for synchronizing the internal oscillator.

A front panel 26-pin LVPECL Clock/Syncconnector allows multiple boards to besynchronized. In the slave mode, it acceptsLVPECL inputs that drive the clock, syncand gate signals. In the master mode, the

LVPECL bus can drive the timing signalsfor synchronizing multiple boards.

Multiple 78660’s can be driven from theLVPECL bus master, supporting synchronoussampling and sync functions across all con-nected boards.



Each QDRII+ SRAM bank can be up to8 MB deep and is an integral part of theboard’s DMA capabilities, providing FIFOmemory space for creating DMA packets.For applications requiring deep memoryresources, DDR3 SDRAM banks can each be upto 512 MB deep. Built-in memory functionsinclude an A/D data transient capture modeand D/A waveform playback mode.



standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications.Supporting PCIe links up to x8, the interfaceincludes multiple DMA controllers forefficient transfers to and from the board. ➤

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40






Pentek, Inc.


➤ ➤ ➤ ➤ ➤ SpecificationsFront Panel Analog Signal Inputs








78660 4-Channel 200 MHz A/Dwith Virtex-6 FPGA - PCIe

Options:









Model Description



Field Programmable Gate ArrayStandard: Xilinx Virtex-6 XC6VLX130TOptional: Xilinx Virtex-6 XC6VLX240Tor XC6VSX315T









Pentek, Inc.

4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - 3U VPXModel 53660


family of high performance 3U VPX boardsbased on the Xilinx Virtex-6 FPGA. A multi-channel, high-speed data converter, it issuitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capture features offer an ideal turnkeysolution.

The 53660 includes four A/Ds and fourbanks of memory. It features built-in support forPCI Express over the 3U VPX backplane.


a Virtex-6 FPGA. All of the board’s data andcontrol paths are accessible by the FPGA,enabling factory-installed functions includingdata multiplexing, channel selection, datapacking, gating, triggering and memorycontrol. The Cobalt Architecture organizesthe FPGA as a container for data processingapplications where each function exists asan intellectual property (IP) module.

Each member of the Cobalt family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces.The 53660 factory-installed functions includefour A/D acquisition IP modules.

IP modules for either DDR3 or QDRII+memories, a controller for all data clockingand synchronization functions, a test signalgenerator, and a PCIe interface completethe factory-installed functions and enable

the 53660 to operate as a complete turnkeysolution, without the need to develop anyFPGA IP.


functions, users can install their own customIP for data processing. Pentek GateFlowFPGA Design Kits include all of the factory-installed modules as documented sourcecode. Developers can integrate their ownIP with the Pentek factory-installed func-tions or use the GateFlow kit to completelyreplace the Pentek IP with their own.





TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

16

QDRII+SRAM8 MB


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

200 MHz16-BIT A/D

16


DDR3 option 155

QDRII+ option 160

DDR3 option 165

RF In

RFXFORMR

200 MHz16-BIT A/D

16


40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTXLVDS

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

Option -105

4X8X 4X

x8PCIe

VIRTEX-6 FPGA






■ Four 200 MHz 16-bit A/Ds■ Up to 2 GB of DDR3 SDRAM



multiboard synchronization■ Optional LVDS connections








Pentek, Inc.







A front panel 26-pin LVPECL Clock/Syncconnector allows multiple boards to be syn-chronized. In the slave mode, it acceptsLVPECL inputs that drive the clock, syncand gate signals. In the master mode, the


Multiple 53660’s can be driven from theLVPECL bus master, supporting synchro-nous sampling and sync functions acrossall connected boards.



Each QDRII+ SRAM bank can be up to8 MB deep and is an integral part of theboard’s DMA capabilities, providing FIFOmemory space for creating DMA packets.For applications requiring deeper memoryresources, DDR3 SDRAM banks can eachbe up to 512 MB deep. Built-in memoryfunctions include multichannel A/D datacapture, tagging and streaming.

In addition to the factory-installed func-tions, custom user-installed IP within theFPGA can take advantage of the memoriesfor many other purposes.







PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40


Pentek, Inc.



53660 4-Channel 200 MHz,16-bit A/D with Virtex-6FPGA - 3U VPX

Options:










versions

Model Description


➤ ➤ ➤ ➤ ➤ Fabric-Transparent Crossbar SwitchThe 53660 features a unique high-speed

switching configuration. A fabric-transpar-ent crossbar switch bridges numerousinterfaces and components on the board usinggigabit serial data paths with no latency.Programmable signal input equalizationand output pre-emphasis settings enableoptimization. Data paths can be selected assingle (1X) lanes, or groups of four lanes (4X).


Input Type: Transformer-coupled,front panel female SSMC connectorsTransformer Type: Coil CraftWBC4-6TLBFull Scale Input: +8 dBm into 50 ohms3 dB Passband: 300 kHz to 700 MHz





Timing Bus: 26-pin front panel connectorLVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTLsignal for gate/trigger and sync/PPSinputs

External Trigger InputType: Front panel female SSMC connec-tor, LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS






Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.



family of high performance 3U VPX boardsbased on the Xilinx Virtex-6 FPGA. A multi-channel, high-speed data converter, it issuitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capture features offer an ideal turnkeysolution.

The 52660 includes four A/Ds and fourbanks of memory. It features built-in support forPCI Express over the 3U VPX backplane.



Each member of the Cobalt family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces.The 52660 factory-installed functions includefour A/D acquisition IP modules.

IP modules for either DDR3 or QDRII+memories, a controller for all data clockingand synchronization functions, a test signalgenerator, and a PCIe interface completethe factory-installed functions and enable

the 52660 to operate as a complete turnkeysolution, without the need to develop anyFPGA IP.







TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

16

QDRII+SRAM8 MB


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

200 MHz16-BIT A/D

16


DDR3 option 155

QDRII+ option 160

DDR3 option 165

RF In

RFXFORMR

200 MHz16-BIT A/D

16


40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

LVDS

VPX-P1

VIRTEX-6 FPGA


GTXGTXGTX

GigabitSerial I/O

Option -105

4X4X 4X

x4PCIe





■ Four 200 MHz 16-bit A/Ds■ Up to 2 GB of DDR3 SDRAM











Pentek, Inc.


➤➤➤➤➤ A/D Converter StageThe front end accepts four full-scale





A front panel 26-pin LVPECL Clock/Syncconnector allows multiple boards to be syn-chronized. In the slave mode, it acceptsLVPECL inputs that drive the clock, syncand gate signals. In the master mode, the


Multiple 52660’s can be driven from theLVPECL bus master, supporting synchro-nous sampling and sync functions acrossall connected boards.



Each QDRII+ SRAM bank can be up to8 MB deep and is an integral part of theboard’s DMA capabilities, providing FIFOmemory space for creating DMA packets.For applications requiring deeper memoryresources, DDR3 SDRAM banks can eachbe up to 512 MB deep. Built-in memoryfunctions include multichannel A/D datacapture, tagging and streaming.








PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

4X 4X 4X 40


Pentek, Inc.



52660 4-Channel 200 MHz,16-bit A/D with Virtex-6FPGA - 3U VPX

Options:










versions

Model Description


➤ ➤ ➤ ➤ ➤ SpecificationsFront Panel Analog Signal Inputs

Input Type: Transformer-coupled,front panel female SSMC connectorsTransformer Type: Coil CraftWBC4-6TLBFull Scale Input: +8 dBm into 50 ohms3 dB Passband: 300 kHz to 700 MHz





Timing Bus: 26-pin front panel connectorLVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTLsignal for gate/trigger and sync/PPSinputs







Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.

Models57660 & 58660

4- or 8-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA -6U OpenVPX




These models include four or eightA/Ds and four or eight banks of memory.


Virtex-6 FPGAs. All of the board’s data andcontrol paths are accessible by the FPGA,enabling factory-installed functions includingdata multiplexing, channel selection, datapacking, gating, triggering and memorycontrol. The Cobalt Architecture organizesthe FPGA as a container for data processingapplications where each function exists as anintellectual property (IP) module. Eachmember of the Cobalt family is delivered withfactory-installed applications ideally matchedto the board’s analog interfaces. The factory-installed functions of these models includefour or eight A/D acquisition IP modules.

IP modules for either DDR3 or QDRII+memories, controllers for all data clockingand synchronization functions, a test signalgenerator, and a PCIe interface complete thefactory-installed functions and enable these

models to operate as complete turnkey solu-tions without the need to develop FPGA IP.









LXT and SXT FPGAs■ Four or eight 200 MHz 16-bit

A/Ds■ Up to 2 or 4 GB of DDR3

SDRAM; or: 32 or 64 MB ofQDRII+ SRAM



■ LVPECL clock/sync bus formultiboard synchronization




VIRTEX-6 FPGA


16

QDRII+SRAM8 MB

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII+ option 160

DDR3 option 165

LVDS GTX

40 8X

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P3

GTXGTX

PCIeGen. 2 x8

4X4X

PCIeGen. 2 x8

VPX-P2VPX-P1

PCIe-to PCIeSWITCH

From/To

Other XMC

Module of

Model 58660

Option -105

Gigabit Serial I/O







TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D

A/D Clock/Sync Bus

1616

RF In

RFXFORMR

200 MHz16-BIT A/D

16

RF In

RFXFORMR

200 MHz16-BIT A/D

16

New!

New!

New!

New!

New!

Model 58660


Pentek, Inc.

Models57660 & 58660


➤ ➤ ➤ ➤ ➤ A/D Converter StagesThe front end accepts four or eight

full-scale analog HF or IF inputs on frontpanel SSMC connectors at +8 dBm into50 ohms with transformer coupling intofour or eight Texas Instruments ADS5485200 MHz, 16-bit A/D converters.

The digital outputs are delivered intothe Virtex-6 FPGAs for signal processing,data capture or for routing to other boardresources.





Multiple boards can be driven from theLVPECL bus master, supporting synchro-nous sampling and sync functions acrossall connected boards.


four or eight independent memory bankswhich can be configured with all QDRII+SRAM, DDR3 SDRAM, or as combinationof two banks of each type of memory.

Each QDRII+ SRAM bank can be up to8 MB deep and is an integral part of theboard’s DMA capabilities, providingFIFO memory space for creating DMApackets. For applications requiring deepermemory resources, DDR3 SDRAM bankscan each be up to 512 MB deep. Built-inmemory functions include multichannelA/D data capture, tagging and streaming.




A/D Acquisition IP ModulesThese models feature four

or eight A/D Acquisition IPModules for easily capturingand moving data. Each IPmodule can receive data fromany of four A/Ds or a testsignal generator

Each IP module has an asso-ciated memory bank for bufferingdata in FIFO mode or for storingdata in transient capture mode.All memory banks are supportedwith DMA engines for easilymoving A/D data through thePCIe interface. These powerfullinked-list DMA engines arecapable of a unique AcquisitionGate Driven mode. In this mode,the length of a transfer performedby a link definition need not beknown prior to data acquisition;rather, it is governed by thelength of the acquisition gate.This is extremely useful inapplications where an externalgate drives acquisition and theexact length of that gate is notknown or is likely to vary.

For each transfer, the DMAengine can automatically constructmetadata packets containingA/D channel ID, a sample-accu-rate time stamp and data lengthinformation. These actionssimplify the host processor’sjob of identifying and executingon the data.

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40


Pentek, Inc.

Models57660 & 58660



57660 4-Channel 200 MHz 16-bitA/D with Virtex-6 FPGA -6U VPX

58660 8-Channel 200 MHz 16-bitA/D with two Virtex-6FPGAs - 6U VPX

Options:










versions

Model Description


➤➤➤➤➤ SpecificationsModel 57660: 4 A/DsModel 58660: 8 A/DsFront Panel Analog Signal Inputs (4 or 8)


A/D Converters (4 or 8)Type: Texas Instruments ADS5485Sampling Rate: 10 MHz to 200 MHzResolution: 16 bits

Sample Clock Sources (1 or 2)On-board clock synthesizers

Clock Synthesizers (1 or 2)Clock Source: Selectable from on-boardprogrammable VCXO (10 to 810 MHz),front panel external clock or LVPECLtiming busSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLL systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16 for theA/D clock

External Clocks (1 or 2)Type: Front panel female SSMC connec-tor, sine wave, 0 to +10 dBm, AC-coupled,50 ohms, accepts 10 to 800 MHz dividerinput clock or PLL system reference

Timing Bus (1 or 2): 26-pin front panelconnector; LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTLsignal for gate/trigger and sync/PPSinputs

External Trigger Inputs (1 or 2)Type: Front panel female SSMC connec-tor, LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Field Programmable Gate Arrays (1 or 2)Standard: Xilinx Virtex-6 XC6VLX130TOptional: Xilinx Virtex-6 XC6VLX240Tor XC6VSX315T


Memory Banks (1 or 2)Option 150 or 160: Two 8 MB QDRII+SRAM memory banks, 400 MHz DDROption 155 or 165: Two 512 MB DDR3SDRAM memory banks, 400 MHz DDR



Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




Pentek, Inc.

Models 72660,73660 and 74660 4- or 8-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - cPCI






Virtex-6 FPGAs. All of the board’s data andcontrol paths are accessible by the FPGA,enabling factory-installed functions includingdata multiplexing, channel selection, datapacking, gating, triggering and memorycontrol. The Cobalt Architecture organizesthe FPGA as a container for data processingapplications where each function exists as anintellectual property (IP) module. Eachmember of the Cobalt family is delivered withfactory-installed applications ideally matchedto the board’s analog interfaces. The factory-installed functions of these models includefour or eight A/D acquisition IP modules.

IP modules for either DDR3 or QDRII+memories, controllers for all data clockingand synchronization functions, a test signal

generator, and a PCIe interface complete thefactory-installed functions and enable thesemodels to operate as complete turnkey solu-tions without the need to develop FPGA IP.








LXT and SXT FPGAs■ Four or eight 200 MHz 16-bit

A/Ds■ Up to 2 or 4 GB of DDR3

SDRAM; or: 32 or 64 MB ofQDRII+ SRAM




TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

VIRTEX-6 FPGA

MODEL 73660

INTERFACES ONLY16

QDRII+SRAM8 MB


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

16 16

ConfigFLASH64 MB PCIe

to PCIBRIDGE

PCIto PCI

BRIDGE

PCIeto PCI

BRIDGE

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

200 MHz16-BIT A/D

16


DDR3 option 155

QDRII+ option 160

DDR3 option 165

RF In

RFXFORMR

200 MHz16-BIT A/D

16


40

From/To Other

XMC Module of

MODEL 74660LVDS

GTX

GTX


PCI/PCI-X BUSPCI/PCI-X BUS32/64-bit, 33/66 MHz32-bit, 33/66 MHz

4X

J2




40

LVDS


J3

VIRTEX-6 FPGA




Pentek, Inc.


➤ ➤ ➤ ➤ ➤ A/D Converter StageThe front end accepts four or eight

full-scale analog HF or IF inputs on frontpanel SSMC connectors at +8 dBm into50 ohms with transformer coupling intofour or eight Texas Instruments ADS5485200 MHz, 16-bit A/D converters.






Multiple boards can be driven from theLVPECL bus master, supporting synchro-nous sampling and sync functions acrossall connected boards.


four or eight independent memory bankswhich can be configured with all QDRII+SRAM, DDR3 SDRAM, or as combinationof two banks of each type of memory.

Each QDRII+ SRAM bank can be up to8 MB deep and is an integral part of theboard’s DMA capabilities, providingFIFO memory space for creating DMApackets. For applications requiring deepermemory resources, DDR3 SDRAM bankscan each be up to 512 MB deep. Built-inmemory functions include multichannelA/D data capture, tagging and streaming.




A/D Acquisition IP ModulesThese models feature four

or eight A/D Acquisition IPModules for easily capturingand moving data. Each IPmodule can receive data fromany of four A/Ds or a testsignal generator

Each IP module has an asso-ciated memory bank for bufferingdata in FIFO mode or for storingdata in transient capture mode.All memory banks are supportedwith DMA engines for easilymoving A/D data through thePCIe interface. These powerfullinked-list DMA engines arecapable of a unique AcquisitionGate Driven mode. In this mode,the length of a transfer performedby a link definition need not beknown prior to data acquisition;rather, it is governed by thelength of the acquisition gate.This is extremely useful inapplications where an externalgate drives acquisition and theexact length of that gate is notknown or is likely to vary.

For each transfer, the DMAengine can automatically constructmetadata packets containingA/D channel ID, a sample-accu-rate time stamp and data lengthinformation. These actionssimplify the host processor’sjob of identifying and executingon the data.

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

PCIe FPGAI/O


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

4X 40


Pentek, Inc.



72660 4-Channel 200 MHz 16-bitA/D with Virtex-6 FPGA -6U cPCI


74660 8-Channel 200 MHz 16-bitA/D with two Virtex-6FPGAs - 6U cPCI

Options:








➤➤➤➤➤ SpecificationsModel 72660 or Model 73660: 4 A/DsModel 74660: 8 A/DsFront Panel Analog Signal Inputs (4 or 8)



Sample Clock Sources (1 or 2)On-board clock synthesizers





Field Programmable Gate Arrays (1 or 2)Standard: Xilinx Virtex-6 XC6VLX130TOptional: Xilinx Virtex-6 XC6VLX240Tor XC6VSX315T

Custom I/OOption -104 provides 20 LVDS pairsbetween the FPGA and the J2 connector,Model 73660; J3 connector, Model 72660;J3 and J5 connectors, Model 74660






Pentek, Inc.

4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - AMCModel 56660


family of high-performance AMC modulesbased on the Xilinx Virtex-6 FPGA. A multi-channel, high-speed data converter, it issuitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capture features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGAprocessing IP.

It includes four A/Ds and four banks ofmemory. In addition to supporting PCIExpress Gen. 2 as a native interface, theModel 56660 includes a front panelgeneral-purpose connector for application-specific I/O.



Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s analoginterfaces. The 56660 factory-installedfunctions include four A/D acquisition IPmodules.

IP modules for either DDR3 orQDRII+ memories, a controller for all dataclocking and synchronization functions, atest signal generator, and a PCIe interfacecomplete the factory-installed functions andenable the 56660 to operate as a completeturnkey solution without the need to developany FPGA IP.











multimodule synchronization■ PCI Express (Gen. 1 & 2)

interface up to x8■ AMC.1 compliant

■ IPMI 2.0 compliant MMC(Module ManagementController)


TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

16

QDRII+SRAM8 MB


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

200 MHz16-BIT A/D

16


DDR3 option 155

QDRII+ option 160

DDR3 option 165

RF In

RFXFORMR

200 MHz16-BIT A/D

16


VIRTEX-6 FPGA


40

LVDSGTX

FPGAGPIO(option 104)

x8 PCIe

8X

FrontPanel

AMCPorts 4 to 11

IPMICONTROLLER

RS-232

FrontPanel


Pentek, Inc.


➤➤➤➤➤ A/D Converter StageThe front end accepts four full-scale





A front panel 26-pin LVPECL Clock/Syncconnector allows multiple modules to besynchronized. In the slave mode, it acceptsLVPECL inputs that drive the clock, syncand gate signals. In the master mode, the

LVPECL bus can drive the timing signalsfor synchronizing multiple modules.




Each QDRII+ SRAM bank can be up to8 MB deep and is an integral part of themodule’s DMA capabilities, providingFIFO memory space for creating DMApackets. For applications requiring deepermemory resources, DDR3 SDRAM bankscan each be up to 512 MB deep. Built-inmemory functions include multichannelA/D data capture, tagging and streaming.








PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 40


Pentek, Inc.



56660 4-Channel 200 MHz A/Dwith Virtex-6 FPGA - AMC

Options:









versions



















Pentek, Inc.

Model 71663 1100-Channel GSM Channelizer with Quad A/D - XMC


family of high-performance XMC modulesbased on the Xilinx Virtex-6 FPGA. Thisfour-channel, high-speed A/D converterwith 1100 GSM DDCs (digitaldownconverters) accepts IF signals from anRF tuner. It is ideal for capturing all trans-mit and receive signals in both upper andlower GSM bands.

It includes four A/Ds and four banks ofDDCs. Channelizer data and control signalsflow across the PCI Express Gen. 2 nativeinterface, providing peak rates of up to4 GB/sec.

The Cobalt ArchitectureThe Pentek Cobalt architecture connects

all of the board’s data converters, digitalinterfaces, clocks and timing signals to theFPGA. Here, four factory-installed GSMchannelizer IP cores are supported withadditional FPGA functions includingpacket formation, four DMA controllers,PCIe interface, gating, and triggering.

The 71663 is a complete, full-featuredsubsystem, ready to use with no additionalFPGA develpment required.

A/D Converter StageThe front end accepts four analog IF

inputs on front panel SSMC connectors withtransformer coupling into four Texas Instru-ments ADS5485 200 MHz, 16-bit A/Dconverters clocked at 180 MHz.

The digital outputs are delivered intothe FPGA for GSM channelizer signal pro-cessing.


ing and synchronization required by theA/D converters. It includes a clock, twosync and two gate or trigger signals. Anon-board clock generator accepts an exter-nal 180 MHz sample clock from the frontpanel SSMC connector. This clock can beused directly by the A/D or divided by abuilt-in clock synthesizer circuit. In an alter-nate mode, the sample clock can be sourcedfrom an on-board 180 MHz voltage-controlled crystal oscillator. In this mode,the front panel SSMC connector can beused to provide a reference clock, typically10 MHz, for synchronizing the internaloscillator.

A front panel 26-pin LVPECL Clock/Syncconnector allows multiple modules to besynchronized. In the slave mode, it acceptsLVPECL inputs that drive the clock, syncand gate signals. In the master mode, theLVPECL bus can drive the timing signalsfor synchronizing multiple modules.

Multiple 71663’s can be driven from theLVPECL bus master, supporting synchronoussampling and sync functions across allconnected modules.

GSM Channelizer CoresThe 71663 contains four powerful GSM

channelizer cores, two with 375 DDCs andtwo with 175 DDCs. Flexible input rout-ing allows the independent, non-blockingassignment of any A/D converter to serveas the input source for any of the four GSMchannelizers. ➤

Features■ Complete GSM channelizer

with analog IF interface

■ Four 180 MHz 16-bit A/Ds■ Two banks of 375 DDCs for

upper GSM band■ Two banks of 175 DDCs for

lower GSM band

■ Sample clock synchronizationto an external systemreference


■ PCI Express Gen. 2 x8

SUPERCHANNELENGINE

PACKETGENERATOR

FIFO &LINKED-LISTDMA ENGINE

GEN 2x8 PCIe

INTERFACE

x4 or x8PCIe

SUPERCHANNELENGINE

SUPERCHANNELENGINE

SUPERCHANNELENGINE

PACKETGENERATOR

PACKETGENERATOR

PACKETGENERATOR




Sample /Ref Clock In

MUX

180 MHz16-BIT A/D

Ch ARF In GSM

CHANNELIZER375 CHANNELS

MUX

MUX

MUX

Ch BRF In

Ch CRF In

Ch DRF In

180 MHzVCXO

CLOCK, SYNC& TRIGGER

GENERATOR

Clock /SyncBus

GSMCHANNELIZER375 CHANNELS



180 MHz16-BIT A/D

180 MHz16-BIT A/D

180 MHz16-BIT A/D



Pentek, Inc.


As a result, the two 375-channel bankseach deliver 94 superchannels, while thetwo 175-channel banks each deliver 44superchannels. The last superchannel ineach bank contains only three DDC channels.

A superchannel enable mask word con-taining one enable bit for each superchannelallows independent selection of whichsuperchannel samples are delivered acrossPCIe. There are four superchannel maskwords, one for each bank.

Superchannel Packets and Headers Superchannel packets are formed by

appending enabled superchannel samplessequentially from each bank. Once complete,a unique superchannel packet header isinserted at the beginning of each packetfor identification.

The header contains a time stamp, asequential packet count, the number ofenabled superchannels, the DMA channelidentifier, and other information. By inspect-ing the header, the remaining superchanneldata “payload” samples can be identifiedand recovered by the host.


standard interface fully compliant withPCI Express Gen. 2 bus specifications.Supporting PCIe links up to x8, the inter-face includes four DMA controllers forefficient packet transfers from each of thefour DDC banks to system memory.

The PCIe interface is also used as theprogramming interface for all status andcontrol between the 71663 and host. ➤

➤ The 375-channel cores are designed forthe upper GSM bands which contain two75 MHz bands, one for uplink and one fordownlink. The 175-channel cores are de-signed for the lower GSM band and handletwo 35 MHz bands, one for uplink and onefor downlink.

Before connection to the 71663, theseGSM RF bands must first be separatelydownconverted to an IF frequency centeredat 45 MHz, 135 MHz or 225 MHz usingan external analog RF tuner.

These IF signals are then digitized bythe 71663 A/Ds at 180 MS/sec in the first,second, or third Nyquist zones, respectively.In order to prevent aliasing, careful filteringmust ensure that no signals appear in adja-cent Nyquist zones.

Each of the channelizers is designed toaccept real digital samples of the IF signalfrom the A/D converter. The first stage ofthe GSM channelizer is a complex mixerthat shifts the center frequency of the IFsignal (45, 135 or 225 MHz) to 0 Hz, therebyproducing complex I+Q samples.

The DDCs split the IF input into either175 or 375 parallel DDC baseband chan-nels, equally spaced at 200 kHz. The DDCoutput sample rate is resampled to pre-cisely 180 MHz*13/2160, or approximately1.08333 MHz. This is four times the GSMsymbol rate of 270.666 kSymbols/sec. Theoutput passband of each DDC channel isnominally 160 kHz, with filter characteris-tics fully defined in the channel responsechart in the specifications.

Channelizer Output FormattingAll 1100 DDCs generate parallel, com-

plex output sample streams. At a samplerate of 1.08333 MS/sec, this represents anaggregate output rate of 9.533 GB/sec,greatly exceeding the 4 GB/sec peak rateof PCIe Gen 2 x8 interface.

To mitigate this situation, every fourDDC channels are frequency-mutliplexedinto a single “superchannel”. This is allowedbecause of the 4x oversampling, and resultsin a reduction of the aggregate PCIe trafficby a factor of 4 to 2.383 GB/sec, which isnow well within the capability of the PCIeGen 2 x8 interface.

During superchannel formation, the24-bit I + 24-bit Q output samples from fourDDCs are summed to superchannel sampleswith 26-bit I + 26-bit Q.


Pentek, Inc.


➤ SpecificationsFront Panel Analog Signal Inputs




Clock SynthesizerClock Source: Selectable from on-board180 MHz VCXO, front panel externalclock or LVPECL timing busSynchronization: VCXO can be lockedto an external 10 MHz system reference

External ClockType: Front panel female SSMC con-nector, sine wave, 0 to +10 dBm, 50 ohms,AC-coupled, accepts 180 MHz sampleclock or 10 MHz system reference


External Trigger InputType: Front panel female SSMCconnector, LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS

GSM Channel BanksDDCs per bank: two banks of 175 DDCsand two banks of 375 DDCsOverall bandwidth per bank: 35 MHz& 75 MHz for 175- & 375-channel banksIF (Center) Freq: 45, 135 or 225 MHz


71663 1100-Channel GSMChannelizer with QuadA/D - XMC


versions

Model Description


DDC ChannelsChannel Spacing: 200 kHz, fixedDDC Center Freqs: IF Freq ± k * 200 kHz,where k = 0 to 87, or 0 to 187DDC Channel Filter Characteristics

< 0.1 dB passband flatness across ±80 kHz from center (160 kHz BW)> 18 dB attenuation at ±100 kHz> 78 dB attenuation at ±170 kHz> 83 dB attenuation at ±600 kHz> 93 dB attenuation at ±800 KHz> 96 dB attenuation at > ±3 MHz

DDC Output Rate ƒs: Resampled to180 MHz*13/2160 = 1.0833333 MS/secDDC Data Output Format:24 bits I + 24 bits Q

SuperchannelsContent: Four consecutive DDC channelsare frequency-offset from each other andthen summed togetherFrequency Offsets for each DDC:First: -ƒs/4 (-270.8333 kHz)Second: 0 HzThird: +ƒs/4 (+270.8333 kHz)Fourth: +ƒs/2 (+541.666 kHz)Superchannel Sample Rate: ƒsSuperchannel Output Format:26 bits I + 26 bits QNumber of Superchannels per Bank:175-Channel banks: 44; 375-Channelbanks: 94

Field Programmable Gate Array: XilinxVirtex-6 XC6VSX315T

PCI Express InterfacePCI Express Bus: Gen. 2 x8






Pentek, Inc.

Model 78663 1100-Channel GSM Channelizer with Quad A/D - x8 PCIe


family of high-performance PCIe boardsbased on the Xilinx Virtex-6 FPGA. This four-channel, high-speed A/D converter with1100 GSM DDCs (digital downconverters)accepts IF signals from an RF tuner. It isideal for capturing all transmit and receivesignals in both upper and lower GSMbands.










A front panel 26-pin LVPECL Clock/Syncconnector allows multiple boards to besynchronized. In the slave mode, it acceptsLVPECL inputs that drive the clock, syncand gate signals. In the master mode, theLVPECL bus can drive the timing signalsfor synchronizing multiple boards.

Multiple 78663’s can be driven from theLVPECL bus master, supporting synchronoussampling and sync functions across allconnected boards.







lower GSM band■ Sample clock synchronization

to an external systemreference



SUPERCHANNELENGINE

PACKETGENERATOR


GEN 2x8 PCIe

INTERFACE

x4 or x8PCIe

SUPERCHANNELENGINE

SUPERCHANNELENGINE

SUPERCHANNELENGINE

PACKETGENERATOR

PACKETGENERATOR

PACKETGENERATOR





MUX

180 MHz16-BIT A/D

Ch ARF In GSM


MUX

MUX

MUX

Ch BRF In

Ch CRF In

Ch DRF In

180 MHzVCXO


GENERATOR

Clock /SyncBus




180 MHz16-BIT A/D

180 MHz16-BIT A/D

180 MHz16-BIT A/D



Pentek, Inc.



A superchannel enable mask word con-taining one enable bit for each superchannelallows independent selection of whichsuperchannel samples are delivered acrossthe PCIe. There are four superchannel maskwords, one for each bank.











The DDCs split the IF input into either175 or 375 parallel DDC baseband channels,equally spaced at 200 kHz. The DDC out-put sample rate is resampled to precisely180 MHz*13/2160, or approximately1.08333 MHz. This is four times the GSMsymbol rate of 270.666 kSymbols/sec. Theoutput passband of each DDC channel isnominally 160 kHz, with filter characteris-tics fully defined in the channel responsechart in the specifications.






Pentek, Inc.












78663 1100-Channel GSMChannelizer with QuadA/D- PCIe

Model Description









Size: Half length PCIe card, 4.38 x 7.13 in.



http://pentek.com/products/Detail.cfm?Model=8266


Pentek, Inc.

Model 53663 1100-Channel GSM Channelizer with Quad A/D - VPX


family of high-performance VPX boardsbased on the Xilinx Virtex-6 FPGA. This four-channel, high-speed A/D converter with1100 GSM DDCs (digital downconverters)accepts IF signals from an RF tuner. It isideal for capturing all transmit and receivesignals in both upper and lower GSMbands.


















lower GSM band■ Sample clock synchronization to


multiboard synchronization■ PCI Express Gen. 2 x8■ 3U VPX form factor provides

a compact, rugged platform

SUPERCHANNELENGINE

PACKETGENERATOR


GEN 2x8 PCIe

INTERFACE

SUPERCHANNELENGINE

SUPERCHANNELENGINE

SUPERCHANNELENGINE

PACKETGENERATOR

PACKETGENERATOR

PACKETGENERATOR





MUX

180 MHz16-BIT A/D

Ch ARF In GSM


MUX

MUX

MUX

Ch BRF In

Ch CRF In

Ch DRF In

180 MHzVCXO


GENERATOR

Clock /SyncBus




180 MHz16-BIT A/D

180 MHz16-BIT A/D

180 MHz16-BIT A/D


VPX BACKPLANE

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

8X

x8PCIe

Model 53663 Commercial (left)and rugged version


Pentek, Inc.









The PCIe interface is also used as theprogramming interface for all status andcontrol between the 53663 and host.


switching configuration. A fabric-transpar-ent crossbar switch bridges numerousinterfaces and components on the boardusing gigabit serial data paths with nolatency. Programmable signal input equal-ization and output pre-emphasis settingsenable optimization. Data paths can beselected as single (1X) lanes, or groups offour lanes (4X). ➤











Pentek, Inc.



53663 1100-Channel GSMChannelizer with QuadA/D - VPX


versions

Model Description











DDC ChannelsChannel Spacing: 200 kHz, fixedDDC Center Freqs: IF Freq ± k * 200 kHz,where k = 0 to 87, or 0 to 187DDC Channel Filter Characteristics:







Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)


products: the 52xxx and the 53xxx. For moreinformation on a 53xxx product, pleaserefer to the product datasheet. The tablebelow provides a comparison of their mainfeatures.


52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


Yes

PCIe width x4 x4 or x8

20pairsonVPXP224pairsonVPXP2

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.



family of high-performance VPX boardsbased on the Xilinx Virtex-6 FPGA. This four-channel, high-speed A/D converter with1100 GSM DDCs (digital downconverters)accepts IF signals from an RF tuner. It isideal for capturing all transmit and receivesignals in both upper and lower GSMbands.


















lower GSM band■ Sample clock synchronization to


multiboard synchronization■ PCI Express Gen. 2 x4■ 3U VPX form factor provides

a compact, rugged platform

SUPERCHANNELENGINE

PACKETGENERATOR


GEN 2x4 PCIe

INTERFACE

SUPERCHANNELENGINE

SUPERCHANNELENGINE

SUPERCHANNELENGINE

PACKETGENERATOR

PACKETGENERATOR

PACKETGENERATOR





MUX

180 MHz16-BIT A/D

Ch ARF In GSM


MUX

MUX

MUX

Ch BRF In

Ch CRF In

Ch DRF In

180 MHzVCXO


GENERATOR

Clock /SyncBus




180 MHz16-BIT A/D

180 MHz16-BIT A/D

180 MHz16-BIT A/D

Gate / Trigger /Sync / PPS VPX BACKPLANE

VPX-P1

4X

x4PCIe

Model 52663 Commercial (left)and rugged version


Pentek, Inc.










➤ The 375-channel cores are designed forthe upper GSM bands which contain two75 MHz bands, one for uplink and one fordownlink. The 175-channel cores aredesigned for the lower GSM band andhandle two 35 MHz bands, one for uplinkand one for downlink.







To mitigate this situation, every fourDDC channels are frequency-mutliplexedinto a single “superchannel”. This is allowedbecause of the 4x oversampling, and resultsin a reduction of the aggregate PCIe trafficby a factor of 4 to 2.383 GB/sec, which isslightly above the capability of the PCIeGen 2 x4 interface.



Pentek, Inc.



52663 1100-Channel GSMChannelizer with QuadA/D - VPX


versions

Model Description











DDC ChannelsChannel Spacing: 200 kHz, fixedDDC Center Freqs: IF Freq ± k * 200 kHz,where k = 0 to 87, or 0 to 187DDC Channel Filter Characteristics:







Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)


products: the 52xxx and the 53xxx. For moreinformation on a 53xxx product, pleaserefer to the product datasheet. The tablebelow provides a comparison of their mainfeatures.


52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


Yes



Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.

1100- or 2200-Channel GSM Channelizer withQuad or Octal A/D - 6U OpenVPX

Models57663 & 58663

General InformationModels 57663 and 58663 are members of

the Cobalt® family of high-performance 6UOpenVPX boards based on the XilinxVirtex-6 FPGA. They consist of one ortwo Model 71663 XMC modules mountedon a VPX carrier board.


This quad or octal, high-speed A/Dconverter with 1100 or 2200 GSM DDCs(digital downconverters) accepts IF signalsfrom an RF tuner. It is ideal for capturingall transmit and receive signals in bothupper and lower GSM bands.


all of the board’s data converters, digitalinterfaces, clocks and timing signals to theFPGA. Here, four or eight factory-installedGSM channelizer IP cores are supportedwith additional FPGA functions includingpacket formation, four or eight DMAcontrollers, PCIe interface, gating, andtriggering.

These models are complete, full-featuredsubsystems, ready to use with no additionalFPGA develpment required.

A/D Converter StageThe front end accepts four or eight analog

IF inputs on front panel SSMC connectors

with transformer coupling into four or eightTexas Instruments ADS5485 200 MHz,16-bit A/D converters clocked at 180 MHz.


Clocking and SynchronizationThe internal timing bus provides all tim-

ing and synchronization required by theA/D converters. It includes clock, sync andgate or trigger signals. One or two on-boardclock generators accept external 180 MHzsample clocks from the front panel SSMCconnectors. The clocks can be used directlyby the A/Ds or divided by a built-in clocksynthesizer circuit. In an alternate mode,the sample clock can be sourced from anon-board 180 MHz voltage-controlled crys-tal oscillator. In this mode, the front panelSSMC connector can be used to provide areference clock, typically 10 MHz, for syn-chronizing the internal oscillator.

A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards tobe synchronized. In the slave mode, it acceptsLVPECL inputs that drive the clock, syncand gate signals. In the master mode, theLVPECL bus can drive the timing signals forsynchronizing multiple boards.

Multiple boards can be driven from theLVPECL bus master, supporting synchronoussampling and sync functions across allconnected boards. ➤

New!

New!

New!

New!

New!

Features■ Four or eight 180 MHz 16-bit

A/Ds■ Two or four banks of 375

DDCs for upper GSM band■ Two or four banks of 175

DDCs for lower GSM band■ PCI Express (Gen. 1 & 2)

interface up to x4■ LVPECL clock/sync bus for

multiboard synchronization■ Ruggedized and conduction-


SUPERCHANNELENGINE

PACKETGENERATOR


GEN 2x4 PCIe

INTERFACE

SUPERCHANNELENGINE

SUPERCHANNELENGINE

SUPERCHANNELENGINE

PACKETGENERATOR

PACKETGENERATOR

PACKETGENERATOR





MUX

180 MHz16-BIT A/D

Ch ARF In GSM


MUX

MUX

MUX

Ch BRF In

Ch CRF In

Ch DRF In

180 MHzVCXO


GENERATOR

Clock /SyncBus




180 MHz16-BIT A/D

180 MHz16-BIT A/D

180 MHz16-BIT A/D


VPX BACKPLANE

4X

PCIeGen. 2 x4

PCIeGen. 2 x4

VPX-P1

PCIe-to PCIeSWITCH

From/To

Other XMC

Module of

Model 58663




PCIe-to-PCIe Switch

Model 58663


Pentek, Inc.


Models57663 & 58663

To mitigate this situation, every fourDDC channels are frequency-mutliplexedinto a single “superchannel”. This is allowedbecause of the 4x over sampling, and resultsin a reduction of the aggregate traffic by afactor of 4 to 2.383 GB/sec.

During superchannel formation, the24-bit I + 24-bit Q output samples fromfour DDCs are summed to superchannelsamples with 26-bits I + 26-bits Q.

As a result, the two 375-channel bankseach deliver 94 superchannels, while thetwo 175-channel banks each deliver 44superchannels. The last superchannel ineach bank only contains three DDC channels.

A superchannel enable mask word con-taining one enable bit for each superchannelallows independent selection of whichsuperchannel samples are delivered acrossthe PCI-X bus. There are four superchannelmask words, one for each bank.


appending enabled superchannel samplessequentially from each bank. Once com-pete, a unique superchannel packet headeris inserted at the beginning of each packetfor identification.



standard interface fully compliant with PCIExpress Gen. 1 and 2 bus specifications.Supporting PCIe links up to x4, the inter-face includes multiple DMA controllersfor efficient transfers to and from the board.

The PCIe interface is also used as theprogramming interface for all status andcontrol between these models and host. ➤

➤➤➤➤➤ GSM Channelizer CoresThese models contain four or eight

powerful GSM channelizer cores, two orfour with 375 DDCs and two or four with175 DDCs. Flexible input routing allowsthe independent, non-blocking assignmentof any A/D converter to serve as the inputsource for any of four GSM channelizers.

The 375-channel cores are designed forthe upper GSM bands which contain two75 MHz bands, one for uplink and one fordownlink. The 175-channel cores aredesigned for the lower GSM band andhandle two 35 MHz bands, one for uplinkand one for downlink.

Before connection to these models, theGSM RF bands must first be separatelydownconverted to an IF frequency cen-tered at 45 MHz, 135 MHz or 225 MHzusing an external analog RF tuner.

These IF signals are then digtitized bythe four or eight A/Ds at 180 MS/sec inthe first, second, or third Nyquist zones,respectively. In order to prevent aliasing,careful filtering must insure that no signalsappear in adjacent Nyquist zones.

Each of the channelizers is designed toaccept real digital samples of the IF signalfrom the A/D converter. The first stage ofthe GSM channelizer is a complex mixerthat shifts the center frequency of the IFsignal (45, 135 or 225 MHz) to 0 Hz, produc-ing complex I+Q samples.

The DDCs split the IF input into either175 or 375 parallel DDC baseband channels,equally spaced at 200 kHz. The DDC out-put sample rate is resampled to precisely180 MHz*13/2160, or approximately1.08333 MHz. This is four times the GSMsymbol rate of 270.666 kSymbols/sec. Theoutput passband of each DDC channel isnominally 160 kHz, with filter characteris-tics fully defined in the channel responsechart in the specifications.



A/D Converters (4 or 8)


Pentek, Inc.


Models57663 & 58663


57663 1100-Channel GSMChannelizer with QuadA/D - 6U VPX

58663 2200-Channel GSMChannelizer with OctalA/D - 6U VPX


versions

Model Description


SpecificationsModel 57663: 4 A/Ds, 1100 ChannelsModel 58663: 8 A/Ds, 2200 ChannelsFront Panel Analog Signal Inputs (4 or 8)



Sample Clock Sources (1 or 2)On-board clock synthesizer

Clock Synthesizers (1 or 2)Clock Source: Selectable from on-board180 MHz VCXO, front panel externalclock or LVPECL timing busSynchronization: VCXO can be lockedto an external 10 MHz system reference

External Clocks (1 or 2)Type: Front panel female SSMC con-nector, sine wave, 0 to +10 dBm, 50ohms, AC-coupled, accepts 180 MHzsample clock or 10 MHz system refer-ence


External Trigger Inputs (1 or 2)Type: Front panel female SSMC con-nector, LVTTLFunction: Programmable functions in-clude: trigger, gate, sync and PPS

GSM Channel Banks (1 or 2)DDCs per bank: two banks of 175DDCs and two banks of 375 DDCsOverall bandwidth per bank: 35 MHz& 75 MHz for 175- & 375-channel banksIF (Center) Freq: 45, 135 or 225 MHz





Field Programmable Gate Arrays (1 or 2)Xilinx Virtex-6 XC6VSX315T

PCI-Express InterfacePCI Express Bus: Gen. 1 or 2: x4


Size: 3.937 in. x 6.717 in. (100 mm x 170.6mm)




Pentek, Inc.

1100- or 2200-Channel GSM Channelizer withQuad or Octal A/D - cPCI

Models 72663, 73663and 74663


members of the Cobalt® family of high-per-formance CompactPCI boards based onthe Xilinx Virtex-6 FPGA. They consist ofone or two Model 71663 XMC modulesmounted on a cPCI carrier board.


This quad or octal, high-speed A/Dconverter with 1100 or 2200 GSM DDCs(digital downconverters) accepts IF signalsfrom an RF tuner. It is ideal for capturingall transmit and receive signals in both up-per and lower GSM bands.


all of the board’s data converters, digitalinterfaces, clocks and timing signals to theFPGA. Here, four or eight factory-installedGSM channelizer IP cores are supportedwith additional FPGA functions includingpacket formation, four or eight DMAcontrollers, PCIe interface, gating, andtriggering.

These models are complete, full-featuredsubsystems, ready to use with no additionalFPGA develpment required.

A/D Converter StageThe front end accepts four or eight analog

IF inputs on front panel SSMC connectorswith transformer coupling into four or eight

Texas Instruments ADS5485 200 MHz,16-bit A/D converters clocked at 180 MHz.


Clocking and SynchronizationThe internal timing bus provides all tim-

ing and synchronization required by theA/D converters. It includes clock, sync andgate or trigger signals. One or two on-boardclock generators accept external 180 MHzsample clocks from the front panel SSMCconnectors. The clocks can be used directlyby the A/Ds or divided by a built-in clocksynthesizer circuit. In an alternate mode,the sample clock can be sourced from anon-board 180 MHz voltage-controlled crys-tal oscillator. In this mode, the front panelSSMC connector can be used to provide areference clock, typically 10 MHz, for syn-chronizing the internal oscillator.

A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards tobe synchronized. In the slave mode, it ac-cepts LVPECL inputs that drive the clock,sync and gate signals. In the master mode,the LVPECL bus can drive the timing signalsfor synchronizing multiple boards.

Multiple boards can be driven from theLVPECL bus master, supporting synchronoussampling and sync functions across allconnected boards. ➤


with analog IF interface■ Four or eight 180 MHz 16-bit

A/Ds■ Two or four banks of 375

DDCs for upper GSM band■ Two or four banks of 175

DDCs for lower GSM band■ Sample clock synchronization to


multiboard synchronization

SUPERCHANNELENGINE

PACKETGENERATOR


GEN 2x4 PCIe

INTERFACE

SUPERCHANNELENGINE

SUPERCHANNELENGINE

SUPERCHANNELENGINE

PACKETGENERATOR

PACKETGENERATOR

PACKETGENERATOR





MUX

180 MHz16-BIT A/D

Ch ARF In GSM


MUX

MUX

MUX

Ch BRF In

Ch CRF In

Ch DRF In

180 MHzVCXO


GENERATOR

Clock /SyncBus




180 MHz16-BIT A/D

180 MHz16-BIT A/D

180 MHz16-BIT A/D

Gate / Trigger /Sync / PPS PCIe

to PCIBRIDGE

PCIto PCI

BRIDGE

From/To Other

XMC Module of

MODEL 74663

PCI/PCI-X BUS

32/64-bit, 33/66 MHz

4X

GEN 2 x4 PCIe

INTERFACE

MODEL 73663 INTERFACE ONLY

PCIeto PCI

BRIDGE

PCI/PCI-X BUS

32-bit, 33/66 MHz






Pentek, Inc.


Models 72663, 73663and 74663

in a reduction of the aggregate traffic by afactor of 4 to 2.383 GB/sec.

During superchannel formation, the24-bit I + 24-bit Q output samples fromfour DDCs are summed to superchannelsamples with 26-bits I + 26-bits Q.

As a result, the two 375-channel bankseach deliver 94 superchannels, while thetwo 175-channel banks each deliver 44superchannels. The last superchannel ineach bank only contains three DDC channels.

A superchannel enable mask word con-taining one enable bit for each superchannelallows independent selection of whichsuperchannel samples are delivered acrossthe PCI-X bus. There are four superchannelmask words, one for each bank.


appending enabled superchannel samplessequentially from each bank. Once com-pete, a unique superchannel packet headeris inserted at the beginning of each packetfor identification.




The PCI-X interface is also used as theprogramming interface for all status andcontrol between these models and host. ➤

➤➤➤➤➤ GSM Channelizer CoresThese models contain four or eight

powerful GSM channelizer cores, two orfour with 375 DDCs and two or four with175 DDCs. Flexible input routing allowsthe independent, non-blocking assignmentof any A/D converter to serve as the inputsource for any of four GSM channelizers.

The 375-channel cores are designed forthe upper GSM bands which contain two75 MHz bands, one for uplink and one fordownlink. The 175-channel cores are de-signed for the lower GSM band and handletwo 35 MHz bands, one for uplink and onefor downlink.

Before connection to these models, theGSM RF bands must first be separatelydownconverted to an IF frequency cen-tered at 45 MHz, 135 MHz or 225 MHzusing an external analog RF tuner.

These IF signals are then digtitized bythe four or eight A/Ds at 180 MS/sec inthe first, second, or third Nyquist zones,respectively. In order to prevent aliasing,careful filtering must insure that no signalsappear in adjacent Nyquist zones.

Each of the channelizers is designed toaccept real digital samples of the IF signalfrom the A/D converter. The first stage ofthe GSM channelizer is a complex mixerthat shifts the center frequency of the IFsignal (45, 135 or 225 MHz) to 0 Hz, pro-ducing complex I+Q samples.

The DDCs split the IF input into either175 or 375 parallel DDC baseband chan-nels, equally spaced at 200 kHz. The DDCoutput sample rate is resampled to precisely180 MHz*13/2160, or approximately1.08333 MHz. This is four times the GSMsymbol rate of 270.666 kSymbols/sec. Theoutput passband of each DDC channel isnominally 160 kHz, with filter characteris-tics fully defined in the channel responsechart in the specifications.



To mitigate this situation, every fourDDC channels are frequency-mutliplexedinto a single “superchannel”. This is allowedbecause of the 4x over sampling, and results


Pentek, Inc.


Models 72663, 73663and 74663

SpecificationsModel 72663 or Model 73663: 4 A/DsModel 74663: 8 A/DsFront Panel Analog Signal Inputs (4 or 8)



Sample Clock Sources (1 or 2)On-board clock synthesizer

Clock Synthesizers (1 or 2)Clock Source: Selectable from on-board180 MHz VCXO, front panel externalclock or LVPECL timing busSynchronization: VCXO can be lockedto an external 10 MHz system reference

External Clocks (1 or 2)Type: Front panel female SSMC con-nector, sine wave, 0 to +10 dBm, 50ohms, AC-coupled, accepts 180 MHzsample clock or 10 MHz system refer-ence


External Trigger Inputs (1 or 2)Type: Front panel female SSMC connec-tor, LVTTLFunction: Programmable functions in-clude: trigger, gate, sync and PPS

GSM Channel Banks (1 or 2)DDCs per bank: two banks of 175DDCs and two banks of 375 DDCsOverall bandwidth per bank: 35 MHz& 75 MHz for 175- & 375-channel banksIF (Center) Freq: 45, 135 or 225 MHz





Field Programmable Gate Arrays (1 or 2)Xilinx Virtex-6 XC6VSX315T





72663 1100-Channel GSMChannelizer with QuadA/D - 6U cPCI

73663 1100-Channel GSMChannelizer with QuadA/D - 3U cPCI

74663 2200-Channel GSMChannelizer with OctalA/D - 6U cPCI


Pentek, Inc.

Model 56663 1100-Channel GSM Channelizer with Quad A/D - AMC


family of high-performance AMC modulesbased on the Xilinx Virtex-6 FPGA. This four-channel, high-speed A/D converter with1100 GSM DDCs (digital downconverters)accepts IF signals from an RF tuner. It isideal for capturing all transmit and receivesignals in both upper and lower GSMbands.















with analog IF interface■ Four 180 MHz 16-bit A/Ds

■ Two banks of 375 DDCs forupper GSM band

■ Two banks of 175 DDCs forlower GSM band


■ LVPECL clock/sync bus formultimodule synchronization




SUPERCHANNELENGINE

PACKETGENERATOR


GEN 2x8 PCIe

INTERFACE

SUPERCHANNELENGINE

SUPERCHANNELENGINE

SUPERCHANNELENGINE

PACKETGENERATOR

PACKETGENERATOR

PACKETGENERATOR





MUX

180 MHz16-BIT A/D

Ch ARF In GSM


MUX

MUX

MUX

Ch BRF In

Ch CRF In

Ch DRF In

180 MHzVCXO


GENERATOR

Clock /SyncBus




180 MHz16-BIT A/D

180 MHz16-BIT A/D

180 MHz16-BIT A/D


x8PCIe

FrontPanel

AMCPorts

4 to 11

IPMICONTROLLER

RS-232


Pentek, Inc.









The PCIe interface is also used as theprogramming interface for all status andcontrol between the 56663 and host.













Pentek, Inc.



56663 1100-Channel GSMChannelizer with QuadA/D - AMC


versions




















Pentek, Inc.

4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - XMCModel 71670


family of high performance XMC modulesbased on the Xilinx Virtex-6 FPGA. This4-channel, high-speed data converter issuitable for connection to transmit HF or IFports of a communications or radar system.Its built-in data playback features offer anideal turnkey solution for demandingtransmit applications.

It includes four D/As, four digitalupconverters and four banks of memory.In addition to supporting PCI Express Gen. 2as a native interface, the Model 71670includes general purpose and gigabit serialconnectors for application-specific I/O .



Each member of the Cobalt family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces.The 71670 factory-installed functions includefour D/A waveform playback IP modules,to support waveform generation throughthe D/A converters. IP modules for DDR3SDRAM memories, a controller for alldata clocking and synchronization functions,

a test signal generator, and a PCIe interfacecomplete the factory-installed functionsand enable the 71670 to operate as a com-plete turnkey solution, without the needto develop any FPGA IP.






Option -105 installs the P16 XMC connec-tor with dual 4X gigabit links to the FPGAto support serial protocols. ➤



LXT and SXT FPGAs■ Four 1.25 GHz 16-bit D/As■ Four digital upconverters

■ Programmable output levels■ 250 MHz max. output

bandwidth■ 2 GB of DDR3 SDRAM■ Sample clock synchronization to






TIMING BUSGENERATOR


VCXO

16


16

ConfigFLASH64 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

1616

DDR3SDRAM512 MB

DDR3SDRAM512 MB


Clock/SyncBus A

40

GigabitSerial I/O

(option 105)

4X

GTX

4X

GTX LVDSGTX

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

16 16

Gate InSync In

�Sync Bus A

Gate InSync In

�Sync Bus B

Trigger In

Clock/SyncBus B

VIRTEX-6 FPGA



Pentek, Inc.


➤➤➤➤➤ Digital Upconverter and D/A StageTwo Texas Instruments DAC3484s pro-

vide four DUC (digital upconverter) andD/A channels. Each channel accepts a base-band real or complex data stream from theFPGA and provides that input to theupconvert, interpolate and D/A stage.

When operating as a DUC, it interpolatesand translates real or complex basebandinput signals to a user selectable IF centerfrequency. It delivers real or quadrature(I+Q) analog outputs to a 16-bit D/Aconverter.

If translation is disabled, each D/A actsas an interpolating 16-bit D/A with outputsampling rates up to 1.25 GHz. In bothmodes, the D/A provides interpolation factorsof 2x, 4x, 8x and 16x. Analog output is throughfour front panel SSMC connectors.


required D/A clocking. The bus includes aclock, sync and a gate or trigger signal. Anon-board clock generator receives a sampleclock either from the front panel SSMC con-nector or from an on-board programmableVCXO (Voltage-Controlled Crystal Oscillator).In this latter mode, the front panel SSMCconnector can be used to provide a 10 MHzreference clock to phase-lock the VCXO.Either clock source (front panel or VCXO)can be used directly or can be divided by2, 4, 8, or 16 to provide lower frequencyD/A clocks.

A pair of front panel µSync connectorsallows multiple modules to be synchro-nized. They accept CML inputs that drivethe board’s sync and trigger/gate signals.The Pentek Models 7192 or 9192 CobaltSynchronizers can drive multiple 71670µSync connectors enabling large, multi-channel synchronous configurations.


independent memory banks of DDR3SDRAM. Each bank is 512 MB deep and isan integral part of the module’s DMA andwaveform playback capabilities. Waveformtables can be loaded into the memorieswith playback managed by the linked listcontrollers.



VITA 42.0 XMC specification. Two connec-tors each provide dual 4X links or a single8X link with up to a 3.125 GHz bit clock.With dual XMC connectors, the 71670 sup-ports x8 PCIe on the first XMC connectorleaving the second connector free to supportuser-installed transfer protocols specific tothe target application. ➤

D/A Waveform Playback IPModule

The Model 71670 factory-installed functions include asophisticated D/A WaveformPlayback IP module. Fourlinked list controllers supportwaveform generation to thefour D/As from tables stored ineither on-board memory or off-board host memory.

Data for Channel 1 andChannel 2 are interleaved fordelivery to a dual channel D/Adevice. For this reason, theymust share a common trigger/gate, sample rate, interpolationfactor, and other parameters.The same rules apply to Chan-nel 3 and Channel 4.Parameters including length ofwaveform, waveform repetition,etc. can be programmed for eachchannel.

Up to 64 individual linkentries for each D/A channelcan be chained together to cre-ate complex waveforms with aminimum of programming.

D/A

WAVEFORM

PLAYBACK

IP MODULE 1

toD/A Ch 1 & 2


FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40

D/A

WAVEFORM

PLAYBACK

IP MODULE 2

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 2

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 3

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 3

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 4

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 4

MEMORYCONTROL

TESTSIGNAL

GENERATOR

PCIe INTERFACE

DATAINTERLEAVER

16toD/A Ch 3 & 4

DATAINTERLEAVER

16


Pentek, Inc.



standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications. Thex8 lane interface includes multiple DMAcontrollers for efficient transfers to andfrom the module.

SpecificationsD/A Converters

Type: TI DAC3484Input Data Rate: 312.5 MHz max.Output Bandwidth: 250 MHz max.Output Sampling Rate: 1.25 GHz max.with interpolationInterpolation: 2x, 4x, 8x or 16xResolution: 16 bits

Front Panel Analog Signal OutputsQuantity: Four D/A outputsOutput Type: Transformer-coupled,front panel female SSMC connectorsFull Scale Output: Programmable from–20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p)in 16 stepsFull Scale Output Programming:1.0x(G+1)/16 Vp-p, where 4-bit integerG = 0 to 15

Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO or front panelexternal clockVCXO Frequency Ranges: 10 to 945 MHz,970 to 1134 MHz and 1213 to 1417 MHzSynchronization: VCXO can be phase-locked to an external 4 to 200 MHzsystem reference, typically 10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8, or16 for the D/A clock


71670 4-Channel 1.25 GHz D/Awith Virtex-6 FPGA - XMC

Options:










versions

Model Description


External ClockType: Front panel female SSMC connector,sine wave, 0 to +10 dBm, AC-coupled,50 ohms, accepts 10 to 500 MHz sampleclock or 5 or 10 MHz system reference

External Trigger InputType: Front panel female SSMC connectorFunction: Programmable functionsinclude: trigger, gate, sync and PPS


Field Programmable Gate ArrayStandard: Xilinx Virtex-6XC6VLX130T-2Optional: Xilinx Virtex-6XC6VLX240T-2 or XC6VSX315T-2

Custom I/OOption -104: Installs the PMC P14 con-nector with 20 LVDS pairs to the FPGAOption -105: Installs the XMC P16 con-nector configurable as two 4X or one 8Xgigabit serial links to the FPGA


PCI-Express InterfacePCI Express Bus: Gen. 1 or Gen 2:x4 or x8;






Pentek, Inc.

4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - x8 PCIeModel 78670


family of high performance PCIe boardsbased on the Xilinx Virtex-6 FPGA. This4-channel, high-speed data converter issuitable for connection to transmit HF or IFports of a communications or radar system.Its built-in data playback features offer anideal turnkey solution for demandingtransmit applications.

It includes four D/As, four digitalupconverters and four banks of memory.In addition to supporting PCI Express Gen. 2as a native interface, the Model 78670includes optional general purpose and gigabitserial connectors for application-specific I/O.



Each member of the Cobalt family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces.The 78670 factory-installed functions includefour D/A waveform playback IP modules,to support waveform generation throughthe D/A converters. IP modules for DDR3SDRAM memories, a controller for alldata clocking and synchronization functions,a test signal generator, and a PCIe interface

complete the factory-installed functionsand enable the 78670 to operate as a com-plete turnkey solution, without the needto develop any FPGA IP.

















TIMING BUSGENERATOR


VCXO

16


16

ConfigFLASH64 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

1616

DDR3SDRAM512 MB

DDR3SDRAM512 MB


Clock/SyncBus A

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

16 16

Gate InSync In

�Sync Bus A

Gate InSync In

�Sync Bus B

Trigger In

Clock/SyncBus B

40 4X

GTX

4X

GTXLVDS GTX

OptionalFPGAGPIO

OptionalSerialI/O

8X

68-pinHeader

x8 PCI Express

Dual 4XSerialConn

x8 PCIe

VIRTEX-6 FPGA



Pentek, Inc.







required D/A clocking. The bus includes aclock, sync and a gate or trigger signal. Anon-board clock generator receives a sampleclock either from the front panel SSMC con-nector or from an on-board programmableVCXO (Voltage-Controlled Crystal Oscillator).In this latter mode, the front panel SSMCconnector can be used to provide a 10 MHzreference clock to phase-lock the VCXO.Either clock source (front panel or VCXO)can be used directly or can be divided by

2, 4, 8, or 16 to provide lower frequencyD/A clocks.

A pair of front panel µSync connectorsallows multiple boards to be synchro-nized. They accept CML inputs that drivethe board’s sync and trigger/gate signals.The Pentek Models 7892 or 9192 CobaltSynchronizers can drive multiple 78670µSync connectors enabling large, multi-channel synchronous configurations.


independent memory banks of DDR3SDRAM. Each bank is 512 MB deep and isan integral part of the board’s DMA andwaveform playback capabilities. Waveformtables can be loaded into the memorieswith playback managed by the linked listcontrollers.



standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications. Thex8 lane interface includes multiple DMAcontrollers for efficient transfers to andfrom the board. ➤D/A Waveform Playback IP

ModuleThe Model 78670 factory-

installed functions include asophisticated D/A WaveformPlayback IP module. Fourlinked list controllers supportwaveform generation to thefour D/As from tables stored ineither on-board memory or off-board host memory.



D/A

WAVEFORM

PLAYBACK

IP MODULE 1

toD/A Ch 1 & 2


FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40

D/A

WAVEFORM

PLAYBACK

IP MODULE 2

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 2

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 3

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 3

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 4

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 4

MEMORYCONTROL

TESTSIGNAL

GENERATOR

PCIe INTERFACE

DATAINTERLEAVER

16toD/A Ch 3 & 4

DATAINTERLEAVER

16


Pentek, Inc.


➤➤➤➤➤ SpecificationsD/A Converters





78670 4-Channel 1.25 GHz D/Awith Virtex-6 FPGA - x8PCIe

Options:









Model Description














Pentek, Inc.

4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U VPXModel 53670


family of high performance 3U VPX boardsbased on the Xilinx Virtex-6 FPGA. This4-channel, high-speed data converter issuitable for connection to transmit HF or IFports of a communications or radar system.Its built-in data playback features offer anideal turnkey solution for demandingtransmit applications.

It includes four D/As, four digitalupconverters and four banks of memory.In addition to supporting PCI Express Gen. 2over the 3U VPX backplane, the Model53670 includes general purpose and gigabitserial connectors for application-specific I/O .

















for multiboard synchronization■ User-configurable gigabit

serial interface■ Optional LVDS connections







TIMING BUSGENERATOR


VCXO

16


16

ConfigFLASH64 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

1616

DDR3SDRAM512 MB

DDR3SDRAM512 MB


Clock/SyncBus A

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

16 16

Gate InSync In

�Sync Bus A

Gate InSync In

�Sync Bus B

Trigger In

Clock/SyncBus B

LVDS

40

FPGAI/O

Option -104

VPX-P2

GTXGTXGTX

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

Option -105

4X8X 4X

x8PCIe

VIRTEX-6 FPGA



Pentek, Inc.














standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications. Thex8 lane interface includes multiple DMAcontrollers for efficient transfers to andfrom the board. ➤D/A Waveform Playback IP





D/A

WAVEFORM

PLAYBACK

IP MODULE 1

toD/A Ch 1 & 2


FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40

D/A

WAVEFORM

PLAYBACK

IP MODULE 2

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 2

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 3

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 3

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 4

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 4

MEMORYCONTROL

TESTSIGNAL

GENERATOR

PCIe INTERFACE

DATAINTERLEAVER

16toD/A Ch 3 & 4

DATAINTERLEAVER

16


Pentek, Inc.



switching configuration. A fabric-transpar-ent crossbar switch bridges numerousinterfaces and components on the boardusing gigabit serial data paths with no latency.Programmable signal input equalizationand output pre-emphasis settings enableoptimization. Data paths can be selected assingle (1X) lanes, or groups of four lanes (4X).







53670 4-Channel 1.25 GHz D/Awith Virtex-6 FPGA - 3UVPX

Options:










versions

Model Description



Timing Bus: 19-pin µSync bus connectorincludes, clock, reset and gate/triggerinputs and outputs, CML






Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.



family of high performance 3U VPX boardsbased on the Xilinx Virtex-6 FPGA. This4-channel, high-speed data converter issuitable for connection to transmit HF or IFports of a communications or radar system.Its built-in data playback features offer anideal turnkey solution for demandingtransmit applications.

It includes four D/As, four digitalupconverters and four banks of memory.In addition to supporting PCI Express Gen. 2over the 3U VPX backplane, the Model52670 includes general purpose and gigabitserial connectors for application-specific I/O .

















for multiboard synchronization■ User-configurable gigabit

serial interface■ Optional LVDS connections







TIMING BUSGENERATOR


VCXO

16


16

ConfigFLASH64 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

1616

DDR3SDRAM512 MB

DDR3SDRAM512 MB


Clock/SyncBus A

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

16 16

Gate InSync In

�Sync Bus A

Gate InSync In

�Sync Bus B

Trigger In

Clock/SyncBus B

LVDS

40

FPGAI/O

Option -104

VPX-P2 VPX-P1

VIRTEX-6 FPGA


GTXGTXGTX

GigabitSerial I/O

Option -105

4X4X 4X

x4PCIe


Pentek, Inc.














standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications. Thex4 lane interface includes multiple DMAcontrollers for efficient transfers to andfrom the board. ➤


The Model 52670 factory-installed functions include asophisticated D/A WaveformPlayback IP module. Fourlinked list controllers supportwaveform generation to thefour D/As from tables stored ineither on-board memory or off-board host memory.

Data for Channel 1 andChannel 2 are interleaved fordelivery to a dual channel D/Adevice. For this reason, theymust share a common trigger/gate, sample rate, interpolationfactor, and other parameters.The same rules apply to Chan-nel 3 and Channel 4. Parametersincluding length of waveform,waveform repetition, etc. can beprogrammed for each channel.


D/A

WAVEFORM

PLAYBACK

IP MODULE 1

toD/A Ch 1 & 2


FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 1

MEMORYCONTROL

4X 4X 4X 40

D/A

WAVEFORM

PLAYBACK

IP MODULE 2

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 2

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 3

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 3

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 4

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 4

MEMORYCONTROL

TESTSIGNAL

GENERATOR

PCIe INTERFACE

DATAINTERLEAVER

16toD/A Ch 3 & 4

DATAINTERLEAVER

16


Pentek, Inc.


➤➤➤➤➤ SpecificationsD/A Converters







Options:










versions

Model Description







PCI-Express InterfacePCI Express Bus: Gen. 1 or Gen 2: x4


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.

4- or 8-Channel 1.25 GHz D/A with DUC and Virtex-6 FPGA -6U OpenVPX

Models57670 & 58670




These models include four or eight D/As,four or eight DUCs, and four or eight banksof memory.



Each member of the Cobalt family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces.The factory-installed functions in thesemodels include four or eightD/A waveformplayback IP modules, to support waveformgeneration through the D/A converters. IPmodules for DDR3 SDRAM memories,controllers for all data clocking and synchro-nization functions, test signal generators,and a PCIe interface complete the factory-

installed functions and enable these modelsto operate as complete turnkey solutions,without the need to develop any FPGA IP.







Features■ Supports Xilinx Virtex-6

LXT and SXT FPGAs■ Four or eight 1.25 GHz

16-bit D/As■ Four or eight digital

upconverters■ Programmable output levels

■ 250 MHz max. outputbandwidth

■ 2 or 4 GB of DDR3 SDRAM■ PCI Express (Gen. 1 & 2)

interface up to x8■ Sample clock synchronization to

an external system reference■ Dual-or Quad µSync clock/

sync bus for multiboardsynchronization




VIRTEX-6 FPGA

LX240T or SX315T

16

ConfigFLASH64 MB

LVDS GTX

40 8X

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P3

GTXGTX

PCIeGen. 2 x8

4X4X

PCIeGen. 2 x8

VPX-P2VPX-P1

PCIe-to PCIeSWITCH

From/To

Other XMC

Module of

Model 58671

Option -105

Gigabit Serial I/O







TIMING BUSGENERATOR


VCXO


Clock/SyncBus A

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

16 16

Gate InSync In

�Sync Bus A

Gate InSync In

�Sync Bus B

Trigger In

Clock/SyncBus B

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB


New!

New!

New!

New!

New!

Model 58670


Pentek, Inc.


Models57670 & 58670

➤➤➤➤➤ Digital Upconverter and D/A StageTwo or four Texas Instruments DAC3484s

provide four or eight DUC (digital upcon-verter) and D/A channels. Each channelaccepts a baseband real or complex datastream from the FPGA and provides thatinput to the upconvert, interpolate andD/A stage.


If translation is disabled, each D/A actsas an interpolating 16-bit D/A with outputsampling rates up to 1.25 GHz. In bothmodes, the D/A provides interpolation factorsof 2x, 4x, 8x and 16x. Analog output is throughfour or eight front panel SSMC connectors.


required D/A clocking. The bus includes aclock, sync and a gate or trigger signal. Anon-board clock generator receives a sampleclock either from the front panel SSMC con-nector or from an on-board programmableVCXO (Voltage-Controlled Crystal Oscillator).In this latter mode, the front panel SSMCconnector can be used to provide a 10 MHzreference clock to phase-lock the VCXO.Either clock source (front panel or VCXO)

can be used directly or can be divided by2, 4, 8, or 16 to provide lower frequencyD/A clocks.

A pair of front panel µSync connectorsallows multiple boards to be synchro-nized. They accept CML inputs that drivethe board’s sync and trigger/gate signals.The Pentek Model 9192 Cobalt Synchro-nizer can drive multiple µSync connectorsenabling large, multichannel synchronousconfigurations.

Memory ResourcesThe architecture of these models supports

four or eight independent memory banksof DDR3 SDRAM. Each bank is 512 MBdeep and is an integral part of the board’sDMA and waveform playback capabilities.Waveform tables can be loaded into thememories with playback managed by thelinked-list controllers.





The factory-installed func-tions in these models includeone or two sophisticated D/AWaveform Playback IP modules.Four or eight linked list con-trollers support waveformgeneration to the four or eightD/As from tables stored ineither on-board memory or off-board host memory.

Data for Channel 1 andChannel 2 are interleaved fordelivery to a dual channel D/Adevice. For this reason, theymust share a common trigger/gate, sample rate, interpolationfactor, and other parameters.The same rules apply to Chan-nel 3 and Channel 4, as well asto the other four channels ofModel 58670.

Parameters including lengthof waveform, waveform repeti-tion, etc. can be programmed foreach channel.

Up to 64 or 128 individuallink entries for each D/A chan-nel can be chained together tocreate complex waveforms witha minimum of programming.

D/A

WAVEFORM

PLAYBACK

IP MODULE 1

toD/A Ch 1 & 2


FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40

D/A

WAVEFORM

PLAYBACK

IP MODULE 2

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 2

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 3

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 3

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 4

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 4

MEMORYCONTROL

TESTSIGNAL

GENERATOR

PCIe INTERFACE

DATAINTERLEAVER

16toD/A Ch 3 & 4

DATAINTERLEAVER

16


Pentek, Inc.


Models57670 & 58670

➤➤➤➤➤ SpecificationsModel 57670: 4-Channel DUC, 4-channel

D/AModel 58670: 8-Channel DUC, 8-channel

D/AD/A Converters (4 or8)


Front Panel Analog Signal Outputs (4 or 8)Output Type: Transformer-coupled,front panel female SSMC connectorsFull Scale Output: Programmable from–20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p)in 16 stepsFull Scale Output Programming:1.0x(G+1)/16 Vp-p, where 4-bit integerG = 0 to 15

Clock Synthesizers (1 or 2)Clock Source: Selectable from on-boardprogrammable VCXO or front panelexternal clockVCXO Frequency Ranges: 10 to 945 MHz,970 to 1134 MHz and 1213 to 1417 MHzSynchronization: VCXO can be phase-locked to an external 4 to 200 MHzsystem reference, typically 10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8, or



58670 8-Channel 1.25 GHz D/Awith two Virtex-6 FPGAs- 6U VPX

Options:










versions

Model Description


16 for the D/A clockExternal Clocks (1 or 2)

Type: Front panel female SSMC connector,sine wave, 0 to +10 dBm, AC-coupled,50 ohms, accepts 10 to 500 MHz sampleclock or 5 or 10 MHz system reference

External Trigger Inputs (1 or 2)Type: Front panel female SSMC connectorFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Timing Bus (1 or 2): 19-pin µSync busconnector includes, clock, reset andgate/trigger inputs and outputs, CML



Memory Banks (1 or 2)Four or eight 512 MB DDR3 SDRAMmemory banks, 400 MHz DDR



Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




Pentek, Inc.

4- or 8-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - cPCIModels 72670,73670 and 74670




These models include four or eight D/As,four or eight DUCs, and four or eight banksof memory.



Each member of the Cobalt family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces.The factory-installed functions in thesemodels include four or eightD/A waveformplayback IP modules, to support waveformgeneration through the D/A converters. IPmodules for DDR3 SDRAM memories,

controllers for all data clocking and synchro-nization functions, a test signal generator,and a PCIe interface complete the factory-installed functions and enable these modelsto operate as complete turnkey solutions,without the need to develop any FPGA IP.








LXT and SXT FPGAs■ Four or eight 1.25 GHz

16-bit D/As■ Four or eight digital

upconverters■ Programmable output levels

■ 250 MHz max. outputbandwidth

■ 2 or 4 GB of DDR3 SDRAM■ Sample clock synchronization to

an external system reference■ Dual-or Quad µSync clock/

sync bus for multiboardsynchronization


TIMING BUSGENERATOR


VCXO

16


16

ConfigFLASH64 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

1616

DDR3SDRAM512 MB

DDR3SDRAM512 MB


Clock/SyncBus A

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

16 16

Gate InSync In

�Sync Bus A

Gate InSync In

�Sync Bus B

Trigger In

Clock/SyncBus B

VIRTEX-6 FPGA




MODEL 73670

INTERFACES ONLY

PCIeto PCI

BRIDGE

40

LVDS GTX



J2

PCIeto PCI

BRIDGE

PCIto PCI

BRIDGE

From/To Other

XMC Module of

Model 74670

GTX

x4 PCIe


4X40

LVDS


J3

VIRTEX-6 FPGA




Pentek, Inc.


➤➤➤➤➤ Digital Upconverter and D/A StageTwo or four Texas Instruments DAC3484s

provide four or eight DUC (digital upcon-verter) and D/A channels. Each channelaccepts a baseband real or complex datastream from the FPGA and provides thatinput to the upconvert, interpolate andD/A stage.






A pair of front panel µSync connectorsallows multiple boards to be synchro-nized. They accept CML inputs that drivethe board’s sync and trigger/gate signals.The Pentek Models 7292, 7392 and 7492or the 9192 Cobalt Synchronizers candrive multiple µSync connectors enablinglarge, multichannel synchronous configu-rations.

Memory ResourcesThe architecture of these models supports

four or eight independent memory banksof DDR3 SDRAM. Each bank is 512 MBdeep and is an integral part of the board’sDMA and waveform playback capabilities.Waveform tables can be loaded into thememories with playback managed by thelinked list controllers.





The factory-installed func-tions in these models includeone or two sophisticated D/AWaveform Playback IP modules.Four or eight linked list con-trollers support waveformgeneration to the four or eightD/As from tables stored ineither on-board memory or off-board host memory.

Data for Channel 1 andChannel 2 are interleaved fordelivery to a dual channel D/Adevice. For this reason, theymust share a common trigger/gate, sample rate, interpolationfactor, and other parameters.The same rules apply to Chan-nel 3 and Channel 4, as well asto the other four channels ofModel 74670.

Parameters including lengthof waveform, waveform repeti-tion, etc. can be programmed foreach channel.

Up to 64 or 128 individuallink entries for each D/A chan-nel can be chained together tocreate complex waveforms witha minimum of programming.

D/A

WAVEFORM

PLAYBACK

IP MODULE 1

toD/A Ch 1 & 2

PCIeFPGA

I/O


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 1

MEMORYCONTROL

4X 40

D/A

WAVEFORM

PLAYBACK

IP MODULE 2

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 2

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 3

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 3

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 4

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 4

MEMORYCONTROL

TESTSIGNAL

GENERATOR

PCIe INTERFACE

DATAINTERLEAVER

16toD/A Ch 3 & 4

DATAINTERLEAVER

16


Pentek, Inc.


➤➤➤➤➤ SpecificationsModels 72670 and 73670: 4-Channel DUC,

4-channel D/AModel 74670: 8-Channel DUC, 4-channel D/AD/A Converters (4 or8)


Front Panel Analog Signal Outputs (4 or 8)Output Type: Transformer-coupled,front panel female SSMC connectorsFull Scale Output: Programmable from–20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p)in 16 stepsFull Scale Output Programming:1.0x(G+1)/16 Vp-p, where 4-bit integerG = 0 to 15

Clock Synthesizers (1 or 2)Clock Source: Selectable from on-boardprogrammable VCXO or front panelexternal clockVCXO Frequency Ranges: 10 to 945 MHz,970 to 1134 MHz and 1213 to 1417 MHzSynchronization: VCXO can be phase-locked to an external 4 to 200 MHzsystem reference, typically 10 MHzClock Dividers: External clock orVCXO can be divided by 1, 2, 4, 8, or16 for the D/A clock


72670 4-Channel 1.25 GHz D/Awith Virtex-6 FPGA - 6UcPCI



Options:








External Clocks (1 or 2)Type: Front panel female SSMC connector,sine wave, 0 to +10 dBm, AC-coupled,50 ohms, accepts 10 to 500 MHz sampleclock or 5 or 10 MHz system reference

External Trigger Inputs (1 or 2)Type: Front panel female SSMC connectorFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Timing Bus (1 or 2): 19-pin µSync busconnector includes, clock, reset andgate/trigger inputs and outputs, CML



Memory Banks (1 or 2)Four or eight 512 MB DDR3 SDRAMmemory banks, 400 MHz DDR





Pentek, Inc.

4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - AMCModel 56670


family of high-performance AMC modulesbased on the Xilinx Virtex-6 FPGA. This4-channel, high-speed data converter issuitable for connection to transmit HF or IFports of a communications or radar system.Its built-in data playback features offer anideal turnkey solution for demandingtransmit applications.

It includes four D/As, four digitalupconverters and four banks of memory.In addition to supporting PCI Express Gen. 2as a native interface, the Model 56670includes a front panel general-purposeconnector for application-specific I/O.



Each member of the Cobalt family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces.The 56670 factory-installed functions includefour D/A waveform playback IP modules,to support waveform generation throughthe D/A converters. IP modules for DDR3

SDRAM memories, a controller for alldata clocking and synchronization functions,a test signal generator, and a PCIe interfacecomplete the factory-installed functionsand enable the 56670 to operate as a com-plete turnkey solution, without the needto develop any FPGA IP.
















TIMING BUSGENERATOR


VCXO

16


16

ConfigFLASH64 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

1616

DDR3SDRAM512 MB

DDR3SDRAM512 MB


Clock/SyncBus A

40

LVDS


RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

16 16

Gate InSync In

μSync Bus A

Gate InSync In

μSync Bus B

Trigger In

Clock/SyncBus B

VIRTEX-6 FPGA


GTX

x8 PCIe

8X

FrontPanel

FrontPanel

AMCPorts 4 to 11

IPMICONTROLLER

RS-232


Pentek, Inc.











independent memory banks of DDR3SDRAM. Each bank is 512 MB deep and isan integral part of the module’s DMA andwaveform playback capabilities. Waveformtables can be loaded into the memorieswith playback managed by the linked listcontrollers.



AMC.1 specification by providing an x8PCIe connection to AdvancedTCA carriersor µTCA chassis. Module management isprovided by an IPMI 2.0 MMC (ModuleManagement Controller). ➤D/A Waveform Playback IP





D/A

WAVEFORM

PLAYBACK

IP MODULE 1

toD/A Ch 1 & 2

PCIeFPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 1

MEMORYCONTROL

8X 40

D/A

WAVEFORM

PLAYBACK

IP MODULE 2

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 2

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 3

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 3

MEMORYCONTROL

D/A

WAVEFORM

PLAYBACK

IP MODULE 4

DATAUNPACKING

& FLOWCONTROL

MUX


toMem

Bank 4

MEMORYCONTROL

TESTSIGNAL

GENERATOR

PCIe INTERFACE

DATAINTERLEAVER

16toD/A Ch 3 & 4

DATAINTERLEAVER

16


Pentek, Inc.



standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications. Thex8 lane interface includes multiple DMAcontrollers for efficient transfers to andfrom the module.






56670 4-Channel 1.25 GHz D/Awith Virtex-6 FPGA - AMC

Options:









versions




Field Programmable Gate ArrayStandard: Xilinx Virtex-6XC6VLX130T-2Optional: Xilinx Virtex-6XC6VLX240T-2 or XC6VSX315T-2








Pentek, Inc.

L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - XMCModel 71690


family of high performance XMC modulesbased on the Xilinx Virtex-6 FPGA. A 2-Chan-nel high-speed data converter, it is suitablefor connection directly to the RF port of acommunications or radar system. Its built-indata capture features offer an ideal turnkeysolution as well as a platform for developingand deploying custom FPGA processing IP.

It includes an L-Band RF tuner, two A/Dsand four banks of memory. In addition tosupporting PCI Express Gen. 2 as a nativeinterface, the Model 71690 includes generalpurpose and gigabit serial connectors forapplication-specific I/O .



Each member of the Cobalt family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces.The 71690 factory-installed functions includetwo A/D acquisition IP modules.

IP modules for either DDR3 or QDRII+memories, a controller for all data clockingand synchronization functions, a test signal

generator, and a PCIe interface complete thefactory-installed functions and enable the71690 to operate as a complete turnkeysolution without the need to develop anyFPGA IP.


functions, users can install their own customIP for data processing. Pentek GateFlowFPGA Design Kits include all of the factory-installed modules as documented sourcecode. Developers can integrate their own IPwith the Pentek factory-installed functions oruse the GateFlow kit to completely replacethe Pentek IP with their own.





Features■ Accepts RF signals from

925 MHz to 2175 MHz■ Programmable LNA boosts

LNB (low-noise block)antenna signal levels withup to 60 dB gain

■ Programmable analogdownconverter providesI + Q baseband signals withbandwidths ranging from4 to 40 MHz

■ Two 200 MHz 16-bit A/Dsdigitize the I + Q signalssynchronously

■ Supports Xilinx Virtex-6 LXTand SXT FPGAs

■ 2 GB of DDR3 SDRAM or32 MB of QDRII+ SRAM

■ Sample clock synchronizationto an external system reference


■ Clock/sync bus for multimodulesynchronization

■ VITA 42.0 XMC compatiblewith switched fabric interfaces



VCXO

16

QDRII+SRAM8 MB


Sample ClkRef In

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus


A/D Clock/Sync

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII+ option 160

DDR3 option 165

Trigger 1

40

GigabitSerial I/O

(option 105)

4X

GTX

4X

GTX LVDSGTX

FPGAGPIO

(option 104)

x8 PCIe

8X

P14PMC

P16XMC

P15XMC

200 MHz16-BIT A/D

200 MHz16-BIT A/D

1616

MAX2112

I Q

RefIn

RFIn

RefOut

12-BITD/A

2

I C2

GC

Control

Trigger 2

TIMINGGENERATOR


Ref

VIRTEX-6 FPGA



Pentek, Inc.


➤ ➤ ➤ ➤ ➤ RF Tuner StageA front panel SSMC connector accepts

L-Band signals between 925 MHz and2175 MHz from an antenna LNB (low noiseblock). A Maxim MAX2112 tuner directlyconverts these L-Band signals to basebandusing a broadband I/Q downconverter.

The device includes an RF variable-gainLNA (low noise amplifier), a PLL (phase-locked loop) synthesized local oscillator,quadrature (I + Q) downconverting mixers,baseband lowpass filters with program-mable cutoff frequency, and variable-gainbaseband amplifiers.

The fractional-N PLL synthesizer locksits VCO to the timing generator output, orto an external reference input between 12and 30 MHz. Together, the baseband amplifi-ers and the RF LNA offer a programmablelinear gain range of 60 dB.

An integrated lowpass filter with vari-able bandwidth provides bandwidthsranging from 4 to 40 MHz, programmablewith 8 bits of resolution.

A/D Converter StageThe analog baseband I and Q analog

tuner outputs are then applied to twoTexas Instruments ADS5485 200 MHz,16-bit A/D converters. The digital outputsare delivered into the Virtex-6 FPGA forsignal processing, data capture or for rout-ing to other module resources.

A/D Clocking and SynchronizationAn internal timing generator provides

all timing, gating, triggering and synchro-nization functions required by the A/Dconverters. It also serves as an optionalsource for the L-Band tuner reference.

The front panel SSMC clock input canbe used directly as the A/D sample clock.In an alternate mode, the sample clockcan be sourced from an on-board program-mable VCXO (voltage-controlled crystaloscillator). In this mode, the front panel SSMCclock input connector accepts a 10 MHz ref-erence signal for synchronizing the VCXOusing a PLL.

The timing generator uses a front panelLVPECL 26-pin clock/sync connector forone clock, two sync, and two gate/triggersignals. In the slave mode, it accepts LVPECLinputs that drive the clock, sync and gate/trigger signals within the module. In themaster mode, the LVPECL bus drives out-put timing signals to synchronize multipleslave modules, supporting synchronoussampling and sync functions across allconnected modules.


four independent memory banks whichcan be configured with all QDRII+ SRAM,all DDR3 SDRAM, or as combination oftwo banks of each type of memory. ➤

A/D Acquisition IP ModulesThe 71690 features two A/D

Acquisition IP Modules for eas-ily capturing and moving data.Each IP module can receive datafrom either of the two A/Ds ora test signal generator



PCIe INTERFACE

fromA/D (I)

fromA/D (Q)

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


SIGNALGENERATOR

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40


Pentek, Inc.



71690 L-Band RF Tuner with2-Channel 200 MHz A/Dand Virtex-6 FPGA - XMC

Options:





-150 Two 8 MB QDRII+ SRAMMemory Banks (Banks 1and 2)





versions

Model Description


➤ Each QDRII+ SRAM bank can be up to8 MB deep and is an integral part of themodule’s DMA capabilities, providingFIFO memory space for creating DMApackets. For applications requiring deepermemory resources, DDR3 SDRAM bankscan each be up to 512 MB deep. Built-inmemory functions include multichannelA/D data capture, tagging and streaming.

The factory-installed A/D acquisitionmodules use memory banks 1 & 2. Banks 3& 4 can be optionally installed to supportcustom user-installed IP within the FPGA .


VITA 42.0 XMC specification. Two connec-tors each provide dual 4X links or a single8X link with up to a 6 GHz bit clock. Withdual XMC connectors, the 71690 supportsx8 PCIe on the first XMC connector leavingthe second connector free to support user-installed transfer protocols specific to thetarget application.



SpecificationsFront Panel Analog Signal Input

Connector: Front panel female SSMCImpedance: 50 ohms

L-Band TunerType: Maxim MAX2112Input Frequency Range: 925 MHz to2175 MHzMonolithic VCO Phase Noise:-97 dBc/Hz at 10 kHzFractional-N PLL Synthesizer:freqVCO = (N.F) x freqREF

where integer N = 19 to 251 andfractional F is a 20-bit binary valuePLL Reference (freqREF): Front panelSSMC connector or on-board 27 MHzcrystal (Option -100), 12 to 30 MHzLNA Gain: 0 to 65 dB, controlled by aprogrammable 12-bit D/A converter*Baseband Amplifier Gain: 0 to 15 dB,in 1 dB steps**Usable Full-Scale Input Range: –50 dBmto +10 dBmBaseband Low Pass Filter: Cutoff fre-quency programmable from 4 to 40 MHzwith 8-bit resolution


Sample Clock Sources: On-board timinggenerator/synthesizer

A/D Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO (10 to 810 MHz),front panel external clock or LVPECLtiming busSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLL systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16, for theA/D clock

Timing Generator External Clock InputType: Front panel female SSMC connec-tor, sine wave, 0 to +10 dBm, AC-coupled,50 ohms, accepts 10 to 200 MHz (up to800 MHz when Timing Generator divideris enabled) or PLL system reference

Timing Generator Bus: 26-pin front panelconnector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs;TTL signal for gate/trigger and sync/PPS inputs

External Trigger InputQuantity: 2Type: Front panel female SSMC connec-tor, LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS




PCI-Express InterfacePCI Express Bus: Gen. 1 x4 or x8;Gen. 2 x4






Pentek, Inc.

L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - x8 PCIeModel 78690


family of high performance PCIe boardsbased on the Xilinx Virtex-6 FPGA. A 2-Chan-nel high-speed data converter, it is suitablefor connection directly to the RF port of acommunications or radar system. Its built-indata capture features offer an ideal turnkeysolution.

It includes an L-Band RF tuner, two A/Dsand four banks of memory. In addition tosupporting PCI Express Gen. 2 as a nativeinterface, the Model 78690 includes optionalgeneral-purpose and gigabit serial connec-tors for application-specific I/O protocols.




IP modules for either DDR3 or QDRII+memories, a controller for all data clockingand synchronization functions, a test signalgenerator, and a PCIe interface complete thefactory-installed functions and enable the

78690 to operate as a complete turnkeysolution without the need to develop anyFPGA IP.







VCXO

16

QDRII+SRAM8 MB


Sample ClkRef In

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus


A/D Clock/Sync

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII+ option 160

DDR3 option 165

Trigger 1

200 MHz16-BIT A/D

200 MHz16-BIT A/D

1616

MAX2112

I Q

RefIn

RFIn

RefOut

12-BITD/A

2

I C2

GC

Control

Trigger 2

TIMINGGENERATOR


RefOption 100

40 4X

GTX

4X

GTXLVDS GTX

OptionalFPGAGPIO

OptionalSerialI/O

8X

68-pinHeader

x8 PCI Express

Dual 4XSerialConn

x8 PCIe

VIRTEX-6 FPGA



925 MHz to 2175 MHz

■ Programmable LNA boostsLNB (low-noise block)antenna signal levels withup to 60 dB gain


■ Two 200 MHz 16-bit A/Ds■ Supports Xilinx Virtex-6 LXT

and SXT FPGAs■ 2 GB of DDR3 SDRAM or

32 MB of QDRII+ SRAM■ Sample clock synchronization







Pentek, Inc.








tuner outputs are then applied to twoTexas Instruments ADS5485 200 MHz,16-bit A/D converters. The digital outputsare delivered into the Virtex-6 FPGA forsignal processing, data capture or for rout-ing to other board resources.




The timing generator uses a front panelLVPECL 26-pin clock/sync connector forone clock, two sync, and two gate/triggersignals. In the slave mode, it accepts LVPECLinputs that drive the clock, sync and gate/trigger signals within the board. In themaster mode, the LVPECL bus drives out-put timing signals to synchronize multipleslave boards, supporting synchronoussampling and sync functions across allconnected boards.







PCIe INTERFACE

fromA/D (I)

fromA/D (Q)

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


SIGNALGENERATOR

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40


Pentek, Inc.



78690 L-Band RF Tuner with2-Channel 200 MHz A/Dand Virtex-6 FPGA - PCIe

Options:









Model Description



The factory-installed A/D AcquisitionModules use memory banks 1 & 2. Banks 3& 4 can be optionally installed to supportcustom user-installed IP within the FPGA .


standard interface fully compliant with PCIExpress Gen. 1 & 2 bus specifications.Supporting PCIe links up to x8, the interfaceincludes multiple DMA controllers forefficient transfers to and from the board.




















Pentek, Inc.

L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - 3U VPXModel 53690


family of high performance 3U VPX boardsbased on the Xilinx Virtex-6 FPGA. A 2-Chan-nel high-speed data converter, it is suitablefor connection directly to the RF port of acommunications or radar system. Its built-indata capture features offer an ideal turnkeysolution as well as a platform for developingand deploying custom FPGA processing IP.

The Model 53690 includes an L-BandRF tuner, two A/Ds and four banks ofmemory. It features built-in support for PCIExpress over the 3U VPX backplane.




IP modules for either DDR3 or QDRII+memories, a controller for all data clockingand synchronization functions, a test signalgenerator, and a PCIe interface complete the

factory-installed functions and enable the53690 to operate as a complete turnkeysolution without the need to develop anyFPGA IP.







VCXO

16

QDRII+SRAM8 MB


Sample ClkRef In

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus


A/D Clock/Sync

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII+ option 160

DDR3 option 165

Trigger 1

200 MHz16-BIT A/D

200 MHz16-BIT A/D

1616

MAX2112

I Q

RefIn

RFIn

RefOut

12-BITD/A

2

I C2

GC

Control

Trigger 2

TIMINGGENERATOR


Ref

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTXLVDS

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

4X8X 4X

x8PCIe

Option -105

VIRTEX-6 FPGA





LNB antenna signal levelswith up to 60 dB gain





to an external system reference■ Clock/sync bus for multiboard








Pentek, Inc.










all timing, gating, triggering and synchro-

nization functions required by the A/Dconverters. It also serves as an optionalsource for the L-Band tuner reference.




four independent memory banks whichcan be configured with all QDRII+ SRAM,all DDR3 SDRAM, or as combination oftwo banks of each type of memory. EachQDRII+ SRAM bank can be up to 8 MBdeep and is an integral part of the board’sDMA capabilities, providing FIFO memoryspace for creating DMA packets. Forapplications requiring deeper memoryresources, DDR3 SDRAM banks can eachbe up to 512 MB deep. ➤





PCIe INTERFACE

fromA/D (I)

fromA/D (Q)

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


SIGNALGENERATOR

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40


Pentek, Inc.



53690 L-Band RF Tuner with2-Channel 200 MHz A/Dand Virtex-6 FPGA - 3UVPX

Options:










versions

Model Description


➤ Built-in memory functions include mul-tichannel A/D data capture, tagging andstreaming. The factory-installed A/D Acqui-sition Modules use memory banks 1 & 2.Banks 3 & 4 can be optionally installed tosupport custom user IP within the FPGA.


switching configuration. A fabric-transparentcrossbar switch bridges numerous interfacesand components on the board using giga-bit serial data paths with no latency.

Programmable signal input equalizationand output pre-emphasis settings enableoptimization. Data paths can be selected assingle (1X) lanes, or groups of four lanes (4X).












Custom I/OOption -104: Provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/OOption -105: Provides one 8X or two 4Xgigabit links between the FPGA and theVPX P1 connector for serial protocols


PCI-Express InterfacePCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)



PCI Express InterfaceThe Model 53690 includes an

industry standard interface fullycompliant with PCI ExpressGen. 1 & 2 bus specifications.Supporting PCIe links up to x8,the interface includes multipleDMA controllers for efficienttransfers to and from the board


52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.



family of high performance 3U VPX boardsbased on the Xilinx Virtex-6 FPGA. A 2-Chan-nel high-speed data converter, it is suitablefor connection directly to the RF port of acommunications or radar system. Its built-indata capture features offer an ideal turnkeysolution as well as a platform for developingand deploying custom FPGA processing IP.

The Model 52690 includes an L-BandRF tuner, two A/Ds and four banks ofmemory. It features built-in support for PCIExpress over the 3U VPX backplane.




IP modules for either DDR3 or QDRII+memories, a controller for all data clockingand synchronization functions, a test signalgenerator, and a PCIe interface complete the








VCXO

16

QDRII+SRAM8 MB


Sample ClkRef In

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus


A/D Clock/Sync

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII+ option 160

DDR3 option 165

Trigger 1

200 MHz16-BIT A/D

200 MHz16-BIT A/D

1616

MAX2112

I Q

RefIn

RFIn

RefOut

12-BITD/A

2

I C2

GC

Control

Trigger 2

TIMINGGENERATOR


Ref

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

LVDS

VPX-P1

VIRTEX-6 FPGA


GTXGTXGTX

GigabitSerial I/O

Option -105

4X4X 4X

x4PCIe




LNB antenna signal levelswith up to 60 dB gain





to an external system reference■ Clock/sync bus for multiboard








Pentek, Inc.



















PCIe INTERFACE

fromA/D (I)

fromA/D (Q)

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


SIGNALGENERATOR

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

4X 4X 4X 40


Pentek, Inc.




Options:










versionsModel Description



The factory-installed A/D AcquisitionModules use memory banks 1 & 2. Banks 3& 4 can be optionally installed to supportcustom user-installed IP within the FPGA .








Timing Generator External Clock InputType: Front panel female SSMC connec-tor, sine wave, 0 to +10 dBm, AC-coupled,

50 ohms, accepts 10 to 200 MHz (up to800 MHz when Timing Generator divideris enabled) or PLL system reference








Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




industry standard interface fullycompliant with PCI ExpressGen. 1 & 2 bus specifications.Supporting PCIe links up to x4,the interface includes multipleDMA controllers for efficienttransfers to and from the board.


52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.

One or two L-Band RF Tuners, 2- or 4-Channel 200 MHz A/D,Virtex-6 FPGA - 6U OpenVPX

Models57690 & 58690




These models include one ot two L-BandRF tuners, two or four A/Ds and four oreight banks of memory.



Each member of the Cobalt family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces.The factory-installed functions in these mod-els include two or four A/D acquisition IPmodules. IP modules for either DDR3 orQDRII+ memories, controllers for all dataclocking and synchronization functions,test signal generators, and a PCIe interfacecomplete the factory-installed functions and

Features■ One or two L-Band tuners

accept RF signals from925 MHz to 2175 MHz

■ One or two programmableLNAs boost LNB (low-noiseblock) antenna signal levelswith up to 60 dB gain

■ One or two programmableanalog downconvertersprovide I + Q basebandsignals with bandwidthsranging from 4 to 40 MHz

■ Two or four 200 MHz 16-bitA/Ds


■ Up to 2 or 4 GB of DDR3SDRAM; or: 32 MB or 64MBof QDRII+ SRAM





New!

New!

New!

New!

New!

16

QDRII+SRAM8 MB

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

QDRII+ option 160

LVDS GTX

40 8X

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P3

GTXGTX

PCIeGen. 2 x8

4X4X

PCIeGen. 2 x8

VPX-P2VPX-P1

PCIe-to PCIeSWITCH

From/To

Other XMC

Module of

Model 58690

Option -105

Gigabit Serial I/O







VCXO


Sample ClkRef In

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus


A/D Clock/Sync

DDR3SDRAM512 MB

DDR3SDRAM512 MB

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155 DDR3 option 165

Trigger 1

200 MHz16-BIT A/D

200 MHz16-BIT A/D

1616

MAX2112

I Q

RefIn

RFIn

RefOut

12-BITD/A

2

I C2

GC

Control

Trigger 2

TIMINGGENERATOR


Ref

VIRTEX-6 FPGA


Model 58690

enable these models to operate as completeturnkey solutions without the need todevelop any FPGA IP.








Pentek, Inc.


Models57690 & 58690

➤➤➤➤➤ RF Tuner StagesOne or two front panel SSMC connectors

accept L-Band signals between 925 MHzand 2175 MHz from the antenna LNBs (lownoise blocks). The Maxim MAX2112 tunersdirectly convert these L-Band signals to base-band using broadband I/Q downconverters.

The devices include RF variable-gainLNAs (low noise amplifiers), PLL (phase-locked loops) synthesized local oscillators,quadrature (I + Q) downconverting mixers,baseband lowpass filters with program-mable cutoff frequency, and variable-gainbaseband amplifiers.

The fractional-N PLL synthesizers locktheir VCOs to the timing generator output,or to an external reference input between 12and 30 MHz. Together, the baseband amplifi-ers and the RF LNAs offer a programmablelinear gain range of 60 dB.

The integrated lowpass filters with variablebandwidths provide bandwidths rangingfrom 4 to 40 MHz, programmable with 8 bitsof resolution.

A/D Converter StagesThe analog baseband I and Q analog

tuner outputs are then applied to two orfour Texas Instruments ADS5485 200 MHz,16-bit A/D converters. The digital outputsare delivered into the Virtex-6 FPGAs forsignal processing, data capture or for rout-ing to other board resources.




The timing generator uses a front panelLVPECL 26-pin clock/sync connector forone clock, two sync, and two gate/triggersignals. In the slave mode, it accepts LVPECLinputs that drive the clock, sync and gate/trigger signals within the bosrd. In themaster mode, the LVPECL bus drives out-put timing signals to synchronize multipleslave bosrds, supporting synchronoussampling and sync functions across allconnected boards.


four or eight independent memory bankswhich can be configured with all QDRII+SRAM, all DDR3 SDRAM, or as combinationof two banks of each type of memory. ➤

A/D Acquisition IP ModulesThese models feature two or

fourA/D Acquisition IP Modulesfor easily capturing and movingdata. Each IP module can receivedata from either of the two A/Dsor a test signal generator



PCIe INTERFACE

fromA/D (I)

fromA/D (Q)

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


SIGNALGENERATOR

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40


Pentek, Inc.


Models57690 & 58690



58690 Dual L-Band RF Tunerwith 4-Channel 200 MHzA/D and two Virtex-6FPGAs - 6U VPX

Options:










versions

Model Description


➤ Each QDRII+ SRAM bank can be up to8 MB deep and is an integral part of theboard’s DMA capabilities, providing FIFOmemory space for creating DMA packets.For applications requiring deeper memoryresources, DDR3 SDRAM banks can eachbe up to 512 MB deep. Built-in memoryfunctions include multichannel A/D datacapture, tagging and streaming.




SpecificationsModel 57690: One RF tuner, two A/DsModel 58690: Two RF tuners, four A/DsFront Panel Analog Signal Inputs (1 or 2)


L-Band Tuners (1 or 2)Type: Maxim MAX2112Input Frequency Range: 925 MHz to2175 MHzMonolithic VCO Phase Noise:-97 dBc/Hz at 10 kHzFractional-N PLL Synthesizer:freqVCO = (N.F) x freqREF where integerN = 19 to 251 and fractional F is a 20-bitbinary valuePLL Reference (freqREF): Front panelSSMC connector or on-board 27 MHzcrystal (Option -100), 12 to 30 MHzLNA Gain: 0 to 65 dB, controlled by aprogrammable 12-bit D/A converter*Baseband Amplifier Gain: 0 to 15 dB,in 1 dB steps**Usable Full-Scale Input Range: –50 dBmto +10 dBmBaseband Low Pass Filter: Cutoff fre-quency programmable from 4 to 40 MHzwith 8-bit resolution


Sample Clock Sources (1 or 2)On-board timing generator/synthesizer

A/D Clock Synthesizers (1 or 2)Clock Source: Selectable from on-boardprogrammable VCXO (10 to 810 MHz),front panel external clock or LVPECLtiming busSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLL systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16, for theA/D clock

Timing Generator External Clock Inputs(1 or 2)Type: Front panel female SSMC connec-tor, sine wave, 0 to +10 dBm, AC-coupled,50 ohms, accepts 10 to 200 MHz (up to800 MHz when Timing Generator divideris enabled) or PLL system reference

Timing Generator Bus (1 or 2): 26-pin frontpanel connector LVPECL bus includes,clock/sync/gate/PPS inputs and outputs;TTL signal for gate/trigger and sync/PPS inputs


Field Programmable Gate Arrays (1 or2)Standard: Xilinx Virtex-6 XC6VLX130TOptional: Xilinx Virtex-6 XC6VLX240Tor XC6VSX315T





Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




Pentek, Inc.

One or two L-Band RF Tuners, 2- or 4-Channel 200 MHz A/D,Virtex-6 FPGA - cPCI

Models 72690, 73690and 74690




These models include one ot two L-BandRF tuners, two or four A/Ds and four oreight banks of memory.



Each member of the Cobalt family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces.The factory-installed functions in these mod-els include two or four A/D acquisition IPmodules. IP modules for either DDR3 orQDRII+ memories, controllers for all dataclocking and synchronization functions, a

Features■ One or two L-Band tuners

accept RF signals from925 MHz to 2175 MHz

■ One or two programmableLNAs boost LNB (low-noiseblock) antenna signal levelswith up to 60 dB gain

■ One or two programmableanalog downconvertersprovide I + Q basebandsignals with bandwidthsranging from 4 to 40 MHz

■ Two or four 200 MHz 16-bitA/Ds


■ Up to 2 or 4 GB of DDR3SDRAM; or: 32 MB or 64MBof QDRII+ SRAM



VCXO

16

QDRII+SRAM8 MB


Sample ClkRef In

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus


A/D Clock/Sync

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII+ option 160

DDR3 option 165

Trigger 1

200 MHz16-BIT A/D

200 MHz16-BIT A/D

1616

MAX2112

I Q

RefIn

RFIn

RefOut

12-BITD/A

2

I C2

GC

Control

Trigger 2

TIMINGGENERATOR


Ref

VIRTEX-6 FPGA

MODEL 73690

INTERFACES ONLY

PCIeto PCI

BRIDGE

40

LVDS GTX



J2

PCIeto PCI

BRIDGE

PCIto PCI

BRIDGE

From/To Other

XMC Module of

MODEL 74690

GTX

x4 PCIe


4X




40

LVDS


J3

VIRTEX-6 FPGA



test signal generator, and a PCIe interfacecomplete the factory-installed functions andenable these models to operate as completeturnkey solutions without the need todevelop any FPGA IP.







Pentek, Inc.


Models 72690, 73690and 74690

➤➤➤➤➤ RF Tuner StageOne or two front panel SSMC connectors

accept L-Band signals between 925 MHzand 2175 MHz from the antenna LNBs (lownoise blocks). The Maxim MAX2112 tunersdirectly convert these L-Band signals to base-band using broadband I/Q downconverters.

The devices include RF variable-gainLNAs (low noise amplifiers), PLL (phase-locked loops) synthesized local oscillators,quadrature (I + Q) downconverting mixers,baseband lowpass filters with program-mable cutoff frequency, and variable-gainbaseband amplifiers.

The fractional-N PLL synthesizers locktheir VCOs to the timing generator output,or to an external reference input between 12and 30 MHz. Together, the baseband amplifi-ers and the RF LNA offer a programmablelinear gain range of 60 dB.

The integrated lowpass filters with vari-able bandwidths provide bandwidthsranging from 4 to 40 MHz, programmablewith 8 bits of resolution.


tuner outputs are then applied to two orfour Texas Instruments ADS5485 200 MHz,16-bit A/D converters. The digital outputsare delivered into the Virtex-6 FPGA forsignal processing, data capture or for rout-ing to other module resources.




The timing generator uses a front panelLVPECL 26-pin clock/sync connector forone clock, two sync, and two gate/triggersignals. In the slave mode, it accepts LVPECLinputs that drive the clock, sync and gate/trigger signals within the bosrd. In themaster mode, the LVPECL bus drives out-put timing signals to synchronize multipleslave bosrds, supporting synchronoussampling and sync functions across allconnected boards.


four or eight independent memory bankswhich can be configured with all QDRII+SRAM, all DDR3 SDRAM, or as combinationof two banks of each type of memory. ➤

A/D Acquisition IP ModulesThese models feature two or

fourA/D Acquisition IP Modulesfor easily capturing and movingdata. Each IP module can receivedata from either of the two A/Dsor a test signal generator



PCIe INTERFACE

fromA/D (I)

fromA/D (Q)

PCIe FPGAI/O


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


SIGNALGENERATOR

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

4X 40


Pentek, Inc.


Models 72690, 73690and 74690


71690 L-Band RF Tuner with2-Channel 200 MHz A/Dand Virtex-6 FPGA - XMC

Options:








➤ Each QDRII+ SRAM bank can be up to 8MB deep and is an integral part of theboard’s DMA capabilities, providing FIFOmemory space for creating DMA packets.For applications requiring deeper memoryresources, DDR3 SDRAM banks can eachbe up to 512 MB deep. Built-in memoryfunctions include multichannel A/D datacapture, tagging and streaming.


PCI-X InterfaceThe models include an industry-standard

interface compliant with PCI-X bus specifica-tions. The interface includes multiple DMAcontrollers for efficient transfers to and fromthe board. Data widths of 32 or 64 bits anddata rates of 33 and 66 MHz are supported.Model 73690: 32 bits only.

SpecificationsModel 72690 or Model 73690: 1 RF tuner,

2 A/DsModel 74690: 2 RF tuners, four A/DsFront Panel Analog Signal Inputs (1 or 2)


L-Band Tuners (1 or 2)Type: Maxim MAX2112Input Frequency Range: 925 MHz to2175 MHzMonolithic VCO Phase Noise:-97 dBc/Hz at 10 kHzFractional-N PLL Synthesizer:freqVCO = (N.F) x freqREF where integer N= 19 to 251 and fractional F is a 20-bitbinary valuePLL Reference (freqREF): Front panelSSMC connector or on-board 27 MHzcrystal (Option -100), 12 to 30 MHzLNA Gain: 0 to 65 dB, controlled by aprogrammable 12-bit D/A converter*Baseband Amplifier Gain: 0 to 15 dB,in 1 dB steps**Usable Full-Scale Input Range: –50 dBmto +10 dBmBaseband Low Pass Filter: Cutoff fre-quency programmable from 4 to 40 MHzwith 8-bit resolution


Sample Clock Sources (1 or 2)On-board timing generator/synthesizer

A/D Clock Synthesizers (1 or 2)Clock Source: Selectable from on-boardprogrammable VCXO (10 to 810 MHz),front panel external clock or LVPECLtiming busSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLL systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16, for theA/D clock

Timing Generator External Clock Inputs(1 or 2)Type: Front panel female SSMC connec-tor, sine wave, 0 to +10 dBm, AC-coupled,50 ohms, accepts 10 to 200 MHz (up to800 MHz when Timing Generator divideris enabled) or PLL system reference

Timing Generator Bus (1 or 2): 26-pin frontpanel connector LVPECL bus includes,clock/sync/gate/PPS inputs and outputs;TTL signal for gate/trigger and sync/PPS inputs


Field Programmable Gate Arrays (1 or2)Standard: Xilinx Virtex-6 XC6VLX130TOptional: Xilinx Virtex-6 XC6VLX240Tor XC6VSX315T







Pentek, Inc.

L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - AMCModel 56690


family of high-performance AMC modulesbased on the Xilinx Virtex-6 FPGA. A 2-Chan-nel high-speed data converter, it is suitablefor connection directly to the RF port of acommunications or radar system. Its built-indata capture features offer an ideal turnkeysolution as well as a platform for developingand deploying custom FPGA processing IP.

It includes an L-Band RF tuner, two A/Dsand four banks of memory. In addition tosupporting PCI Express Gen. 2 as a nativeinterface, the Model 56690 includes afront panel general-purpose connector forapplication-specific I/O.




IP modules for either DDR3 or QDRII+memories, a controller for all data clocking

and synchronization functions, a test signalgenerator, and a PCIe interface complete thefactory-installed functions and enable the56690 to operate as a complete turnkeysolution without the need to develop anyFPGA IP.








LNB (low-noise block)antenna signal levels withup to 60 dB gain


■ Two 200 MHz 16-bit A/Dsdigitize the I + Q signalssynchronously


■ 2 GB of DDR3 SDRAM or32 MB of QDRII+ SRAM


■ Clock/sync bus for multimodulesynchronization





VCXO

16

QDRII+SRAM8 MB


Sample ClkRef In

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus


A/D Clock/Sync

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII+ option 160

DDR3 option 165

Trigger 1

40

LVDS


200 MHz16-BIT A/D

200 MHz16-BIT A/D

1616

MAX2112

I Q

RefIn

RFIn

RefOut

12-BITD/A

2

I C2

GC

Control

Trigger 2

TIMINGGENERATOR


Ref

VIRTEX-6 FPGA


GTX

x8 PCIe

8X

FrontPanel

FrontPanel

AMCPorts 4 to 11

IPMICONTROLLER

RS-232


Pentek, Inc.


➤➤➤➤➤ RF Tuner StageA front panel SSMC connector accepts






tuner outputs are then applied to twoTexas Instruments ADS5485 200 MHz,16-bit A/D converters. The digital outputsare delivered into the Virtex-6 FPGA forsignal processing, data capture or for rout-ing to other module resources.




The timing generator uses a front panelLVPECL 26-pin clock/sync connector forone clock, two sync, and two gate/triggersignals. In the slave mode, it accepts LVPECLinputs that drive the clock, sync and gate/trigger signals within the module. In themaster mode, the LVPECL bus drives out-put timing signals to synchronize multipleslave modules, supporting synchronoussampling and sync functions across allconnected modules.







PCIe INTERFACE

fromA/D (I)

fromA/D (Q)

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX


SIGNALGENERATOR

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 40


Pentek, Inc.



56690 L-Band RF Tuner with2-Channel 200 MHz A/Dand Virtex-6 FPGA - AMC

Options:









versions

























Pentek, Inc.


General InformationModel 71760 is a member of the Onyx®

family of high-performance XMC modulesbased on the Xilinx Virtex-7 FPGA. A multi-channel, high-speed data converter, it issuitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capture features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGAprocessing IP.

It includes four A/Ds and four banks ofmemory. In addition to supporting PCIExpress Gen. 3 as a native interface, the Model71760 includes general-purpose and gigabit-serial connectors for application-specific I/O.

The Onyx ArchitectureBased on the proven design of the Pentek

Cobalt family, Onyx raises the processingperformance with the new flagship familyof Virtex-7 FPGAs from Xilinx. As the centralfeature of the board architecture, the FPGAhas access to all data and control paths,enabling factory-installed functions includingdata multiplexing, channel selection, datapacking, gating, triggering and memorycontrol. The Onyx Architecture organizesthe FPGA as a container for data processingapplications where each function exists as anintellectual property (IP) module.

Each member of the Onyx family isdelivered with factory-installed applicationsideally matched to the board’s analoginterfaces. The 71760 factory-installedfunctions include four A/D acquisition IPmodules for simplifying data capture anddata transfer.

IP modules for DDR3 SDRAM memories,a controller for all data clocking and synchro-nization functions, a test signal generator,and a PCIe interface complete the factory-installed functions and enable the 71760 tooperate as a complete turnkey solutionwithout the need to develop any FPGA IP.




with one of two FPGAs to match the specificrequirements of the processing task.Supported FPGAs are VX330T or VX690T.The VX690T features 3600 DSP48E1 slicesand is ideal for modulation/demodulation,encoding/decoding, encryption/decryption,and channelization of the signals betweentransmission and reception. For applicationsnot requiring large DSP resources or logic, thelower-cost VX330T can be installed.





VXT FPGAs■ GateXpress supports dynamic

FPGA reconfiguration acrossPCIe

■ Four 200 MHz 16-bit A/Ds■ 4 GB of DDR3 SDRAM■ Sample clock synchronization


multimodule synchronization■ PCI Express (Gen. 1, 2 & 3)

interface up to x8■ Advanced reconfigurability

features■ VITA 42.0 XMC compatible




TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

VIRTEX-7 FPGA

VX330T or VX690T


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

RF In

RFXFORMR

200 MHz16-BIT A/D

16

RF In

RFXFORMR

200 MHz16-BIT A/D

16


GigabitSerial I/O(option 105)

GTXGTX LVDSGTX


PCIeGen. 3 x8

P14PMC

P16XMC

P15XMC

4X4XCONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

48 32 32 32 32PCIeGen. 3 x8

FPGAConfigBus

GATEXPRESS PCIeCONFIGURATION

MANAGER


Pentek, Inc.


➤➤➤➤➤ GateXpress for FPGA ConfigurationThe Onyx architecture includes GateXpress,

a sophisticated FPGA-PCIe configurationmanager for loading and reloading the FPGA.At power up, GateXpress immediately pre-sents a PCIe target for the host computer todiscover, effectively giving the FPGA timeto load from FLASH. This is especially impor-tant for larger FPGAs where the loadingtimes can exceed the PCIe discovery window,typically 100 msec on most PCs.

The board’s configuration FLASH canhold four FPGA images. Images can be fac-tory-installed IP or custom IP created bythe user, and programmed into the FLASHvia JTAG using Xilinx iMPACT or throughthe board’s PCIe interface. At power up theuser can choose which image will load basedon a hardware switch setting.

Once booted, GateXpress allows the userthree options for dynamically reconfiguringthe FPGA with a new IP image. The first isthe option to load an alternate image fromFLASH through software control. The userselects the desired image and issues areload command.

The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. This isimportant in security situations where therecan be no latent user image left in nonvola-tile memory when power is removed. Inapplications where the FPGA IP may needto change many times during the course of

a mission, images can be stored on the hostcomputer and loaded through PCIe as needed.

The third option, typically used duringdevelopment, allows the user to directly loadthe FPGA through JTAG using Xilinx iMPACT.

In all three FPGA loading scenarios,GateXpress handles the hardware negotiationsimplifying and streamlining the loadingtask. In addition, GateXpress preserves thePCIe configuration space allowing dynamicFPGA reconfiguration without needing toreset the host computer to rediscover theboard. After the reload, the host simplycontinues to see the board with the expecteddevice ID.

A/D Converter StageThe front end accepts four full-scale




timing and synchronization required bythe A/D converters. It includes a clock, twosync and two gate or trigger signals. Anon-board clock generator receives an ➤



Each IP module has anassociated memory bank forbuffering data in FIFO modeor for storing data in transientcapture mode. All memory banksare supported with DMA enginesfor easily moving A/D datathrough the PCIe interface.These powerful linked-list DMAengines are capable of a uniqueAcquisition Gate Driven mode.In this mode, the length of a trans-fer performed by a link definitionneed not be known prior to dataacquisition; rather, it is governedby the length of the acquisitiongate. This is extremely useful inapplications where an externalgate drives acquisition and theexact length of that gate is notknown or is likely to vary.

For each transfer, the DMAengine can automaticallyconstruct metadata packetscontaining A/D channel ID, asample-accurate time stamp anddata length information. Theseactions simplify the hostprocessor’s job of identifyingand executing on the data.

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 48


Pentek, Inc.



71760 4-Channel 200 MHz A/Dwith Virtex-7 FPGA - XMC

Options:

-073 XC7VX330T-2 FPGA





versions

Model Description


➤ external sample clock from the frontpanel SSMC connector. This clock can beused directly by the A/D or divided by abuilt-in clock synthesizer circuit. In an alter-nate mode, the sample clock can be sourcedfrom an on-board programmable voltage-controlled crystal oscillator. In this mode,the front panel SSMC connector can beused to provide a 10 MHz reference clock forsynchronizing the internal oscillator.




independent DDR3 SDRAM memory banks.Each bank is 1 GB deep and is an integralpart of the module’s DMA capabilities,providing FIFO memory space for creatingDMA packets. Built-in memory functionsinclude multichannel A/D data capture,tagging and streaming.



VITA 42.0 XMC specification. Two connec-tors each provide dual 4X links or a single8X link with up to 10 Gb/sec per lane. Withdual XMC connectors, the 71760 supportsx8 PCIe on the first XMC connector leavingthe second connector free to support user-installed transfer protocols specific to thetarget application.


standard interface fully compliant with PCIExpress Gen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8, the interfaceincludes multiple DMA controllers forefficient transfers to and from the module.


Input Type: Transformer-coupled, frontpanel female SSMC connectorsTransformer Type: Coil Craft WBC4-6TLBFull Scale Input: +8 dBm into 50 ohms3 dB Passband: 300 kHz to 700 MHz







Field Programmable Gate ArrayStandard: Xilinx Virtex-7 XC7VX330T-2Optional: Xilinx Virtex-7 XC7VX690T-2


MemoryType: DDR3 SDRAMSize: Four banks, 1 GB eachSpeed: 800 MHz (1600 MHz DDR)

PCI-Express InterfacePCI Express Bus: Gen. 1, 2 or 3: x4 or x8Gen. 3 available only with the VX330T-2and VX690T-2 FPGAs




integrated PC developmentsystem for Pentek Cobalt andOnyx PCI Express boards (Mod-els 78xxx). It was created to saveengineers and system integratorsthe time and expense associatedwith building and testing a devel-opment system that ensuresoptimum performance of Pentekboards.


Pentek, Inc.

4-Channel 200 MHz, 16-bit A/D with Virtex-7 FPGA - x8 PCIeModel 78760


family of high-performance PCIe boardsbased on the Xilinx Virtex-7 FPGA. A multi-channel, high-speed data converter, it issuitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capture features offer an ideal turnkeysolution as well as a platform for developingand deploying custom FPGA processing IP.

It includes four A/Ds and four banks ofmemory. In addition to supporting PCIExpress Gen. 3 as a native interface, the Model78760 includes optional general-purposeand gigabit-serial connectors for application-specific I/O protocols.


Cobalt Family, Onyx raises the processingperformance with the new flagship familyof Virtex-7 FPGAs from Xilinx. As the centralfeature of the board architecture, the FPGAhas access to all data and control paths,enabling factory-installed functions includingdata multiplexing, channel selection, datapacking, gating, triggering and memorycontrol. The Onyx Architecture organizesthe FPGA as a container for data processingapplications where each function exists as anintellectual property (IP) module.

Each member of the Onyx family isdelivered with factory-installed applicationsideally matched to the board’s analoginterfaces. The 78760 factory-installedfunctions include four A/D acquisition IPmodules for simplifying data capture anddata transfer. IP modules for DDR3 SDRAMmemories, a controller for all data clocking









radio interface solution■ Supports Xilinx Virtex-7 VXT

FPGAs■ GateXpress supports dynamic




multiboard synchronization■ PCI Express (Gen. 1, 2 & 3)

interface up to x8■ Advanced reconfigurability

features■ Optional user-configurable



TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

VIRTEX-7 FPGA

VX330T or VX690T


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

RF In

RFXFORMR

200 MHz16-BIT A/D

16

RF In

RFXFORMR

200 MHz16-BIT A/D

16


68-pinHeader

x8 PCI Express

Dual 4XSerialConn


GTXGTX LVDSGTX


PCIeGen. 3 x8

4X4XCONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

48 32 32 32 32

FPGA - PCIeCONFIGURATION

MANAGER

PCIeGen. 3 x8

FPGACONFIGBUS


Pentek, Inc.














timing and synchronization required bythe A/D converters. It includes a clock, twosync and two gate or trigger signals. Anon-board clock generator receives an ➤





PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 48


Pentek, Inc.



78760 4-Channel 200 MHz A/Dwith Virtex-7 FPGA - x8PCIe

Options:





Model Description


➤ external sample clock from the frontpanel SSMC connector. This clock can beused directly by the A/D or divided by abuilt-in clock synthesizer circuit. In an alter-nate mode, the sample clock can besourced from an on-board programmablevoltage-controlled crystal oscillator. In thismode, the front panel SSMC connector canbe used to provide a 10 MHz reference clockfor synchronizing the internal oscillator.




independent DDR3 SDRAM memory banks.Each bank is 1 GB deep and is an integralpart of the board’s DMA capabilities,providing FIFO memory space for creatingDMA packets. Built-in memory functionsinclude multichannel A/D data capture,tagging and streaming.



standard interface fully compliant with PCIExpress Gen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8, the interfaceincludes multiple DMA controllers forefficient transfers to and from the board.












PCI-Express InterfacePCI Express Bus: Gen. 1, 2 or 3: x4 or x8Gen. 3 available only with the VX330T-2and VX690T-2 FPGAs






Pentek, Inc.



family of high-performance 3U VPX boardsbased on the Xilinx Virtex-7 FPGA. A multi-channel, high-speed data converter, it issuitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capture features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGAprocessing IP.

The 53760 includes four A/Ds and fourbanks of memory. It features built-in supportfor PCI Express over the 3U VPX backplane.

















multiboard synchronization■ Advanced reconfigurability

features■ Optional user-configurable







TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

VIRTEX-7 FPGA

VX330T or VX690T


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

RF In

RFXFORMR

200 MHz16-BIT A/D

16

RF In

RFXFORMR

200 MHz16-BIT A/D

16


LVDS

40

Option -104FPGAI/O

VPX BACKPLANE

VPX-P2

GTXGTXGTX

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

Option -105

4X4X

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

PCIeGen. 2 x8

CONFIGFLASH1 GB

PCIeGen. 2x8

FPGAConfigBus


MANAGER



Pentek, Inc.














timing and synchronization required bythe A/D converters. It includes a clock, twosync and two gate or trigger signals. Anon-board clock generator receives an exter-nal sample clock from the front panel ➤





PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 40


Pentek, Inc.



53760 4-Channel 200 MHz A/Dwith Virtex-7 FPGA - 3UVPX

Options:






versions

Model Description

8267 VPX Development SystemSee 8267 Datasheet forOptions

➤ SSMC connector. This clock can beused directly by the A/D or divided by abuilt-in clock synthesizer circuit. In analternate mode, the sample clock can besourced from an on-board programmablevoltage-controlled crystal oscillator. In thismode, the front panel SSMC connector canbe used to provide a 10 MHz reference clockfor synchronizing the internal oscillator.

















PCI-Express InterfacePCI Express Bus: Gen. 1 or Gen. 2: x4 or x8;


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




industry-standard interface fullycompliant with PCI Express Gen.1 and 2 bus specifications. Sup-porting PCIe links up to x8, theinterface includes multipleDMA controllers for efficienttransfers to and from the board.

Fabric-Transparent CrossbarSwitch

The 53760 features a uniquehigh-speed switching configura-tion. A fabric-transparent crossbarswitch bridges numerous inter-faces and components on theboard using gigabit serial datapaths with no latency. Program-mable signal input equalizationand output pre-emphasis set-tings enable optimization.


52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


Yes



Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.



family of high-performance 3U VPX boardsbased on the Xilinx Virtex-7 FPGA. A multi-channel, high-speed data converter, it issuitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capture features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGAprocessing IP.

The 52760 includes four A/Ds and fourbanks of memory. It features built-in supportfor PCI Express over the 3U VPX backplane.
























TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

VIRTEX-7 FPGA

VX330T or VX690T


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

RF In

RFXFORMR

200 MHz16-BIT A/D

16

RF In

RFXFORMR

200 MHz16-BIT A/D

16


LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTX

VPX-P1

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

CONFIGFLASH1 GB

FPGAConfigBus


MANAGER

PCIeGen. 2 x4

PCIeGen. 2x4

GigabitSerial I/O

Option -105

4X4X



Pentek, Inc.














timing and synchronization required bythe A/D converters. It includes a clock, twosync and two gate or trigger signals. Anon-board clock generator receives an exter-nal sample clock from the front panel ➤





PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

4X 4X 4X 40


Pentek, Inc.



52760 4-Channel 200 MHz A/Dwith Virtex-7 FPGA - 3UVPX

Options:






versions

Model Description


➤ SSMC connector. This clock can beused directly by the A/D or divided by abuilt-in clock synthesizer circuit. In analternate mode, the sample clock can besourced from an on-board programmablevoltage-controlled crystal oscillator. In thismode, the front panel SSMC connector canbe used to provide a 10 MHz reference clockfor synchronizing the internal oscillator.



















Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




industry-standard interface fullycompliant with PCI ExpressGen. 1 and 2 bus specifications.Supporting PCIe links up to x4,the interface includes multipleDMA controllers for efficienttransfers to and from the board.


52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


Yes



Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.


Models57760 & 58760


of the Onyx® family of high-performance6U OpenVPX boards based on the XilinxVirtex-7 FPGA. They consist of one ortwo Model 71760 XMC modules mountedon a VPX carrier board.





Each member of the Onyx family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces. Thefactory-installed functions of these modelsinclude four or eight A/D acquisition IPmodules for simplifying data capture anddata transfer.

IP modules for DDR3 SDRAM memories,controllers for all data clocking and synchro-

nization functions, test signal generators,and a PCIe interface complete the factory-installed functions and enable these modelsto operate as complete turnkey solutionswithout the need to develop FPGA IP.










■ Four or eight 200 MHz 16-bitA/Ds

■ 4 or 8 GB of DDR3 SDRAM■ PCI Express (Gen. 1, 2 & 3)

interface up to x8■ Sample clock synchronization






New!

New!

New!

New!

New!

LVDS

48

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P3

VIRTEX-7 FPGA

VX330T or VX690T

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

GTXGTXGTX

PCIeGen. 3 x8

4X4X

PCIeGen. 3 x8

CONFIGFLASH1 GB

PCIeGen. 3x8

FPGAConfigBus


MANAGER

VPX-P2VPX-P1

PCIe-to PCIeSWITCH

From/To

Other XMC

Module of

Model 58760

Option -105

Gigabit Serial I/O



except the PCIe-to-PCIe Switch and

provides 24 LVDS pairs from the

2nd FPGA to VPX-P5

TIMING BUSGENERATOR


200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

RF In

RFXFORMR

200 MHz16-BIT A/D

16

RF In

RFXFORMR

200 MHz16-BIT A/D

16


VCXO

Model 58760


Pentek, Inc.


Models57760 & 58760


a sophisticated FPGA-PCIe configurationmanager for loading and reloading the FPGAs.At power-up, GateXpress immediatelypresents a target for the host computerto discover, effectively giving the FPGAstime to load from FLASH. This is especiallyimportant for larger FPGAs where the load-ing times can exceed the PCIe discoverywindow, typically 100 msec on most PCs.

The board’s configuration FLASH canhold four FPGA images. Images can befactory-installed IP or custom IP created bythe user. In this case, it’s programmed intothe FLASH via JTAG using Xilinx iMPACTor through the board’s PCIe interface. Atpower-up the user can choose which imageto load based on a hardware switch setting.

Once booted, GateXpress allows the userthree options for dynamically reconfiguringthe FPGAs with new IP images. The firstoption is to load an alternate image fromFLASH through software control. The userselects the desired image and issues areload command.

The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. This isimportant in security situations where therecan be no latent user image left in nonvola-

tile memory when power is removed. Inapplications where the FPGA IP may needto change many times during the course ofa mission, images can be stored on the hostcomputer and loaded as needed.

The third option, typically used duringdevelopment, allows the user to directly loadthe FPGAs through JTAG using XilinxiMPACT.

In all three FPGA-loading scenarios,GateXpress handles the hardware negotiationthereby simplifying and streamlining theloading task. In addition, GateXpress pre-serves the PCIe configuration space allowingdynamic FPGA reconfiguration without theneed to reset the host computer so it canrediscover the board. After the reload, thehost computer simply continues to see theboard with the expected device ID.

A/D Converter StagesThe front end accepts four or eight full-

scale analog HF or IF inputs on front panelSSMC connectors at +8 dBm into 50 ohmswith transformer coupling into four oreight Texas Instruments ADS5485 200 MHz,16-bit A/D converters.

The digital outputs are delivered intothe Virtex-7 FPGAs for signal processing,data capture or for routing to other boardresources. ➤

A/D Acquisition IP ModulesThese models feature four or

eight A/D Acquisition IP Mod-ules for easily capturing andmoving data. Each IP modulecan receive data from any offour A/Ds or the test signalgenerator



PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

GigabitSerial I/O

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 4X 4X 48


Pentek, Inc.


Models57760 & 58760


57760 4-Channel 200 MHz 16-bitA/D with Virtex-7 FPGA -6U VPX

58760 8-Channel 200 MHz 16-bitA/D with two Virtex-7FPGAs - 6U VPX

Options:





versions

Model Description


➤ ➤ ➤ ➤ ➤ Clocking and SynchronizationAn internal timing bus provides all



Multiple boards can be driven from theLVPECL bus master, supporting synchronoussampling and sync functions across allconnected boards.

Memory ResourcesThe Onyx architecture supports four or

eight independent DDR3 SDRAM memorybanks. Each bank is 1 GB deep and is anintegral part of the board’s DMA capabilities,providing FIFO memory space for creatingDMA packets. Built-in memory functionsinclude multichannel A/D data capture,tagging and streaming.



standard interface fully compliant with PCIExpress Gen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the board.

SpecificationsModel 57760: 4 A/DsModel 58760: 8 A/DsFront Panel Analog Signal Inputs (4 or 8)



Sample Clock Sources: (1 or 2)On-board clock synthesizer



Timing Bus (1 or 2)26-pin front panel connector; LVPECLbus includes, clock/sync/gate/PPS in-puts and outputs; TTL signal for gate/trigger and sync/PPS inputs

External Trigger Inputs (1 or 2)Type: Front panel female SSMC connector,LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Field Programmable Gate Arrays (1 or 2)Standard: Xilinx Virtex-7 XC7VX330T-2Optional: Xilinx Virtex-7 XC7VX690T-2

Custom I/OOption -104: Provides 24 LVDS pairsbetween the FPGA and the VPX P3connector, Model 57760; P3 and P5,Model 58760Option -105: Supports serial protocolsby providing a 4X gigabit link betweenthe FPGA and VPX P2, Model 57760; orone 4X link from each FPGA to P2 andan additional 4X link between the FPGAs,Model 58760.

Memory Banks (4 or 8)Type: DDR3 SDRAMSize: 1 GB eachSpeed: 800 MHz (1600 MHz DDR)

PCI-Express InterfacePCI Express Bus: Gen. 1, 2 or 3: x4 or x8


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




Pentek, Inc.

4- or 8-Channel 200 MHz, 16-bit A/D with Virtex-7 FPGA - cPCIModels 72760,73760 and 74760


members of the Onyx® family of high-per-formance CompactPCI boards based onthe Xilinx Virtex-7 FPGA. They consist ofone or two Model 71760 XMC modulesmounted on a cPCI carrier board.



The Onyx ArchitectureThe Pentek Onyx Architecture features

Virtex-7 FPGAs. All of the board’s data andcontrol paths are accessible by the FPGA,enabling factory-installed functions includingdata multiplexing, channel selection, datapacking, gating, triggering and memorycontrol. The Onyx Architecture organizesthe FPGA as a container for data process-ing applications where each function existsas an intellectual property (IP) module.

Each member of the Onyx family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces. Thefactory-installed functions of these modelsinclude four or eight A/D acquisition IPmodules for simplifying data capture anddata transfer.

IP modules for DDR3 SDRAM memories,controllers for all data clocking and synchro-nization functions, a test signal generator,and a PCIe interface complete the factory-installed functions and enable these modelsto operate as complete turnkey solutionswithout the need to develop FPGA IP.








■ Supports Xilinx Virtex-7VXT FPGAs

■ GateXpress supports dynamicFPGA reconfiguration acrossPCI/PCI-X bus

■ Four or eight 200 MHz 16-bitA/Ds

■ Four or eight GB of DDR3SDRAM




TIMING BUSGENERATOR


VCXO


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B Timing Bus


VIRTEX-7 FPGA




MODEL 73760 INTERFACES ONLY

PCIeto PCI

BRIDGE

40

LVDS GTX

FPGA I/O(Option

-104)


J2

PCIeto PCI

BRIDGE

PCIto PCI

BRIDGE

40

From/To Other

XMC Module of

Model 74760

LVDS GTX


x4PCIe

x4PCIe

x4 PCIe

x4 PCIe


J3

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GBCONFIG

FLASH1 GB


MANAGERGATEXPRESS PCIeCONFIGURATION

MANAGER

FPGAConfigBus

FPGAConfigBus

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

200 MHz16-BIT A/D

A/D Clock/Sync Bus

1616

RF In

RFXFORMR

200 MHz16-BIT A/D

16

RF In

RFXFORMR

200 MHz16-BIT A/D

16




Pentek, Inc.



a sophisticated FPGA configuration man-ager for loading and reloading the FPGA. Atpower up, GateXpress immediately pre-sents a target for the host computer todiscover, effectively giving the FPGA timeto load from FLASH. This is especially impor-tant for larger FPGAs where the loadingtimes can exceed the PCI-X discovery window,typically 100 msec on most PCs.

The board’s configuration FLASH canhold four FPGA images. Images can befactory-installed IP or custom IP created bythe user, and programmed into the FLASHvia JTAG using Xilinx iMPACT or throughthe board’s PCI-X interface. At power upthe user can choose which image will loadbased on a hardware switch setting.


The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCI-X interface. This isimportant in security situations where therecan be no latent user image left in nonvola-

tile memory when power is removed. Inapplications where the FPGA IP may needto change many times during the course ofa mission, images can be stored on the hostcomputer and loaded as needed.


In all three FPGA loading scenarios,GateXpress handles the hardware negotiationsimplifying and streamlining the loadingtask. In addition, GateXpress preserves thePCI-X configuration space allowing dynamicFPGA reconfiguration without needing toreset the host computer to rediscover theboard. After the reload, the host simplycontinues to see the board with the expecteddevice ID.

A/D Converter StageThe front end accepts four or eight full-

scale analog HF or IF inputs on front panelSSMC connectors at +8 dBm into 50 ohmswith transformer coupling into four oreight Texas Instruments ADS5485 200 MHz,16-bit A/D converters.

The digital outputs are delivered intothe Virtex-7 FPGA for signal processing,data capture or for routing to other boardresources. ➤

A/D Acquisition IP ModulesThese models feature four or

eight A/D Acquisition IP Mod-ules for easily capturing andmoving data. Each IP modulecan receive data from any offour A/Ds or the test signalgenerator



PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

PCIe FPGAI/O


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

4X 40


Pentek, Inc.





74760 8-Channel 200 MHz 16-bitA/D with two Virtex-7FPGAs - 6U cPCI

Options:




➤ ➤ ➤ ➤ ➤ Clocking and SynchronizationAn internal timing bus provides all



Multiple boards can be driven from theLVPECL bus master, supporting synchronoussampling and sync functions across allconnected boards.






SpecificationsModel 72760 or Model 73760: 4 A/DsModel 74760: 8 A/DsFront Panel Analog Signal Inputs (4 or 8)



Sample Clock Sources: (1 or 2)On-board clock synthesizer



Timing Bus (1 or 2)26-pin front panel connector; LVPECLbus includes, clock/sync/gate/PPS in-puts and outputs; TTL signal for gate/trigger and sync/PPS inputs

External Trigger Inputs (1 or 2)Type: Front panel female SSMC connector,LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS


Custom I/OOption -104: provides 20 LVDS pairsbetween the FPGA and the J2 connector,Model 73760; J3 connector, Model 72760;J3 and J5 connectors, Model 74760

Memory Banks (1 or 2)Type: DDR3 SDRAMSize: Four banks, 1 GB eachSpeed: 800 MHz (1600 MHz DDR)





Pentek, Inc.



family of high-performance AMC modulesbased on the Xilinx Virtex-7 FPGA. A multi-channel, high-speed data converter, it issuitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capture features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGAprocessing IP.

It includes four A/Ds and four banks ofmemory. In addition to supporting PCIExpress Gen. 3 as a native interface, theModel 56760 includes a front panelgeneral-purpose connector for application-specific I/O.



Each member of the Onyx family isdelivered with factory-installed applicationsideally matched to the board’s analoginterfaces. The 56760 factory-installedfunctions include four A/D acquisition IP

modules for simplifying data capture anddata transfer.

IP modules for DDR3 SDRAM memories,a controller for all data clocking and synchro-nization functions, a test signal generator,and a PCIe interface complete the factory-installed functions and enable the 56760 tooperate as a complete turnkey solutionwithout the need to develop any FPGA IP.










■ Four 200 MHz 16-bit A/Ds■ 4 GB of DDR3 SDRAM■ Sample clock synchronization to






TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

VIRTEX-7 FPGA

VX330T or VX690T


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

RF In

RFXFORMR

200 MHz16-BIT A/D

16

RF In

RFXFORMR

200 MHz16-BIT A/D

16


LVDSGTX


PCIeGen. 3 x8

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

48 32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

FrontPanel

FrontPanel

Ports 4 to 11

IPMICONTROLLER

RS-232

AMC


Pentek, Inc.




The board’s configuration FLASH canhold four FPGA images. Images can befactory-installed IP or custom IP created bythe user, and programmed into the FLASHvia JTAG using Xilinx iMPACT or throughthe board’s PCIe interface. At power up theuser can choose which image will load basedon a hardware switch setting.










timing and synchronization required bythe A/D converters. It includes a clock, twosync and two gate or trigger signals. Anon-board clock generator receives ➤





PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

PCIe FPGAGPIO


MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 2


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 3

A/D

ACQUISITION

IP MODULE 4



DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

METADATAGENERATOR

MUX MUX


SIGNALGENERATOR

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 3

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

8X 48


Pentek, Inc.


➤ an external sample clock from the frontpanel SSMC connector. This clock can beused directly by the A/D or divided by abuilt-in clock synthesizer circuit. In analternate mode, the sample clock can besourced from an on-board programmablevoltage-controlled crystal oscillator. In thismode, the front panel SSMC connectorcan be used to provide a 10 MHz referenceclock for synchronizing the internal oscillator.




independent DDR3 SDRAM memory banks.Each bank is 1 GB deep and is an integralpart of the module’s DMA capabilities, pro-viding FIFO memory space for creating DMApackets. Built-in memory functions include anA/D data transient capture mode and D/Awaveform playback mode.

In addition to the factory-installed func-tions, custom user- installed IP within theFPGA can take advantage of the memoriesfor many other purposes.




standard interface fully compliant with PCIExpress Gen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8, the interfaceincludes multiple DMA controllers for effi-cient transfers to and from the module.












PCI-Express InterfacePCI Express Bus: Gen. 1, 2 or 3: x4 or x8;Gen. 3 available only with the VX330T-2and VX690T-2 FPGAs





56760 4-Channel 200 MHz A/Dwith Virtex-7 FPGA - AMC

Options:





versions


Pentek, Inc.



family of high performance XMC modulesbased on the Xilinx Virtex-7 FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communi-cations or radar system. Its built-in datacapture and playback features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGAprocessing IP.

It includes 1 GHz A/D and D/A convert-ers and four banks of memory. In additionto supporting PCI Express Gen. 3 as anative interface, the Model 71730 includesoptional general purpose and gigabit serialcard connectors for application-specific I/O.



Each member of the Onyx family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 71730 factory-installed functionsinclude an A/D acquisition and a D/A wave-form playback IP module for simplifyingdata capture and data transfer.

IP modules for DDR3 SDRAM memories,a controller for all data clocking and synchro-nization functions, a test signal generatorand a PCIe interface complete the factory-installed functions and enable the 71730 tooperate as a complete turnkey solution, with-out the need to develop any FPGA IP.











■ One 1 GHz 12-bit A/D■ One 1 GHz 16-bit D/A

■ 4 GB of DDR3 SDRAM■ Sample clock synchronization to


for multimodule synchronization■ PCI Express (Gen. 1, 2 & 3)





TIMING BUSGENERATOR


VCXO

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

RF In

RFXFORMR

1 GHz12-BIT A/D

12Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

VIRTEX-7 FPGA

VX330T or VX690T


GTXGTX LVDSGTX


PCIeGen. 3 x8

P14PMC

P16XMC

P15XMC

4X4XCONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

48 32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER


Pentek, Inc.







PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A


FPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

8X 4X 4X 48




A/D Converter StageThe front end accepts an analog HF or


The digital outputs are delivered into theVirtex-7 FPGA for signal processing, data cap-ture or for routing to other module resources.


16-bit D/A. The converter has an inputsample rate of 1 GS/sec, allowing it to acceptfull-rate data from the FPGA. Additionally,the D/A includes a 2x or 4x interpolationfilter for applications that provide 1/2 or 1/4rate input data. Analog output is through afront panel SSMC connector. ➤










Pentek, Inc.



71730 1 GHz A/D and D/A,Virtex-7 FPGA - XMC

Options:






versions

Model Description


➤➤➤➤➤ Clocking and SynchronizationTwo internal timing buses provide either


Each timing bus includes a clock, syncand a gate or trigger signal. An on-boardclock generator receives a sample clock eitherfrom the front panel SSMC connector orfrom an on-board programmable VCXO(Voltage-Controlled Crystal Oscillator). Inthis latter mode, the front panel SSMC con-nector can be used to provide a 10 MHzreference clock to phase-lock the VCXO.Either clock source (front panel or VCXO)can be used directly or can be dividedindependently by 2, 4, 8, or 16 to providedifferent lower frequency A/D and D/Aclocks.







standard interface fully compliant with PCIExpress Gen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the module.

















XMC InterfaceThe Model 71730 complies

with the VITA 42.0 XMC specifi-cation. Two connectors eachprovide dual 4X links or a single8X link with up to 10 Gb/secper lane. With dual XMC con-nectors, the 71730 supports x8PCIe on the first XMC connectorleaving the second connector freeto support user-installed trans-fer protocols specific to thetarget application.


integrated PC developmentsystem for Pentek Cobalt andOnyx PCI Express boards (Mod-els 78xxx). It was created to saveengineers and system integratorsthe time and expense associatedwith building and testing a devel-opment system that ensuresoptimum performance of Pentekboards.


Pentek, Inc.



family of high-performance PCIe boardsbased on the Xilinx Virtex-7 FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communi-cations or radar system. Its built-in datacapture and playback features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGAprocessing IP.

It includes 1 GHz A/D and 1 GHz D/Aconverters and four banks of memory. In addi-tion to supporting PCI Express Gen. 3 as anative interface, the Model 78730 includesoptional general-purpose and gigabit serial cardconnectors for application specific I/O.















■ One 1 GHz 12-bit A/D■ One 1 GHz 16-bit D/A

■ 4 GB of DDR3 SDRAM■ Sample clock synchronization to


for multimodule synchronization■ PCI Express (Gen. 1, 2 & 3)




TIMING BUSGENERATOR


VCXO

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

RF In

RFXFORMR

1 GHz12-BIT A/D

12Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

VIRTEX-7 FPGA

VX330T or VX690T

GTX

PCIeGen. 3 x8

P15XMC

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

Dual 4XSerialConn


GTXGTX LVDS


4X4X 48

68-pinHeader


Pentek, Inc.






The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. This isimportant in security situations where therecan be no latent user image left in nonvola-tile memory when power is removed. Inapplications where the FPGA IP may needto change many times during the course ofa mission, images can be stored on the hostcomputer and loaded through PCIe as needed.

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A


FPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

8X 4X 4X 48







GHz, 16-bit D/A. The converter has an in-put sample rate of 1 GSPS, allowing it toacept full rate data from the FPGA. Addi-tionally, the D/A includes a 2x or 4xinterpolation filter for applications that pro-vide 1/2 or 1/4 rate input data. Analogoutput is through a front panel SSMCconnector. ➤










Pentek, Inc.




Each timing bus includes a clock, syncand a gate or trigger signal. An on-boardclock generator receives a sample clock eitherfrom the front panel SSMC connector orfrom an on-board programmable VCXO(Voltage-Controlled Crystal Oscillator). Inthis latter mode, the front panel SSMC con-nector can be used to provide a 10 MHzreference clock to phase-lock the VCXO.Either clock source (front panel or VCXO)can be used directly or can be divided inde-pendently by 2, 4, 8, or 16 to provide differentlower frequency A/D and D/A clocks.











D/A ConverterType: Texas Instruments DAC5681ZInput Data Rate: 1 GHz max.

Interpolation Filter: bypass, 2x or 4xOutput Sampling Rate: 1 GHz max.Resolution: 16 bits
















78730 1 GHz A/D and D/A,Virtex-7 FPGA - x8 PCIe

Options:






versions

Model Description



Pentek, Inc.















TIMING BUSGENERATOR


VCXO

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

RF In

RFXFORMR

1 GHz12-BIT A/D

12Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

VIRTEX-7 FPGA

VX330T or VX690T

LVDS

40

Option -104FPGAI/O

VPX BACKPLANE

VPX-P2

GTXGTXGTX

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

Option -105

4X4X

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

PCIeGen. 2 x8

CONFIGFLASH1 GB

PCIeGen. 2x8

FPGAConfigBus


MANAGER




■ GateXpress supports dynamicFPGA reconfiguration acrossPCIe

■ One 1 GHz 12-bit A/D

■ One 1 GHz 16-bit D/A■ 4 GB of DDR3 SDRAM■ Sample clock synchronization to



interface up to x8■ Optional LVDS connections








Pentek, Inc.







PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A


FPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

8X 4X 4X 40







16-bit D/A. The converter has an inputsample rate of 1 GSPS, allowing it to aceptfull rate data from the FPGA. Additionally,the D/A includes a 2x or 4x interpolationfilter for applications that provide 1/2 or 1/4rate input data. Analog output is througha front panel SSMC connector. ➤










Pentek, Inc.






Crossbar SwitchThe 53730 features a unique high-speed

switching configuration. A fabric-transparentcrossbar switch bridges numerous interfacesand components on the board using gigabitserial data paths with no latency. Program-mable signal input equalization and outputpre-emphasis settings enable optimization.







Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO or front panel ex-ternal clockVCXO Frequency Ranges: 10 to 945MHz, 970 to 1134 MHz, and 1213 to1417 MHzSynchronization: VCXO can be phase-locked to an external 4 to 200 MHz systemreference, typically 10 MHz

Clock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16, indepen-dently for the A/D clock and D/A clock





Custom I/OOption -104: Provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/OOption -105: Provides one 8X or two4X gigabit links between the FPGA andthe VPX P1 to support serial protocols


PCI-Express InterfacePCI Express Bus: Gen. 1 or Gen. 2: x4 or x8;


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


Yes



Lowest Price

Two x4 or one x8

No

Yes No

Memory ResourcesThe 53730 architecture supports

four independent DDR3 SDRAMmemory banks. Each bank is 1 GBdeep and is an integral part of theboard’s DMA capabilities, provid-ing FIFO memory space forcreating DMA packets.


industry-standard interface fullycompliant with PCI Express Gen.1 & 2 bus specifications. Sup-porting PCIe links up to x8, theinterface includes multipleDMA controllers for efficienttransfers to and from the board.



Options:






versions

Model Description





Pentek, Inc.















TIMING BUSGENERATOR


VCXO

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

RF In

RFXFORMR

1 GHz12-BIT A/D

12Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

VIRTEX-7 FPGA

VX330T or VX690T

LVDS

48

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTX

VPX-P1

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

PCIeGen. 2 x4

CONFIGFLASH1 GB

PCIeGen. 2x4

FPGAConfigBus


MANAGER

GTXGTX

GigabitSerial I/O

Option -105

4X4X








for multiboard synchronization■ PCI Express (Gen. 1 and 2)

interface up to x4■ Optional LVDS connections








Pentek, Inc.







PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A


FPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

4X 4X 4X 48







16-bit D/A. The converter has an inputsample rate of 1 GSPS, allowing it to aceptfull rate data from the FPGA. Additionally,the D/A includes a 2x or 4x interpolationfilter for applications that provide 1/2 or 1/4rate input data. Analog output is througha front panel SSMC connector. ➤










Pentek, Inc.




Options:






versions

Model Description













Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO or front panel ex-ternal clockVCXO Frequency Ranges: 10 to 945MHz, 970 to 1134 MHz, and 1213 to1417 MHzSynchronization: VCXO can be phase-locked to an external 4 to 200 MHz systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16, indepen-dently for the A/D clock and D/A clock









Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


Yes



Lowest Price

Two x4 or one x8

No

Yes No

Memory ResourcesThe 52730 architecture sup-

ports four independent DDR3SDRAM memory banks. Eachbank is 1 GB deep and is anintegral part of the board’sDMA capabilities, providingFIFO memory space for creatingDMA packets. Built-in memoryfunctions include multichannelA/D data capture, tagging andstreaming.


industry-standard interface fullycompliant with PCI ExpressGen. 1 & 2 bus specifications.Supporting PCIe links up to x4,the interface includes multipleDMA controllers for efficienttransfers to and from the board.




Pentek, Inc.


Models57730 & 58730


of the Onyx® family of high-performance6U OpenVPX boards based on the XilinxVirtex-7 FPGA. They consist of one ortwo Model 71730 XMC modules mountedon a VPX carrier board.





Each member of the Onyx family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces. Thefactory-installed functions of these modelsinclude one or two A/D acquisition and oneor two D/A waveform playback IP modulesfor simplifying data capture and data transfer.

IP modules for DDR3 SDRAM memories,controllers for all data clocking and synchro-nization functions, test signal generators,

and a PCIe interface complete the factory-installed functions and enable these modelsto operate as complete turnkey solutionswithout the need to develop FPGA IP.







New!

New!

New!

New!

New!




■ One or two 1 GHz 12-bit A/D■ One or two 1 GHz 16-bit D/A

■ 4 or 8 GB of DDR3 SDRAM■ Sample clock synchronization to

an external system reference■ PCI Express (Gen. 1, 2 & 3)

interface up to x8■ Dual-µSync clock/sync bus

for multiboard synchronization■ Optional user-configurable




LVDS

48

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P3

VIRTEX-7 FPGA

VX330T or VX690T

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

GTXGTXGTX

PCIeGen. 3 x8

4X4X

PCIeGen. 3 x8

CONFIGFLASH1 GB

PCIeGen. 3x8

FPGAConfigBus


MANAGER

VPX-P2VPX-P1

PCIe-to PCIeSWITCH

From/To

Other XMC

Module of

Model 58730

Option -105

Gigabit Serial I/O



except the PCIe-to-PCIe Switch and

provides 24 LVDS pairs from the

2nd FPGA to VPX-P5

TIMING BUSGENERATOR


VCXO

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

RF In

RFXFORMR

1 GHz12-BIT A/D

12Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

Model 58730


Pentek, Inc.


Models57730 & 58730


a sophisticated FPGA-PCIe configurationmanager for loading and reloading the FPGAs.At power-up, GateXpress immediatelypresents a target for the host computerto discover, effectively giving the FPGAstime to load from FLASH. This is especiallyimportant for larger FPGAs where the load-ing times can exceed the PCIe discoverywindow, typically 100 msec on most PCs.

The board’s configuration FLASH canhold four FPGA images. Images can befactory-installed IP or custom IP created bythe user. In this case, it’s programmed intothe FLASH via JTAG using Xilinx iMPACTor through the board’s PCIe interface. Atpower-up the user can choose which imageto load based on a hardware switch setting.

Once booted, GateXpress allows the userthree options for dynamically reconfiguringthe FPGAs with new IP images. The firstoption is to load an alternate image fromFLASH through software control. The userselects the desired image and issues areload command.

The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. This isimportant in security situations where therecan be no latent user image left in nonvola-tile memory when power is removed. Inapplications where the FPGA IP may needto change many times during the course ofa mission, images can be stored on the hostcomputer and loaded as needed.

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A


FPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

8X 4X 4X 48

The third option, typically used duringdevelopment, allows the user to directly loadthe FPGAs through JTAG using XilinxiMPACT.

In all three FPGA-loading scenarios,GateXpress handles the hardware negotiationthereby simplifying and streamlining theloading task. In addition, GateXpress pre-serves the PCIe configuration space allowingdynamic FPGA reconfiguration without theneed to reset the host computer so it canrediscover the board. After the reload, thehost computer simply continues to see theboard with the expected device ID.

A/D Converter StagesThe front end accepts one or two ana-

log HF or IF inputs on front panel SSMCconnectors with transformer couplinginto one or two Texas InstrumentsADS5400 1 GHz, 12-bit A/D converters.

The digital outputs are delivered intothe Virtex-7 FPGAs for signal processing,data capture or for routing to other boardresources.

D/A Converter StagesThese models feature one or two TI

DAC5681Z 1 GHz, 16-bit D/As. The convert-ers have an input sample rate of 1 GSPS,allowing them to acept full rate data fromthe FPGA. Additionally, the D/As includea 2x or 4x interpolation filter for applicationsthat provide 1/2- or 1/4-rate input data.Analog output is through front panel SSMCconnectors. ➤










Pentek, Inc.


Models57730 & 58730



Each timing bus includes a clock, syncand a gate or trigger signal. An on-boardclock generator receives a sample clock eitherfrom the front panel SSMC connector orfrom an on-board programmable VCXO(Voltage-Controlled Crystal Oscillator). Inthis latter mode, the front panel SSMCconnector can be used to provide a 10 MHzreference clock to phase-lock the VCXO.Either clock source (front panel or VCXO)can be used directly or can be dividedindependently by 2, 4, 8, or 16 to providedifferent lower frequency A/D and D/Aclocks.


The Pentek Model 9192 Cobalt or OnyxSynchronizer can drive multiple µSyncconnectors enabling large, multichannelsynchronous configurations. Also, an LVTTLexternal gate/trigger input is accepted on afront panel SSMC connector.




SpecificationsModel 57730: 1 A/D, 1 D/AModel 58730: 2 A/Ds, 2 D/AsFront Panel Analog Signal Inputs (1 or 2)








Timing Bus (1 or 2): 19-pin µSync bus con-nector includes sync and gate/triggerinputs, CML



Custom I/O (1 or 2)Option -104: Provides 24 LVDS pairsbetween the FPGA and the VPX P3connector, Model 57730; P3 and P5,Model 58730Option -105: Supports serial protocolsby providing a 4X gigabit link betweenthe FPGA and VPX P2, Model 57730; orone 4X link from each FPGA to P2 andan additional 4X link between the FPGAs,Model 58730

Memory Banks (4 or 8)Type: DDR3 SDRAMSize: 1 GB eachSpeed: 800 MHz (1600 MHz DDR)



Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

PCI Express InterfaceThese models include an

industry-standard interface fullycompliant with PCI ExpressGen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8,the interface includes multipleDMA controllers for efficienttransfers to and from the board.


57730 1 GHz A/D and D/A withVirtex-7 FPGA - 6U VPX

58730 Two 1 GHz A/Ds andD/As, with two Virtex-7FPGAs - 6U VPX

Options:



-105 Gigabit link between theFPGA and P2 connector,Model 57730; gigabitlinks from each FPGA toP2 connector, Model 78730


versions

Model Description





Pentek, Inc.


Models 72730,73730 and 74730


members of the Onyx® family of high per-formance CompactPCI boards based onthe Xilinx Virtex-7 FPGA. They consist ofone or two Model 71730 XMC modulesmounted on a cPCI carrier board.





Each member of the Onyx family is deliv-ered with factory-installed applications ideallymatched to the board’s analog interfaces. Thefactory-installed functions of these modelsinclude ne or two A/D acquisition and oneor two D/A waveform playback IP modulesfor simplifying data capture and data transfer.

IP modules for DDR3 SDRAM memories,controllers for all data clocking and synchro-nization functions, a test signal generator,and a PCIe interface complete the factory-installed functions and enable these modelsto operate as complete turnkey solutionswithout the need to develop FPGA IP.









FPGA reconfiguration acrossPCI/PCI-X bus

■ One or two 1 GHz 12-bit A/D■ One or two 1 GHz 16-bit D/A■ Four or eight GB of DDR3

SDRAM■ Sample clock synchronization to


for multimodule synchronization■ Optional LVDS connections


VIRTEX-7 FPGA





PCIeto PCI

BRIDGE

40

LVDS GTX

FPGA I/O(Option

-104)


J2

PCIeto PCI

BRIDGE

PCIto PCI

BRIDGE

40

From/To Other

XMC Module of

Model 74730

LVDS GTX


x4PCIe

x4PCIe

x4 PCIe

x4 PCIe


J3

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GBCONFIG

FLASH1 GB


MANAGERGATEXPRESS PCIeCONFIGURATION

MANAGER

FPGAConfigBus

FPGAConfigBus

TIMING BUSGENERATOR


D/A Clock/Sync Bus

VCXO

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

RF In

RFXFORMR

1 GHz12-BIT A/D

12

Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync



Pentek, Inc.


Models 72730,73730 and 74730


a sophisticated FPGA configuration man-ager for loading and reloading the FPGA. Atpower up, GateXpress immediately pre-sents a target for the host computer todiscover, effectively giving the FPGA timeto load from FLASH. This is especially impor-tant for larger FPGAs where the loadingtimes can exceed the PCI-X discovery window,typically 100 msec on most PCs.

The board’s configuration FLASH canhold four FPGA images. Images can befactory-installed IP or custom IP created bythe user, and programmed into the FLASHvia JTAG using Xilinx iMPACT or throughthe board’s PCI-X interface. At power upthe user can choose which image will loadbased on a hardware switch setting.


The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCI-X interface. This isimportant in security situations where therecan be no latent user image left in nonvola-tile memory when power is removed. Inapplications where the FPGA IP may needto change many times during the course ofa mission, images can be stored on the hostcomputer and loaded as needed.

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A

PCIeFPGA

I/O


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

4X 40


In all three FPGA loading scenarios,GateXpress handles the hardware negotiationsimplifying and streamlining the loadingtask. In addition, GateXpress preserves thePCI-X configuration space allowing dynamicFPGA reconfiguration without needing toreset the host computer to rediscover theboard. After the reload, the host simplycontinues to see the board with the expecteddevice ID.

A/D Converter StageThe front end accepts one or two ana-

log HF or IF input on front panel SSMCconnectors with transformer couplinginto one or two Texas InstrumentsADS5400 1 GHz, 12-bit A/D converters.


D/A Converter StageThese models feature one or two TI

DAC5681Z 1 GHz, 16-bit D/As. The convert-ers have an input sample rate of 1 GSPS,allowing them to acept full rate data fromthe FPGA. Additionally, the D/As includea 2x or 4x interpolation filter for applica-tions that provide 1/2 or 1/4 rate input data.Analog output is through front panel SSMCconnectors. ➤










Pentek, Inc.


Models 72730,73730 and 74730



Each timing bus includes a clock, syncand a gate or trigger signal. An on-boardclock generator receives a sample clock eitherfrom the front panel SSMC connector orfrom an on-board programmable VCXO(Voltage-Controlled Crystal Oscillator). Inthis latter mode, the front panel SSMC con-nector can be used to provide a 10 MHzreference clock to phase-lock the VCXO.Either clock source (front panel or VCXO)can be used directly or can be dividedindependently by 2, 4, 8, or 16 to providedifferent lower frequency A/D and D/Aclocks.






SpecificationsModel 72730 or Model 73730: 1 A/D, 1 D/AModel 74730: 2 A/Ds, 2 D/AsFront Panel Analog Signal Inputs (1 or 2)
















PCI-X InterfaceThese models include an

industry-standard interfacefully compliant with PCI-X busspecifications. The interfaceincludes multiple DMA control-lers for efficient transfers to andfrom the board. Data widths of32 or 64 bits and data rates of 33and 66 MHz are supported.Model 73730: 32 bits only.




74730 Two 1 GHz A/D and D/A,Virtex-7 FPGA - 6U cPCI

Options:





Pentek, Inc.



family of high performance AMC modulesbased on the Xilinx Virtex-7 FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communi-cations or radar system. Its built-in datacapture and playback features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGAprocessing IP.

It includes 1 GHz A/D and D/A convert-ers and four banks of memory. In additionto supporting PCI Express Gen.3 as a nativeinterface, the Model 56730 includes a frontpanel general-purpose connector for appli-cation-specific I/O .



Each member of the Onyx family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 56730 factory-installed functionsinclude an A/D acquisition and a D/A wave-








for multiboard synchronization■ PCI Express (Gen. 1, 2 & 3)




TIMING BUSGENERATOR


VCXO

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

RF In

RFXFORMR

1 GHz12-BIT A/D

12Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

VIRTEX-7 FPGA

VX330T or VX690T

LVDSGTX


PCIeGen. 3 x8

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

48 32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

FrontPanel

FrontPanel

Ports 4 to 11

IPMICONTROLLER

RS-232

AMC

form playback IP module for simplifyingdata capture and data transfer.








Pentek, Inc.







PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D

toD/A

PCIeFPGAGPIO


D/A loopback

MemoryBank 1

MemoryBank 2

MemoryBank 3

MemoryBank 4


A/D

ACQUISITION

IP MODULE


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 2

toMem

Bank 1

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROLLER

8X 48







16-bit D/A. The converter has an inputsample rate of 1 GSPS, allowing it to aceptfull rate data from the FPGA. Additionally,the D/A includes a 2x or 4x interpolationfilter for applications that provide 1/2 or 1/4rate input data. Analog output is through afront panel SSMC connector. ➤










Pentek, Inc.








independent DDR3 SDRAM memory banks.Each bank is 1 GB deep and is an integralpart of the module’s DMA capabilities,providing FIFO memory space for creatingDMA packets. Built-in memory functionsinclude an A/D data transient capture modeand D/A waveform playback mode.

In addition to the factory-installed func-tions, custom user- installed IP within theFPGA can take advantage of the memoriesfor many other purposes.














PCI-Express InterfacePCI Express Bus: Gen. 1, 2 or 3: x4 or x8;





56730 1 GHz A/D and D/A,Virtex-7 FPGA - AMC

Options:



-104 LVDS FPGA I/O to frontpannel connector


versions

AMC InterfaceThe Model 56730 complies

with the AMC.1 specification byproviding an x8 PCIe connectionto AdvancedTCA carriers orµTCA chassis. Module manage-ment is provided by an IPMI 2.0MMC (Module ManagementController).


industry-standard interface fullycompliant with PCI Express Gen.1, 2 and 3 bus specifications. Sup-porting PCIe links up to x8, theinterface includes multiple DMAcontrollers for efficient transfersto and from the module.


Pentek, Inc.

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC,Virtex-7 FPGA - XMCModel 71741


family of high-performance XMC modulesbased on the Xilinx Virtex-7 FPGA. A high-speed data converter with a programmabledigital downconverter, it is suitable for con-nection to HF or IF ports of a communicationsor radar system. Its built-in data capturefeatures offer an ideal turnkey solution.

It includes a 3.6 GHz, 12-bit A/D con-verter and four banks of memory. In additionto supporting PCI Express Gen. 3 as a nativeinterface, Model 71741 includes an optionalconnection to the Virtex-7 FPGA for customI/O .



Each member of the Onyx family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 71741 factory-installed functionsinclude an A/D acquisition IP module anda programmable digital downconverter. Inaddition, IP modules for DDR3 SDRAM














■ Programmable one- or two-channel DDC (DigitalDownconverter)

■ 4 GB of DDR3 SDRAM■ µSync clock/sync bus for





TIMING BUSGENERATOR


Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

RF In

RFXFORMR



12

TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

VIRTEX-7 FPGA

VX330T or VX690T

GTX

PCIeGen. 3 x8

P15XMC

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER


GTXGTX LVDS


P14PMC

P16XMC

4X4X 48


Pentek, Inc.






The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. This isimportant in security situations wherethere can be no latent user image left innonvolatile memory when power is removed.In applications where the FPGA IP mayneed to change many times during thecourse of a mission, images can be storedon the host computer and loaded throughPCIe as needed. ➤




For each transfer, the DMAengine can automatically constructmetadata packets containing asample-accurate time stamp anddata length information. Theseactions simplify the hostprocessor’s job of identifyingand executing on the data.

DDC IP CoresWithin the FPGA is a powerful DDC IP

core. The core supports a single-channelmode, accepting data samples from theA/D at the full 3.6 GHz rate. Additionally,a dual-channel mode supports the A/D’s1.8 GHz two-channel operation .

In dual-channel mode, each DDC hasan independent 32-bit tuning frequencysetting that ranges from DC to ƒs, where ƒsis the A/D sampling frequency.

In single-channel mode, decimationcan be programmed to 8x, 16x or 32x. Indual-channel mode, both channels sharethe same decimation rate, programmableto 4x, 8x or 16x.

The decimating filter for each DDCaccepts a unique set of user-supplied 16-bitcoefficients. The 80% default filters deliveran output bandwidth of 0.8*ƒs/N, whereN is the decimation setting. The rejection ofadjacent-band components within the80% output bandwidth is better than 100 dB.Each DDC delivers a complex output streamconsisting of 16-bit I + 16-bit Q samples ata rate of ƒs/N.

PCIe INTERFACE

fromA/D

PCIe


A/D

ACQUISITION

IP MODULE

MUX


SIGNALGENERATOR

MEMORYCONTROLLER

8XtoMem

Bank 2

toMem

Bank 1

fromA/D


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3

*Two channel mode shown.Programmable decimation of 8, 16 or 32

available in one channel mode.

DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE

DATA PACKING &FLOW CONTROL

A/D

ACQUISITION

IP MODULE

MUX


DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


METADATAGENERATOR

METADATAGENERATOR

GigabitSerial I/O

FPGAGPIO


4X 4X 48


Pentek, Inc.



71741 1-Ch. 3.6 GHz or 2-Ch.1.8 GHz, 12-bit A/D withWideband DDC, Virtex-7FPGA - XMC

Options:






versions

Model Description


➤ The third option, typically used duringdevelopment, allows the user to directly loadthe FPGA through JTAG using Xilinx iMPACT.


A/D Converter StageThe front end accepts analog HF or IF in-

puts on a pair of front panel SSMC connectorswith transformer coupling into a Texas Instru-ments ADC12D1800 12-bit A/D. The converteroperates in single-channel interleaved modewith a sampling rate of 3.6 GHz and an inputbandwidth of 1.75 GHz; or, in dual-channelmode with a sampling rate of 1.8 GHz andinput bandwidth of 2.8 GHz.

The ADC12D1800 provides a program-mable 15-bit gain adjustment allowing the71741 to have a full scale input range of+2 dBm to +4 dBm. A built-in AutoSyncfeature supports A/D synchronizationacross multiple modules.





sample clock via a front panel SSMC connec-tor. A second front panel SSMC accepts a TTLsignal that can function as Gate, PPS or Sync.

A front panel µSync bus connector allowsmultiple modules to be synchronized, idealfor multichannel systems. The µSync busincludes gate, reset, and in and out refer-ence clock signals. Two 71741’s can besynchronized with a simple cable. Forlarger systems, multiple 71741’s can besynchronized using the Model 7192 high-speed sync module to drive the sync bus.




Digital DownconvertersModes: One or two channels,programmableSupported Sample Rate: One-channelmode: 3.6 GHz, two-channel mode:1.8 GHzDecimation Range: One-channel mode:8x, 16x or 32x, two-channel mode: 4x,8x, or 16xLO Tuning Freq. Resolution: 32 bits,0 to ƒsLO SFDR: >120 dBPhase Offset Resolution: 32 bits,0 to 360 degreesFIR Filter: User-programmable 18-bitcoefficientsDefault Filter Set: 80% bandwidth,<0.3 dB passband ripple, >100 dBstopband attenuation

Sample Clock Source: Front panel SSMCconnector












ports four independent DDR3SDRAM memory banks. Eachbank is 1 GB deep and is anintegral part of the module’sDMA capabilities, providingFIFO memory space for creatingDMA packets. Built-in memoryfunctions include multichannelA/D data capture, tagging andstreaming.


Pentek, Inc.

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC,Virtex-7 FPGA - x8 PCIeModel 78741


family of high-performance PCIe modulesbased on the Xilinx Virtex-7 FPGA. A high-speed data converter with a programmabledigital downconverter, it is suitable for con-nection to HF or IF ports of a communicationsor radar system. Its built-in data capturefeatures offer an ideal turnkey solution.

It includes a 3.6 GHz, 12-bit A/D con-verter and four banks of memory. In additionto supporting PCI Express Gen. 3 as a nativeinterface, Model 78741 includes an optionalconnection to the Virtex-7 FPGA forcustom I/O.



Each member of the Onyx family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 78741 factory-installed functionsinclude an A/D acquisition IP module anda programmable digital downconverter. Inaddition, IP modules for DDR3 SDRAMmemories, a controller for all data clocking

and synchronization functions, a test signalgenerator and a PCIe interface completethe factory-installed functions and enablethe 78741 to operate as a complete turnkeysolution, without the need to develop anyFPGA IP.



















TIMING BUSGENERATOR


Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

RF In

RFXFORMR



12

TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

VIRTEX-7 FPGA

VX330T or VX690T

GTX

PCIeGen. 3 x8

P15XMC

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGERGigabitSerial I/O(option 105)

GTXGTX LVDS


4X4X 48

Dual 4XSerialConn

68-pinHeader


Pentek, Inc.






The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. This isimportant in security situations wherethere can be no latent user image left innonvolatile memory when power is removed.In applications where the FPGA IP mayneed to change many times during thecourse of a mission, images can be stored ➤










PCIe INTERFACE

fromA/D

PCIe


A/D

ACQUISITION

IP MODULE

MUX


SIGNALGENERATOR

MEMORYCONTROLLER

8XtoMem

Bank 2

toMem

Bank 1

fromA/D


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3



DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


A/D

ACQUISITION

IP MODULE

MUX


DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


METADATAGENERATOR

METADATAGENERATOR

GigabitSerial I/O

FPGAGPIO


4X 4X 48


Pentek, Inc.




Options:






versions

Model Description


➤ on the host computer and loaded throughPCIe as needed.



A/D Converter StageThe front end accepts analog HF or IF


The ADC12D1800 provides a program-mable 15-bit gain adjustment allowing the78741 to have a full scale input range of+2 dBm to +4 dBm. A built-in AutoSyncfeature supports A/D synchronizationacross multiple boards.


standard interface fully compliant with PCIExpress Gen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the board



A front panel µSync bus connector allowsmultiple boards to be synchronized, ideal formultichannel systems. The µSync busincludes gate, reset, and in and out refer-ence clock signals. Two 78741’s can besynchronized with a simple cable. Forlarger systems, multiple 78741’s can besynchronized using the Model 7892 high-speed sync board to drive the sync bus.


















.


Pentek, Inc.

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC,Virtex-7 FPGA - 3U VPXModel 53741


family of high-performance 3U VPX boardsbased on the Xilinx Virtex-7 FPGA. A high-speed data converter with a programmabledigital downconverter, it is suitable for con-nection to HF or IF ports of a communicationsor radar system. Its built-in data capturefeatures offer an ideal turnkey solution.

























System Specification)

TIMING BUSGENERATOR


Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

RF In

RFXFORMR



12

TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

VIRTEX-7 FPGA

VX330T or VX690T

LVDS

40

Option -104FPGAI/O

VPX BACKPLANE

VPX-P2

GTXGTXGTX

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

Option -105

4X4X

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

PCIeGen. 2 x8

CONFIGFLASH1 GB

PCIeGen. 2x8

FPGAConfigBus


MANAGER



Pentek, Inc.











PCIe INTERFACE

fromA/D

PCIe


A/D

ACQUISITION

IP MODULE

MUX


SIGNALGENERATOR

MEMORYCONTROLLER

8XtoMem

Bank 2

toMem

Bank 1

fromA/D


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3



DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


A/D

ACQUISITION

IP MODULE

MUX


DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


METADATAGENERATOR

METADATAGENERATOR

GigabitSerial I/O

FPGAGPIO


4X 4X 40





The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. This isimportant in security situations where therecan be no latent user image left in nonvolatilememory when power is removed. In applica-tions where the FPGA IP may need to changemany times during the course of a mission,images can be stored on the host computerand loaded through PCIe as needed.


In all three FPGA loading scenarios,GateXpress handles the hardware negotiationsimplifying and streamlining the loadingtask. In addition, GateXpress preserves thePCIe configuration space allowing dynamicFPGA reconfiguration without needing toreset the host computer to rediscover theboard. After the reload, the host simplycontinues to see the board with the ex-pected device ID. ➤


Pentek, Inc.



53741 1-Ch. 3.6 GHz or 2-Ch.1.8 GHz, 12-bit A/D withWideband DDC, Virtex-7FPGA - 3U VPX

Options:






versions

Model Description









standard interface fully compliant with PCIExpress Gen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers.




Digital DownconvertersModes: One or two channels,programmableSupported Sample Rate: One-channelmode: 3.6 GHz, two-channel mode:1.8 GHzDecimation Range: One-channel mode:8x, 16x or 32x, two-channel : 4x, 8x, or 16x

LO Tuning Freq. Resolution: 32 bits, 0 to ƒsLO SFDR: >120 dBPhase Offset Resolution: 32 bits,0 to 360 degreesFIR Filter: User-programmable 18-bitcoefficientsDefault Filter Set: 80% bandwidth,<0.3 dB passband ripple, >100 dBstopband attenuation


Timing Bus: 19-pin µSync bus connector in-cludes sync and gate/trigger inputs, CML



Custom I/OOption -104: Provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/OOption -105: Provides one 8X or two 4Xgigabit links between the FPGA and theVPX P1 to support serial protocols




Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




ports four independent DDR3SDRAM memory banks. Eachbank is 1 GB deep and is anintegral part of the board’s DMAcapabilities, providing FIFOmemory space for creating DMApackets.

Crossbar SwitchThe 53741 features a unique

high-speed switching configura-tion. A fabric-transparent crossbarswitch bridges numerous inter-faces and components on theboard using gigabit serial datapaths with no latency. Program-mable signal input equalizationand output pre-emphasis settingsenable optimization.


52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


Yes



Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.



family of high-performance 3U VPX boardsbased on the Xilinx Virtex-7 FPGA. A high-speed data converter with a programmabledigital downconverter, it is suitable for con-nection to HF or IF ports of a communicationsor radar system. Its built-in data capturefeatures offer an ideal turnkey solution.

























System Specification)

TIMING BUSGENERATOR


Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

RF In

RFXFORMR



12

TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

VIRTEX-7 FPGA

VX330T or VX690T

LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTX

VPX-P1

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

PCIeGen. 2 x4

CONFIGFLASH1 GB

PCIeGen. 2x4

FPGAConfigBus


MANAGER

GTXGTX

GigabitSerial I/O

Option -105

4X4X



Pentek, Inc.











PCIe INTERFACE

fromA/D

PCIe


A/D

ACQUISITION

IP MODULE

MUX


SIGNALGENERATOR

MEMORYCONTROLLER

4XtoMem

Bank 2

toMem

Bank 1

fromA/D


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3



DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


A/D

ACQUISITION

IP MODULE

MUX


DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


METADATAGENERATOR

METADATAGENERATOR

GigabitSerial I/O

FPGAGPIO


4X 4X 40





The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. This isimportant in security situations wherethere can be no latent user image left innonvolatile memory when power is removed.In applications where the FPGA IP mayneed to change many times during thecourse of a mission, images can be stored onthe host computer and loaded through PCIeas needed.


In all three FPGA loading scenarios,GateXpress handles the hardware negotiationsimplifying and streamlining the loadingtask. In addition, GateXpress preserves thePCIe configuration space allowing dynamicFPGA reconfiguration without needing toreset the host computer to rediscover theboard. After the reload, the host simply ➤


Pentek, Inc.



52741 1-Ch. 3.6 GHz or 2-Ch.1.8 GHz, 12-bit A/D withWideband DDC, Virtex-7FPGA - 3U VPX

Options:






versions

Model Description


➤ continues to see the board with theexpected device ID.










Digital DownconvertersModes: One or two channels,programmableSupported Sample Rate: One-channelmode: 3.6 GHz, two-channel mode:1.8 GHzDecimation Range: One-channel mode:8x, 16x or 32x, two-channel mode: 4x,8x, or 16xLO Tuning Freq. Resolution: 32 bits,0 to ƒsLO SFDR: >120 dB

Phase Offset Resolution: 32 bits,0 to 360 degreesFIR Filter: User-programmable 18-bitcoefficientsDefault Filter Set: 80% bandwidth,<0.3 dB passband ripple, >100 dBstopband attenuation





Custom I/OOption -104: Provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/OOption -105: Provides one 8X or two 4Xgigabit links between the FPGA and theVPX P1 connector to support serialprotocols


PCI-Express InterfacePCI Express Bus: Gen. 1, 2 or 3: x4


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)








52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.



family of high-performance XMC modulesbased on the Xilinx Virtex-7 FPGA. A high-speed data converter with a programmabledigital downconverter, it is suitable for con-nection to HF or IF ports of a communicationsor radar system. Its built-in data capturefeatures offer an ideal turnkey solution.

It includes a 3.6 GHz, 12-bit A/D con-verter and four banks of memory. In additionto supporting PCI Express Gen. 3 as a nativeinterface, Model 71741 includes an optionalconnection to the Virtex-7 FPGA for customI/O .























TIMING BUSGENERATOR


Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

RF In

RFXFORMR



12

TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

VIRTEX-7 FPGA

VX330T or VX690T

GTX

PCIeGen. 3 x8

P15XMC

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER


GTXGTX LVDS


P14PMC

P16XMC

4X4X 48


Pentek, Inc.






The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. This isimportant in security situations wherethere can be no latent user image left innonvolatile memory when power is removed.In applications where the FPGA IP mayneed to change many times during thecourse of a mission, images can be storedon the host computer and loaded throughPCIe as needed. ➤










PCIe INTERFACE

fromA/D

PCIe


A/D

ACQUISITION

IP MODULE

MUX


SIGNALGENERATOR

MEMORYCONTROLLER

8XtoMem

Bank 2

toMem

Bank 1

fromA/D


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3



DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


A/D

ACQUISITION

IP MODULE

MUX


DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


METADATAGENERATOR

METADATAGENERATOR

GigabitSerial I/O

FPGAGPIO


4X 4X 48


Pentek, Inc.




Options:






versions

Model Description


➤ The third option, typically used duringdevelopment, allows the user to directly loadthe FPGA through JTAG using Xilinx iMPACT.


A/D Converter StageThe front end accepts analog HF or IF in-

puts on a pair of front panel SSMC connectorswith transformer coupling into a Texas Instru-ments ADC12D1800 12-bit A/D. The converteroperates in single-channel interleaved modewith a sampling rate of 3.6 GHz and an inputbandwidth of 1.75 GHz; or, in dual-channelmode with a sampling rate of 1.8 GHz andinput bandwidth of 2.8 GHz.

The ADC12D1800 provides a program-mable 15-bit gain adjustment allowing the71741 to have a full scale input range of+2 dBm to +4 dBm. A built-in AutoSyncfeature supports A/D synchronizationacross multiple modules.






A front panel µSync bus connector allowsmultiple modules to be synchronized, idealfor multichannel systems. The µSync busincludes gate, reset, and in and out refer-ence clock signals. Two 71741’s can besynchronized with a simple cable. Forlarger systems, multiple 71741’s can besynchronized using the Model 7192 high-speed sync module to drive the sync bus.














Model 8266


ports four independent DDR3SDRAM memory banks. Eachbank is 1 GB deep and is anintegral part of the module’sDMA capabilities, providingFIFO memory space for creatingDMA packets. Built-in memoryfunctions include multichannelA/D data capture, tagging andstreaming.

The Model 8266 is a fully-integrated PC developmentsystem for Pentek Cobalt, Onyxand Flexor PCI Express boards. Itwas created to save engineers andsystem integrators the time andexpense associated with buildingand testing a development systemthat ensures optimum perfor-mance of Pentek boards.


Pentek, Inc.

1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bitA/D, w/ Wideband DDC, Virtex-7 FPGA - cPCI

Models 72741,73741 and 74741


members of the Onyx® family of high per-formance CompactPCI boards based onthe Xilinx Virtex-7 FPGA. They consist ofone or two Model 71741 XMC modulesmounted on a cPCI carrier board.


These models include one or two 3.6 GHz,12-bit A/D converters, four or eight banksof memory, and one or two wideband DDCs



Each member of the Onyx family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The factory-installed functions of thesemodels include one or two A/D acquisitionIP modules and one or two wideband DDCs.

In addition, IP modules for DDR3 SDRAMmemories, a controller for all data clockingand synchronization functions, a test signalgenerator and a PCIe interface completethe factory-installed functions and enablethese models to operate as complete turn-key solutions, without the need to developany FPGA IP.












■ Programmable one- or two-channel DDCs (DigitalDownconverters)

■ 4 or 8 GB of DDR3 SDRAM■ µSync clock/sync bus for



TIMING BUSGENERATOR


Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

RF In

RFXFORMR



12

TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

VIRTEX-7 FPGA

VX330T or VX690T

PCIeto PCI

BRIDGE

PCIto PCI

BRIDGE

40

From/To Other

XMC Module of

Model 74741

LVDS GTX


x4PCIe

x4 PCIe


J3

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

CONFIGFLASH1 GB


MANAGER

FPGAConfigBus




VIRTEX-7 FPGA


PCIeto PCI

BRIDGE

40

LVDS GTX

FPGA I/O(Option

-104)


J2

x4PCIe

x4 PCIe

CONFIGFLASH1 GB


MANAGER

FPGAConfigBus



Pentek, Inc.


Models 72741,73741 and 74741







two A/D Acquisition IP Mod-ules for easy capture and datamoving. The IP modules canreceive data from the A/D, or atest signal generator. The IP mod-ules have associated memorybanks for buffering data in FIFOmode or for storing data intransient capture mode.

In single-channel mode, allbanks are used to store thesingle-channel of input data. Indual-channel mode, memorybanks 1 and 2 store data frominput channel 1 and memorybanks 3 and 4 store data frominput channel 2. In both modes,continuous, full-rate transientcapture of 12-bit data is supported.








PCIe INTERFACE

fromA/D

PCIe


A/D

ACQUISITION

IP MODULE

MUX


SIGNALGENERATOR

MEMORYCONTROLLER

4XtoMem

Bank 2

toMem

Bank 1

fromA/D


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3



DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


A/D

ACQUISITION

IP MODULE

MUX


DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


METADATAGENERATOR

METADATAGENERATOR

FPGAGPIO

40


Pentek, Inc.


Models 72741,73741 and 74741


72741 1-Ch. 3.6 GHz or 2-Ch.1.8 GHz, 12-bit A/D, withWideband DDC, Virtex-7FPGA - 6U cPCI

73741 1-Ch. 3.6 GHz or 2-Ch.1.8 GHz, 12-bit A/D, withWideband DDC, Virtex-7FPGA - 3U cPCI

74741 2-Ch. 3.6 GHz or 4-Ch.1.8 GHz, 12-bit A/D, withWideband DDC, Virtex-7FPGAs - 6U cPCI

Options:









The ADC12D1800 provides a program-mable 15-bit gain adjustment allowingthese models to have a full scale inputrange of +2 dBm to +4 dBm. A built-inAutoSync feature supports A/D synchro-nization across multiple boards.

The A/D digital outputs are deliveredinto the Virtex-7 FPGA for signal process-ing, data capture or for routing to otherboard resources.


edge sample clock via a front panel SSMCconnector. A second front panel SSMC acceptsa TTL signal that can function as Gate, PPSor Sync.

A front panel µSync bus connector allowsmultiple boards to be synchronized, ideal formultichannel systems. The µSync bus includesgate, reset, and in and out reference clocksignals. Two boards can be synchronizedwith a simple cable. For larger systems,multiple boards can be synchronized usingthe Models 7292, 7392 or 7492 high-speedsync boards to drive the sync bus.

SpecificationsModel 72741 or Model 73741: One A/DModel 74741: Two A/DsFront Panel Analog Signal Inputs (2 or 4)


A/D Converters (1 or 2)Type: Texas Instruments ADC12D1800Sampling Rate: Single-channel mode:500 MHz to 3.6 GHz; dual-channelmode: 150 MHz to 1.8 GHzResolution: 12 bitsInput Bandwidth: single-channel mode:1.75 GHz; dual-channel mode: 2.8 GHzFull Scale Input: +2 dBm to +4 dBm,programmable

Digital Downconverters (2 or 4)Modes: One or two channels,programmableSupported Sample Rate: One-channelmode: 3.6 GHz, two-channel mode:1.8 GHzDecimation Range: One-channel mode:8x, 16x or 32x, two-channel mode: 4x,8x, or 16xLO Tuning Freq. Resolution: 32 bits,0 to ƒsLO SFDR: >120 dBPhase Offset Resolution: 32 bits,0 to 360 degreesFIR Filter: User-programmable 18-bitcoefficientsDefault Filter Set: 80% bandwidth,<0.3 dB passband ripple, >100 dBstopband attenuation


Timing Bus (1 or 2) 19-pin µSync bus connector includessync and gate/trigger inputs, CML

External Trigger Input (1 or2)Type: Front panel female SSMC connector,LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS







Memory ResourcesThe Onyx architecture sup-


PCI-X InterfaceThese models include an

industry-standard interfacefully compliant with PCI-X busspecifications. The interfaceincludes multiple DMA control-lers for efficient transfers to andfrom the board. Data widths of32 or 64 bits and data rates of 33and 66 MHz are supported.Model 73741: 32 bits only.


Pentek, Inc.

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC,Virtex-7 FPGA - AMCModel 56741


family of high-performance AMC modulesbased on the Xilinx Virtex-7 FPGA. A high-speed data converter with a programmabledigital downconverter, it is suitable for con-nection to HF or IF ports of a communicationsor radar system. Its built-in data capturefeatures offer an ideal turnkey solution.

It includes a 3.6 GHz, 12-bit A/D con-verter and four banks of memory. In additionto supporting PCI Express Gen. 3 as a nativeinterface, Model 56741 includes an optionalfront-panel connection to the Virtex-7FPGA for custom I/O.



Each member of the Onyx family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 56741 factory-installed functionsinclude an A/D acquisition IP module anda programmable digital downconverter. In

addition, IP modules for DDR3 SDRAMmemories, a controller for all data clockingand synchronization functions, a test signalgenerator and a PCIe interface completethe factory-installed functions and enablethe 56741 to operate as a complete turnkeysolution, without the need to develop anyFPGA IP.


















TIMING BUSGENERATOR


Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

RF In

RFXFORMR



12

TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

VIRTEX-7 FPGA

VX330T or VX690T

LVDSGTX


PCIeGen. 3 x8

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

48 32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

FrontPanel

FrontPanel

Ports 4 to 11

IPMICONTROLLER

RS-232

AMC


Pentek, Inc.
















PCIe INTERFACE

fromA/D

PCIe


A/D

ACQUISITION

IP MODULE

MUX


SIGNALGENERATOR

MEMORYCONTROLLER

8XtoMem

Bank 2

toMem

Bank 1

fromA/D


toMEM

CONTROL

MEMORYCONTROLLER

toMem

Bank 4

toMem

Bank 3



DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


A/D

ACQUISITION

IP MODULE

MUX


DDC*DEC: 4, 8 or 16

POWERMETER &

THRESHOLDDETECT

DDC CORE


METADATAGENERATOR

METADATAGENERATOR

FPGAGPIO


48


Pentek, Inc.



56741 1-Ch. 3.6 GHz or 2-Ch.1.8 GHz, 12-bit A/D withWideband DDC, Virtex-7FPGA - AMC

Options:



-104 LVDS FPGA I/O to frontpanel connector


versions






The ADC12D1800 provides a program-mable 15-bit gain adjustment allowing the56741 to have a full scale input range of+2 dBm to +4 dBm. A built-in AutoSyncfeature supports A/D synchronizationacross multiple boardss.

The A/D digital outputs are deliveredinto the Virtex-7 FPGA for signal process-ing, data capture or for routing to otherboard resources.

























Pentek, Inc.

Model 71610 LVDS Digital I/O with Virtex-6 FPGA - XMC


family of high-performance XMC modulesbased on the Xilinx Virtex-6 FPGA. Thisdigital I/O module provides 32 LVDS dif-ferential inputs or outputs plus LVDS clock,data valid, and data flow control on a frontpanel 80-pin connector. Its built-in datacapture and data generation feature offersan ideal turnkey solution as well as a plat-form for developing and deploying customFPGA-processing IP.

In addition to supporting PCI ExpressGen. 1 as a native interface, the Model 71610includes a general-purpose connector forapplication-specific I/O.


a Virtex-6 FPGA. All of the board’s dataand control paths are accessible by theFPGA, enabling factory-installed functionsfor data flow and memory control. The Co-balt Architecture organizes the FPGA as acontainer for data processing applicationswhere each function exists as an IP (intel-lectual property) module.

Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s interface.The 71610 factory-installed functions include32-bit acquisition and generation IP modules,to support either input or output functions,respectively.

IP modules for DDR3 SDRAM memo-ries, a controller for all data clocking, a testsignal generator, and a PCIe interface com-

plete the factory-installed functions andenable the 71610 to operate as a completeturnkey solution without the need to de-velop any FPGA IP.


function, users can install their own customIP for data processing. Pentek GateFlowFPGA Design Kits include all of the factory-installed modules as documented sourcecode. Developers can integrate their ownIP with the Pentek factory-installed functionsor use the GateFlow kit to completelyreplace the Pentek IP with their own.

Xilinx Virtex-6 FPGAThe Virtex-6 FPGA can be populated

with a variety of different FPGAs to matchthe specific requirements of the processingtask. Supported FPGAs include: LX130TLX240T, or SX315T. The SXT part featuresup to 1344 DSP48E slices and is ideal formodulation/demodulation, encoding/decoding, encryption/decryption, andchannelization of the signals betweentransmission and reception. For applica-tions not requiring large DSP resources,one of the lower-cost LXT FPGAs can beinstalled.

Option -104 installs the P14 PMC con-nector with 20 pairs of LVDS connectionsto the FPGA for custom I/O to the carrierboard.

Option -105 installs the P16 XMC con-nector with one 8X or two 4X gigabit linksto the FPGA to support serial protocols. ➤

Features■ 32 bits of LVDS digital I/O■ One LVDS clock■ One LVDS data valid

■ One LVDS data suspend■ Supports LXT and SXT

Virtex-6 FPGAS■ DMA controller moves data

to and from system memory■ Up to 2 GB of DDR3 SDRAM■ PCI Express interface


■ Optional LVDS connectionsto the Virtex-6 FPGA forcustom I/O to the carrierboard

VIRTEX-6 FPGA


32

32 PairsLVDS Data

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

Memory Banks 1 & 2 Memory Banks 3 & 4Option 165

40 4X

GTX

4X

GTXLVDS GTX

OptionalFPGAGPIO

OptionalGigabitSerial I/O

8X

PMC P14

x8 PCIe

80-pin Front PanelConnector

XMC P15 XMC P16

LVDSClock

DataValid

DataSuspend


Pentek, Inc.

Model 71610 LVDS Digital I/O with Virtex-6 FPGA - XMC

➤➤➤➤➤ Acquisition IP ModuleThe module can be configured for digital

input mode by setting a jumper on the board.In this case, the module accepts input dataClock and input Data Valid signals. Thissupports a continuous input Clock withdata accepted only when the Data Validline is true. The module can optionallygenerate a Data Suspend output signal indi-cating that the 71610 is no longer capable ofaccepting data. The module accepts 32 bitsfrom the front panel connector or from anon-board test signal generator.

Each IP module has an associated memorybank for buffering data in FIFO mode or forstoring data in transient capture mode.Memory banks are supported with DMAengines for easily moving input data throughthe PCIe interface.

Generation IP ModuleThe module can be configured for digital

output mode by setting a jumper on theboard. In this case, the module generatesoutput data Clock and output Data Validsignals. This supports a continuous outputClock with data valid only when the DataValid line is true. The module can option-ally accept a Data Suspend input signal tohalt data generation when the destinationdevice is no longer capable of accepting data.

A linked-list controller allows users togenerate 32-bit digital words out throughthe front panel LVDS connector from tablesstored in either on-board or off-board hostmemory. Parameters including length oftable, delay from software trigger, table rep-etition, etc. can be programmed for entry. Upto 64 individual link entries can be chainedtogether to create complex output patternswith minimum programming.


VITA 42.0 XMC specification. Each of twoconnectors provides multilane gigabit serialinterfaces with up to a 6 GHz bit clock. Withdual XMC connectors, the 71610 supports x4or x8 PCIe on the primary P15 XMC connec-tor. The secondary P16 XMC connector isused for dual 4X or single 8X user-installedgigabit serial interfaces, such as Aurora,PCIe and serial RapidIO.


71610 LVDS Digital I/O withVirtex-6 FPGA - XMC

Options:

-062 XC6VLX240T

-064 XC6VSX315T







versions

Model Description



standard interface fully compliant with PCIExpress Gen. 1 bus specifications. Support-ing a PCIe x4 or x8 connection, the interfaceincludes multiple DMA controllers forefficient transfers to and from the module.

Memory ResourcesThe 71610 hardware architecture supports

up to four independent 512 MB memorybanks of DDR3 SDRAM. The board isalways configured with 1 GB of memory(Banks 1 and 2).

In addition to the factory-installed func-tions, custom user-installed IP within theFPGA can take advantage of the memoriesfor many other purposes. For customerswho need more memory to support their IP,Banks 3 and 4 can be optionally added for atotal of 2 GB of DDR3 SDRAM

SpecificationsFront Panel Input/Output

Data Lines: 35 LVDS differential pairs(32 pairs supported in factory-installedfunctions), 2.5 V compliantClock: One LVDS differential pair, 2.5 VcompliantData Valid: One LVDS differential pair,2.5 V compliantData Suspend: One LVDS differentialpair, 2.5 V compliant



MemoryStandard: Two 512 MB DDR3 SDRAMmemory banks (1 and 2), 400 MHz DDROption 165: Two 512 MB DDR3 SDRAMmemory banks (3 and 4), 400 MHz DDR

PCI-Express InterfacePCI Express Bus: Gen. 1: x4 or x8






Pentek, Inc.

Model 78610 LVDS Digital I/O with Virtex-6 FPGA - x8 PCIe


family of high-performance PCIe boardsbased on the Xilinx Virtex-6 FPGA. Thisdigital I/O board provides 32 LVDS differ-ential inputs or outputs plus LVDS clock,data valid, and data flow control on a frontpanel 80-pin connector. Its built-in datacapture and data generation feature offersan ideal turnkey solution as well as a plat-form for developing and deploying customFPGA-processing IP.




Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s interface.The 78610 factory-installed functionsinclude 32-bit acquisition and generationIP modules, to support either input or outputfunctions, respectively.

IP modules for DDR3 SDRAM memo-ries, a controller for all data clocking, a testsignal generator, and a PCIe interface com-

plete the factory-installed functions andenable the 78610 to operate as a completeturnkey solution without the need todevelop any FPGA IP.




with a variety of different FPGAs to matchthe specific requirements of the processingtask. Supported FPGAs include: LX130TLX240T, or SX315T. The SXT part featuresup to 1344 DSP48E slices and is ideal formodulation/demodulation, encoding/decoding, encryption/decryption, andchannelization of the signals betweentransmission and reception. For applicationsnot requiring large DSP resources, one ofthe lower-cost LXT FPGAs can be installed.



Features■ 32 bits of LVDS digital I/O■ One LVDS clock■ One LVDS data valid






VIRTEX-6 FPGA


32

32 PairsLVDS Data

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



LVDSClock

DataValid

DataSuspend

40 4X

GTX

4X

GTXLVDS GTX

OptionalFPGAGPIO

OptionalSerialI/O

8X

68-pinHeader

x8 PCI Express

Dual 4XSerialConn

x8 PCIe


Pentek, Inc.

Model 78610 LVDS Digital I/O with Virtex-6 FPGA - x8 PCIe

➤➤➤➤➤ Acquisition IP ModuleThe board can be configured for digital

input mode by the setting of a jumper. Inthis case, the board accepts input dataClock and input data Valid signals. Thissupports a continuous input Clock withdata accepted only when the Data Validline is true. The board can optionallygenerate a Data Suspend output signal indi-cating that the 78610 is no longer capable ofaccepting data. The board accepts 32 bitsfrom the front panel connector or from anon-board test signal generator.


Generation IP ModuleThe board can be configured for digital

output mode by the setting of a jumper. Inthis case, the board generates output dataClock and output Data Valid signals. Thissupports a continuous output Clock withdata valid only when the Data Valid line istrue. The board can optionally accept aData Suspend input signal to halt data gen-eration when the destination device is nolonger capable of accepting data.



standard interface fully compliant with PCIExpress Gen. 1 bus specifications. Sup-porting a PCIe x4 or x8 connection, theinterface includes multiple DMA control-lers for efficient transfers to and from theboard.


78610 LVDS Digital I/O withVirtex-6 FPGA - PCIe

Options:

-062 XC6VLX240T

-064 XC6VSX315T






Model Description


Memory ResourcesThe 78610 hardware architecture

supports up to four independent 512 MBmemory banks of DDR3 SDRAM. Theboard is always configured with 1 GB ofmemory (Banks 1 and 2).



Data Lines: 35 LVDS differential pairs(32 pairs supported in factory-installedfunctions), 2.5 V compliantClock: One LVDS differential pair,2.5 V compliantData Valid: One LVDS differential pair,2.5 V compliantData Suspend: One LVDS differentialpair, 2.5 V compliant










Pentek, Inc.

Model 53610 LVDS Digital I/O with Virtex-6 FPGA - 3U VPX


family of high-performance 3U VPX boardsbased on the Xilinx Virtex-6 FPGA. Thisdigital I/O board provides 32 LVDS differ-ential inputs or outputs plus LVDS clock,data valid, and data flow control on a frontpanel 80-pin connector. Its built-in datacapture and data generation feature offersan ideal turnkey solution as well as a plat-form for developing and deploying customFPGA-processing IP.





IP modules for DDR3 SDRAM memo-ries, a controller for all data clocking, a test

signal generator, and a PCIe interface com-plete the factory-installed functions andenable the 53610 to operate as a completeturnkey solution without the need todevelop any FPGA IP.







Features■ 32 bits of LVDS digital I/O

■ One LVDS clock■ One LVDS data valid■ One LVDS data suspend

■ Supports LXT and SXTVirtex-6 FPGAS

■ DMA controller moves datato and from system memory

■ Up to 2 GB of DDR3 SDRAM■ PCI Express interface■ Optional user-configurable


to the Virtex-6 FPGA forcustom I/O to the carrierboard





VIRTEX-6 FPGA


32

32 PairsLVDS Data

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



LVDSClock

DataValid

DataSuspend

LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTX

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

Option -105

4X8X 4X

x8PCIe



Pentek, Inc.









standard interface fully compliant with PCIExpress Gen. 1 bus specifications. Support-ing a PCIe x4 or x8 connection, the interfaceincludes multiple DMA controllers for effi-cient transfers to and from the board.



In addition to the factory-installed func-tions, custom user-installed IP within theFPGA can take advantage of the memoriesfor many other purposes. For customerswho need more memory to support their


53610 LVDS Digital I/O withVirtex-6 FPGA - 3U VPX

Options:

-062 XC6VLX240T

-064 XC6VSX315T







versions

Model Description


IP, Banks 3 and 4 can be optionally addedfor a total of 2 GB of DDR3 SDRAM




Custom I/OOption -104: Provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/O.Option -105: Provides one 8X or two 4Xgigabit links between the FPGA andthe VPX P1 connector to support serialprotocols.




Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No

Fabric-Transparent CrossbarSwitch

The 53610 features a uniquehigh-speed switching configu-ration. A fabric-transparentcrossbar switch bridges numer-ous interfaces and componentson the board using gigabit serialdata paths with no latency.Programmable signal inputequalization and output pre-emphasis settings enableoptimization. Data paths can beselected as single (1X) lanes, orgroups of four lanes (4X).




Pentek, Inc.



family of high-performance 3U VPX boardsbased on the Xilinx Virtex-6 FPGA. Thisdigital I/O board provides 32 LVDS differ-ential inputs or outputs plus LVDS clock,data valid, and data flow control on a frontpanel 80-pin connector. Its built-in datacapture and data generation feature offersan ideal turnkey solution as well as a plat-form for developing and deploying customFPGA-processing IP.





IP modules for DDR3 SDRAM memo-ries, a controller for all data clocking, a test

signal generator, and a PCIe interface com-plete the factory-installed functions andenable the 52610 to operate as a completeturnkey solution without the need todevelop any FPGA IP.







Features■ 32 bits of LVDS digital I/O

■ One LVDS clock■ One LVDS data valid■ One LVDS data suspend


■ DMA controller moves datato and from system memory

■ Up to 2 GB of DDR3 SDRAM■ PCI Express interface■ Optional user-configurable


to the Virtex-6 FPGA forcustom I/O to the carrierboard





VIRTEX-6 FPGA


32

32 PairsLVDS Data

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



LVDSClock

DataValid

DataSuspend

LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTX

GigabitSerial I/O

VPX-P1

Option -105

4X4X 4X

x4PCIe



Pentek, Inc.









standard interface fully compliant with PCIExpress Gen. 1 bus specifications. Sup-porting a PCIe x4 connection, the interfaceincludes multiple DMA controllers forefficient transfers to and from the board.



In addition to the factory-installed func-tions, custom user-installed IP within theFPGA can take advantage of the memoriesfor many other purposes. For customerswho need more memory to support their IP,


52610 LVDS Digital I/O withVirtex-6 FPGA - 3U VPX

Options:

-062 XC6VLX240T

-064 XC6VSX315T







versions

Model Description


Banks 3 and 4 can be optionally added fora total of 2 GB of DDR3 SDRAM




Custom I/OOption -104: Provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/O.Option -105: Provides one 8X or two 4Xgigabit links between the FPGA andthe VPX P1 connector to support serialprotocols.


PCI-Express InterfacePCI Express Bus: Gen. 1: x4


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.

Single or Dual LVDS Digital I/O with Virtex-6 FPGA -6U OpenVPX

Models57610 and 58610




These models include one or twogeneral-purpose connectors for application-specific I/O.


Virtex-6 FPGAs. All of the board’s data andcontrol paths are accessible by the FPGA,enabling factory-installed functions fordata flow and memory control. The CobaltArchitecture organizes the FPGA as a con-tainer for data processing applicationswhere each function exists as an IP (intel-lectual property) module.

Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s interface.The factory-installed functions of thesemodels include 32-bit acquisition and gen-eration IP modules, to support either inputor output functions, respectively.

IP modules for DDR3 SDRAM memo-ries, controllers for all data clocking, testsignal generators, and a PCIe interfacecomplete the factory-installed functions

and enable these models to operate as com-plete turnkey solutions without the needto develop any FPGA IP.







New!

New!

New!

New!

New!

Features■ 32 or 64 bits of LVDS digital

I/O■ One or two LVDS clocks■ One or two LVDS data valid

■ One or two LVDS datasuspend


■ One or two DMA controllersmove data to and fromsystem memory

■ Up to 2 or 4 GB of DDR3





VIRTEX-6 FPGA


32

32 PairsLVDS Data

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



LVDSClock

DataValid

DataSuspend

LVDS GTX

40 8X

FPGAI/O

Option -104

VPX BACKPLANE

GTXGTX

PCIeGen. 2 x8

4X4X

PCIeGen. 2 x8

VPX-P2VPX-P1

PCIe-to PCIeSWITCH

From/To

Other XMC

Module of

Model 58610

Option -105

Gigabit Serial I/O

VPX-P3







Model 58610


Pentek, Inc.

Single or Dual LVDS Digital I/O with Virtex-6 FPGA -6U OpenVPX


➤➤➤➤➤ Acquisition IP ModulesThese models can be configured for digi-

tal input mode by the setting of one ortwo jumpers. In this case, the board acceptsinput data Clock and input data Validsignals. This supports a continuous inputClock with data accepted only when theData Valid line is true. The board canoptionally generate a Data Suspend outputsignal indicating that these models are nolonger capable of accepting data. Theboard accepts 32 bits from the front panelconnector or from an on-board test signalgenerator.


Generation IP ModulesThese models can be configured for digi-

tal output mode by the setting of one ortwo jumpers. In this case, the board gener-ates output data Clock and output DataValid signals. This supports a continuousoutput Clock with data valid only whenthe Data Valid line is true. The board canoptionally accept a Data Suspend inputsignal to halt data generation when thedestination device is no longer capable ofaccepting data.

One or two linked-list controllers allowusers to generate 32-bit digital words outthrough the front panel LVDS connectorfrom tables stored in either on-board oroff-board host memory. Parameters includ-ing length of table, delay from softwaretrigger, table repetition, etc. can be program-med for entry. Up to 64 or 128 individuallink entries can be chained together to cre-ate complex output patterns with minimumprogramming.




57610 Single LVDS Digital I/Owith Virtex-6 FPGA -6U VPX

58610 Dual LVDS Digital I/Owith two Virtex-6 FPGAs -6U VPX

Options:

-062 XC6VLX240T

-064 XC6VSX315T







versions

Model Description


Memory ResourcesThe hardware architecture supports

up to four or eight independent 512 MBmemory banks of DDR3 SDRAM. Theboard is always configured with 1 GB ofmemory (Banks 1 and 2).

In addition to the factory-installed func-tions, custom user-installed IP within theFPGA can take advantage of the memoriesfor many other purposes. For customerswho need more memory to support their IP,Banks 3 and 4 can be optionally added fora total of 4 GB.

SpecificationsModel 57610: Single LVDS Digital I/OModel 58610: Dual LVDS Digital I/OFront Panel Input/Output (1 or 2)


Field Programmable Gate Array (1 or 2)Standard: Xilinx Virtex-6 XC6VLX130TOptional: Xilinx Virtex-6 XC6VLX240T,or XC6VSX315T


Memory Banks (1 or 2)Standard: Two 512 MB DDR3 SDRAMmemory banks (1 and 2), 400 MHz DDROption 165: Two 512 MB DDR3 SDRAMmemory banks (3 and 4), 400 MHz DDR

PCI Express InterfacePCI Express Bus: Gen. 1 or 2: x4 or x8


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




Pentek, Inc.

Single or Dual LVDS Digital I/O with Virtex-6 FPGA - cPCIModels 72610,73610 and 74610


members of the Cobalt® family of high-per-formance CompactPCI boards based onthe Xilinx Virtex-6 FPGA. They consist ofone or two Model 71610 XMC modulesmounted on a cPCI carrier board.


These models include one or twogeneral-purpose connectors for application-specific I/O.


Virtex-6 FPGAs. All of the board’s data andcontrol paths are accessible by the FPGA,enabling factory-installed functions fordata flow and memory control. The CobaltArchitecture organizes the FPGA as a con-tainer for data processing applicationswhere each function exists as an IP (intel-lectual property) module.

Each member of the Cobalt family isdelivered with factory-installed applicationsideally matched to the board’s interface.The factory-installed functions of thesemodels include 32-bit acquisition and gen-eration IP modules, to support either inputor output functions, respectively.

IP modules for DDR3 SDRAM memo-ries, controllers for all data clocking, a test

signal generator, and a PCIe interface com-plete the factory-installed functions andenable these models to operate as completeturnkey solutions without the need todevelop any FPGA IP.






Features■ 32 or 64 bits of LVDS digital

I/O

■ One or two LVDS clocks■ One or two LVDS data valid■ One or two LVDS data

suspend■ Supports LXT and SXT

Virtex-6 FPGAS■ One or two DMA controllers

move data to and fromsystem memory

■ Up to 2 or 4 GB of DDR3SDRAM


VIRTEX-6 FPGA


32

32 PairsLVDS Data

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



LVDSClock

DataValid

DataSuspend

PCIeto PCI

BRIDGE

PCIto PCI

BRIDGE

40 From/To Other

XMC Module of

MODEL 74610

LVDS GTX


x4 PCIe


4X

J3

VIRTEX-6 FPGA




MODEL 73610

INTERFACES ONLY

PCIeto PCI

BRIDGE

40

LVDS GTX



J2



Pentek, Inc.

Single or Dual LVDS Digital I/O with Virtex-6 FPGA - cPCIModels 72610,73610 and 74610

➤➤➤➤➤ Acquisition IP ModuleThese models can be configured for digi-

tal input mode by the setting of a jumper.In this case, the board accepts input dataClock and input data Valid signals. Thissupports a continuous input Clock withdata accepted only when the Data Validline is true. The board can optionallygenerate a Data Suspend output signal indi-cating that these models are no longercapable of accepting data. The boardaccepts 32 bits from the front panel connec-tor or from an on-board test signal generator.


Generation IP ModuleThese models can be configured for digi-

tal output mode by the setting of a jumper.In this case, the board generates outputdata Clock and output Data Valid signals.This supports a continuous output Clockwith data valid only when the Data Validline is true. The board can optionally accepta Data Suspend input signal to halt datageneration when the destination device isno longer capable of accepting data.





72610 Single LVDS Digital I/Owith Virtex-6 FPGA -6U cPCI

73610 Single LVDS Digital I/Owith Virtex-6 FPGA -3U cPCI

74610 Dual LVDS Digital I/Owith Virtex-6 FPGAs -6U cPCI

Options:

-062 XC6VLX240T

-064 XC6VSX315T





Memory ResourcesThe hardware architecture supports

up to four or eight independent 512 MBmemory banks of DDR3 SDRAM. Theboard is always configured with 1 GB ofmemory (Banks 1 and 2).

In addition to the factory-installed func-tions, custom user-installed IP within theFPGA can take advantage of the memoriesfor many other purposes. For customerswho need more memory to support their IP,Banks 3 and 4 can be optionally added for atotal of 2 GB of DDR3 SDRAM for Models72610 and 73610 or a total of 4 GB forModel 74610.

SpecificationsModel 72610 or Model 73610: Single LVDS

Digital I/OModel 74610: Dual LVDS Digital I/OFront Panel Input/Output (1 or 2)


Field Programmable Gate Array (1 or 2)Standard: Xilinx Virtex-6 XC6VLX130TOptional: Xilinx Virtex-6 XC6VLX240T,or XC6VSX315T

Custom I/OOption -104 provides 20 LVDS pairsbetween the FPGA and the J2 connector,Model 73610; J3 connector, Model 72610;J3 and J5 connectors, Model 74610

Memory Banks (1 or 2)Standard: Two 512 MB DDR3 SDRAMmemory banks (1 and 2), 400 MHz DDROption 165: Two 512 MB DDR3 SDRAMmemory banks (3 and 4), 400 MHz DDR





Pentek, Inc.

Model 56610 LVDS Digital I/O with Virtex-6 FPGA - AMC


family of high-performance AMC boardsbased on the Xilinx Virtex-6 FPGA. Thisdigital I/O board provides 32 LVDS differ-ential inputs or outputs plus LVDS clock,data valid, and data flow control on a frontpanel 80-pin connector. Its built-in datacapture and data generation feature offersan ideal turnkey solution as well as a plat-form for developing and deploying customFPGA-processing IP.





IP modules for DDR3 SDRAM memo-ries, a controller for all data clocking, a testsignal generator, and a PCIe interface com-plete the factory-installed functions andenable the 56610 to operate as a completeturnkey solution without the need todevelop any FPGA IP.





Option -104 installs a front panel connec-tor with 20 pairs of LVDS connections tothe FPGA for custom I/O. ➤Features

■ 32 bits of LVDS digital I/O■ One LVDS clock■ One LVDS data valid







VIRTEX-6 FPGA


32

32 PairsLVDS Data

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



LVDSClock

DataValid

DataSuspend

40

LVDSGTX


x8 PCIe

8X

FrontPanel

AMCPorts 4 to 11

IPMICONTROLLER

RS-232

FrontPanel


Pentek, Inc.

Model 56610 LVDS Digital I/O with Virtex-6 FPGA - AMC










56610 LVDS Digital I/O withVirtex-6 FPGA - PCIe

Options:

-062 XC6VLX240T

-064 XC6VSX315T







versions


standard interface fully compliant with PCIExpress Gen. 1 bus specifications. Support-ing a PCIe x4 or x8 connection, the interfaceincludes multiple DMA controllers forefficient transfers to and from the board.














Pentek, Inc.

Quad Serial FPDP Interface with Virtex-6 FPGA - PCIeModel 7811


family of high performance XMC modulesbased on the Xilinx Virtex-6 FPGA. A multi-channel, gigabit serial interface, it is idealfor interfacing to Serial FPDP data converterboards or as a chassis-to-chassis data link.

The 7811 is fully compatible with theVITA 17.1 Serial FPDP specification. Itsbuilt-in data transfer features make it acomplete turnkey solution. For users whorequire application-specific functions,the 7811 serves as a flexible platform fordeveloping and deploying custom FPGAprocessing IP.


a Virtex-6 FPGA. All of the board’s data andcontrol paths are accessible by the FPGA,enabling factory-installed functions includingdata transfer and control. The CobaltArchitecture organizes the FPGA as acontainer for data processing applicationswhere each function exists as an intellectualproperty (IP) module.

IP modules for data routing and flowcontrol, CRC support, advanced DMAengines, and a PCIe interface complete the



function, users can install their own customIP for data processing. Pentek GateFlow®

FPGA Design Kits include all of the factory-installed modules as documented sourcecode. Developers can integrate their ownIP with the Pentek factory-installed functionsor use the GateFlow kit to completely replacethe Pentek IP with their own.

Xilinx Virtex-6 FPGAThe Virtex-6 FPGA can be populated with

two different FPGAs to match the specificrequirements of the processing task. SupportedFPGAs include: LX130T, LX240T or SX315T.The SX315T part features 1,344 DSP48Eslices and is ideal for modulation/demodu-lation, encoding/decoding, encryption/decryption, and channelization of the signalsbetween transmission and reception.

For applications not requiring large DSPresources, the lower-cost LX130T FPGAcan be installed. ➤

Features■ Complete Serial FPDP

solution■ Fully compliant with VITA

17.1specification■ Fibre optic or copper serial

interfaces■ PCI Express interface up to

x8

VIRTEX-6 FPGA


16

ConfigFLASH16 MB

GTX

x8 PCIe

8X

PCIe

RX TX RX TX RX TX RX TX

GTXGTXGTXGTX

CH 1 CH 2 CH 3 CH 4

FIBER OPTICor COPPERINTERFACE





Pentek, Inc.

Quad Serial FPDP Interface with Virtex-6 FPGA - PCIeModel 7811

➤➤➤➤➤ Serial FPDP InterfaceThe 7811 is fully compatible with the

VITA 17.1 Serial FPDP specification. Withthe capability to support 1.0625, 2.125, 2.5,3.125, and 4.25 Gbaud link rates and theoption for multi-mode and single-modeoptical interfaces or copper interfaces theboard can work in virtually any system.Programmable modes include: flow controlin both receive and transmit directions, CRCsupport, and copy/loop modes.


standard interface fully compliant with PCIExpress bus specifications. SupportingPCIe links up to x8, the interface includeseight DMA controllers. Each of the fourSerial FPDP channels includes dedicatedDMA engines for transmit and receive forefficient transfers to and from the board.

SpecificationsFront Panel Serial FPDP Inputs/Outputs

Number of Connectors: 4Fiber Optic Connector Type: LC

Laser: 850 nm (standard, other optionsavailable)

Copper Connector Type: SFP+Fiber Optic or Copper Link Rates:1.0625, 2.125, 2.5, 3.125 or 4.25 Gbaud(copper rate depends on cable langth)Fiber Optic or Copper Data TransferRates: 105, 210, 247, 309 or 420 MB/sec(depending on link rate) per serialFPDP port

Field Programmable Gate ArrayStandard: Xilinx Virtex-6 XC6VLX130TOptional: Xilinx Virtex-6 XC6VLX240T



Size: Half-length PCIe card,4.38 in. x 7.13 in. ➤


7811 Quad Serial FPDPInterface with Virtex-6FPGA - PCIe

Options:



-280 Copper serial interfaces

-281 Multi-mode optical serialinterfaces

Model Description

8266 PC Development SystemSee 8266 Datasheet forOptions VIRTEX-6 FPGA DATAFLOW DETAILVIRTEX-6 FPGA DATAFLOW DETAIL

8X

PACKETDECONSTRUCT

2K x 32RX FIFO

OPTIONALCRC

CHECK

SERIAL FPDP RX ENGINE

SERIAL FPDP TX ENGINE

MUX

DISPARITYCALCULATE

64 x 32COPY MODE

RX FIFO

OPTIONALCRC

GENERATOR

PACKETCONSTRUCT

RATE BALANCEIDLE

INSERT/DELETE

2K x 32TX FIFO

32K x 32FIFO

DMA ENGINE

16K x 32FIFO

DMA ENGINE

SERIAL FPDP CHANNEL 1

CH 1RX

CH 1TX

RX

TX

CH 2

PCIeINTERFACE


RX

TX

CH 3 SERIAL FPDP CHANNEL 3

RX

TX


Copy modedata path


integrated PC developmentsystem for Pentek Cobalt, Onyxand Flexor PCI Express boards. Itwas created to save engineers andsystem integrators the time andexpense associated with buildingand testing a development systemthat ensures optimum perfor-mance of Pentek boards.


Pentek, Inc.

Quad Serial FPDP Interface with Virtex-6 FPGA - XMCModel 71611


family of high performance XMC modulesbased on the Xilinx Virtex-6 FPGA. A multi-channel, gigabit serial interface, it is idealfor interfacing to Serial FPDP data converterboards or as a chassis-to-chassis data link.

The 71611 is fully compatible with theVITA 17.1 Serial FPDP specification. Itsbuilt-in data transfer features make it acomplete turnkey solution. For users whorequire application-specific functions, the71611 serves as a flexible platform fordeveloping and deploying custom FPGAprocessing IP.

In addition to supporting PCI Express asa native interface, the Model 71611 includesa general purpose connector for application-specific I/O.


a Virtex-6 FPGA. All of the board’s data andcontrol paths are accessible by the FPGA,enabling factory-installed functions includingdata transfer and memory control. TheCobalt Architecture organizes the FPGA asa container for data processing applicationswhere each function exists as an intellectualproperty (IP) module.

IP modules for DDR3 SDRAM memories,controllers for data routing and flow control,

CRC support, advanced DMA engines, anda PCIe interface complete the factory-installedfunctions and enable the 71611 to operateas a complete turnkey solution withoutthe need to develop any FPGA IP.





with a variety of different FPGAs to matchthe specific requirements of the processingtask. Supported FPGAs include: LX240T,SX315T, or SX475T. The SXT parts featureup to 2016 DSP48E slices and are ideal formodulation/demodulation, encoding/decoding, encryption/decryption, andchannelization of the signals betweentransmission and reception. For applicationsnot requiring large DSP resources, the lower-cost LXT FPGA can be installed.

Option -104 installs the P14 PMC connec-tor with 20 pairs of LVDS connections tothe FPGA for custom I/O. ➤



17.1 specification■ Fiber optic or copper serial

interfaces■ Up to 2 GB of DDR3 SDRAM■ PCI Express interface up to

x8■ LVDS connections to the

Virtex-6 FPGA for custom I/OVIRTEX-6 FPGA

LX240T, SX315T or SX475T

32 16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB


40

LVDSGTX

FPGAGPIO

(option -104)

x8 PCIe

8X

P14PMC

P15XMC


GTXGTXGTXGTX

CH 1 CH 2 CH 3 CH 4






Pentek, Inc.

Quad Serial FPDP Interface with Virtex-6 FPGA - XMCModel 71611


VITA 17.1 Serial FPDP specification. Withthe capability to support 1.0625, 2.125, 2.5,3.125, and 4.25 Gbaud link rates and theoption for multi-mode and single-modeoptical interfaces, the board can work invirtually any system. Programmable modesinclude: flow control in both receive andtransmit directions, CRC support, andcopy/loop modes.


four independent memory banks of DDR3SDRAM. Each memory is 512 MB deep andan integral part of the module’s DMA capa-bilities, providing FIFO memory spacefor creating DMA packets.



standard interface fully compliant with PCIExpress Gen. 1 bus specifications. SupportingPCIe links up to x8, the interface includeseight DMA controllers. Each of the fourSerial FPDP channels includes dedicatedDMA engines for transmit and receive forefficient transfers to and from the module.




Copper Connector Type: Micro TwinaxFiber Optic or Copper Link Rates:1.0625, 2.125, 2.5, 3.125 or 4.25 Gbaud(copper rate depends on cable langth)Fiber Optic or Copper Data TransferRates: 105, 210, 247, 309 or 420 MB/sec(depending on link rate) per serialFPDP port

Field Programmable Gate Array: XilinxVirtex-6 XC6VLX240T, XC6VSX315T,or XC6VSX475T

Custom I/OOption -104: Installs the PMC P14 con-nector with 20 LVDS pairs to the FPGA

MemoryOption 155 or 165: Two 512 MB DDR3SDRAM memory banks, 400 MHz DDR



Size: Standard XMC module,2.91 in. x 5.87 in. ➤


71611 Quad Serial FPDPInterface with Virtex-6FPGA - XMC

Options:










versions

Model Description


8X

PACKETDECONSTRUCT

2K x 32RX FIFO

OPTIONALCRC

CHECK



MUX

DISPARITYCALCULATE

64 x 32COPY MODE

RX FIFO

OPTIONALCRC

GENERATOR

PACKETCONSTRUCT

RATE BALANCEIDLE

INSERT/DELETE

2K x 32TX FIFO

32K x 32FIFO

DMA ENGINE

to optional 512 MBSDRAM buffer

16K x 32FIFO

DMA ENGINE


CH 1RX

CH 1TX

RX

TX


CH 2

PCIeINTERFACE


RX

TX



RX

TX



Copy modedata path




Pentek, Inc.

Quad Serial FPDP Interface with Virtex-6 FPGA - x8 PCIeModel 78611


family of high performance PCIe boardsbased on the Xilinx Virtex-6 FPGA. A multi-channel, gigabit serial interface, it is idealfor interfacing to Serial FPDP data converterboards or as a chassis-to-chassis data link.





IP modules for DDR3 SDRAM memories,controllers for data routing and flow control,CRC support, advanced DMA engines, and

a PCIe interface complete the factory-installedfunctions and enable the 78611 to operateas a complete turnkey solution withoutthe need to develop any FPGA IP.






Option -104 connects 20 pairs of LVDSsignals from the FPGA on PMC P14 to a68-pin DIL ribbon-cable header on the PCIeboard for custom I/O. ➤






Virtex-6 FPGA for custom I/O

VIRTEX-6 FPGA


32 16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



GTXGTXGTXGTX

CH 1 CH 2 CH 3 CH 4

40

LVDS GTX

OptionalFPGAGPIO

8X

68-pinHeader

x8 PCI Express

x8 PCIe






Pentek, Inc.



VITA 17.1 Serial FPDP specification. With thecapability to support 1.0625, 2.125, 2.5, 3.125,and 4.25 Gbaud link rates and the option formulti-mode and single-mode optical inter-faces, the board can work in virtually anysystem. Programmable modes include: flowcontrol in both receive and transmit directions,CRC support, and copy/loop modes.


four independent memory banks of DDR3SDRAM. Each memory is 512 MB deep andan integral part of the board’s DMA capa-bilities, providing FIFO memory spacefor creating DMA packets.



standard interface fully compliant with PCIExpress Gen. 1 bus specifications. SupportingPCIe links up to x8, the interface includeseight DMA controllers. Each of the fourSerial FPDP channels includes dedicatedDMA engines for transmit and receive forefficient transfers to and from the board.




Copper Connector Type: Micro TwinaxFiber Optic or Copper Link Rates:1.0625, 2.125, 2.5, 3.125 or 4.25 Gbaud(copper rate depends on cable langth)Fiber Optic or Copper Data Transfer Rates:105, 210, 247, 309 or 420 MB/sec (depend-ing on link rate) per serial FPDP port

Field Programmable Gate Array: XilinxVirtex-6 XC6VLX240T, XC6VSX315T, orXC6VSX475T

Custom I/OOption -104: Connects 20 pairs of LVDSsignals from the FPGA on PMC P14 to a68-pin DIL ribbon-cable header on thePCIe board for custom I/O.







Options:









Model Description


8X

PACKETDECONSTRUCT

2K x 32RX FIFO

OPTIONALCRC

CHECK



MUX

DISPARITYCALCULATE

64 x 32COPY MODE

RX FIFO

OPTIONALCRC

GENERATOR

PACKETCONSTRUCT

RATE BALANCEIDLE

INSERT/DELETE

2K x 32TX FIFO

32K x 32FIFO

DMA ENGINE


16K x 32FIFO

DMA ENGINE


CH 1RX

CH 1TX

RX

TX


CH 2

PCIeINTERFACE


RX

TX



RX

TX



Copy modedata path




Pentek, Inc.



family of high performance PCIe boardsbased on the Xilinx Virtex-6 FPGA. A multi-channel, gigabit serial interface, it is idealfor interfacing to Serial FPDP data converterboards or as a chassis-to-chassis data link.












Option -104 connects 20 pairs of LVDSsignals from the FPGA on PMC P14 to a68-pin DIL ribbon-cable header on the PCIeboard for custom I/O. ➤







VIRTEX-6 FPGA


32 16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



GTXGTXGTXGTX

CH 1 CH 2 CH 3 CH 4

40

LVDS GTX

OptionalFPGAGPIO

8X

68-pinHeader

x8 PCI Express

x8 PCIe






Pentek, Inc.



VITA 17.1 Serial FPDP specification. With thecapability to support 1.0625, 2.125, 2.5, 3.125,and 4.25 Gbaud link rates and the option formulti-mode and single-mode optical inter-faces, the board can work in virtually anysystem. Programmable modes include: flowcontrol in both receive and transmit directions,CRC support, and copy/loop modes.


four independent memory banks of DDR3SDRAM. Each memory is 512 MB deep andan integral part of the board’s DMA capa-bilities, providing FIFO memory spacefor creating DMA packets.



standard interface fully compliant with PCIExpress Gen. 1 bus specifications. SupportingPCIe links up to x8, the interface includeseight DMA controllers. Each of the fourSerial FPDP channels includes dedicatedDMA engines for transmit and receive forefficient transfers to and from the board.




Copper Connector Type: Micro TwinaxFiber Optic or Copper Link Rates:1.0625, 2.125, 2.5, 3.125 or 4.25 Gbaud(copper rate depends on cable langth)Fiber Optic or Copper Data Transfer Rates:105, 210, 247, 309 or 420 MB/sec (depend-ing on link rate) per serial FPDP port


Custom I/OOption -104: Connects 20 pairs of LVDSsignals from the FPGA on PMC P14 to a68-pin DIL ribbon-cable header on thePCIe board for custom I/O.







Options:









Model Description


8X

PACKETDECONSTRUCT

2K x 32RX FIFO

OPTIONALCRC

CHECK



MUX

DISPARITYCALCULATE

64 x 32COPY MODE

RX FIFO

OPTIONALCRC

GENERATOR

PACKETCONSTRUCT

RATE BALANCEIDLE

INSERT/DELETE

2K x 32TX FIFO

32K x 32FIFO

DMA ENGINE


16K x 32FIFO

DMA ENGINE


CH 1RX

CH 1TX

RX

TX


CH 2

PCIeINTERFACE


RX

TX



RX

TX



Copy modedata path




Pentek, Inc.

Quad Serial FPDP Interface with Virtex-6 FPGA - 3U VPXModel 53611


family of high performance 3U VPX boardsbased on the Xilinx Virtex-6 FPGA. A multi-channel, gigabit serial interface, it is idealfor interfacing to Serial FPDP data converterboards or as a chassis-to-chassis data link.


In addition to supporting PCI Expressover the 3U VPX backplane, the Model53611 includes a general purpose connectorfor application-specific I/O.










Option -104 provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/O. ➤






Virtex-6 FPGA for custom I/O■ 3U VPX form factor provides

a compact, rugged platform■ Compatible with several VITA

standards including:VITA-46, VITA-48 andVITA-65 (OpenVPXTM



VIRTEX-6 FPGA


32 16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



GTXGTXGTXGTX

CH 1 CH 2 CH 3 CH 4

LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

GTX

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1VPX-P2

8X

x8PCIe







Pentek, Inc.





8X

PACKETDECONSTRUCT

2K x 32RX FIFO

OPTIONALCRC

CHECK



MUX

DISPARITYCALCULATE

64 x 32COPY MODE

RX FIFO

OPTIONALCRC

GENERATOR

PACKETCONSTRUCT

RATE BALANCEIDLE

INSERT/DELETE

2K x 32TX FIFO

32K x 32FIFO

DMA ENGINE


16K x 32FIFO

DMA ENGINE


CH 1RX

CH 1TX

RX

TX


CH 2

PCIeINTERFACE


RX

TX



RX

TX



Copy modedata path


four independent memory banks of DDR3SDRAM. Each memory is 512 MB deep andan integral part of the board’s DMA capabili-ties, providing FIFO memory space forcreating DMA packets.


standard interface fully compliant with PCIExpress Gen. 1 bus specifications. Support-ing PCIe links up to x8, the interfaceincludes eight DMA controllers. Each ofthe four Serial FPDP channels includesdedicated DMA engines for transmit andreceive for efficient transfers to and fromthe board.

Crossbar SwitchThe 53611 features a unique high-speed

switching configuration. A fabric-transpar-ent crossbar switch bridges numerousinterfaces and components on the boardusing gigabit serial data paths with nolatency. Programmable signal input equal-ization and output pre-emphasis settingsenable optimization. Data paths can be se-lected as single (1X) lanes, or groups of fourlanes (4X).


Pentek, Inc.







Custom I/OOption -104: Provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/O




Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)




52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No


53611 Quad Serial FPDPInterface with Virtex-6FPGA - 3U VPX

Options:










versions

Model Description



integrated development systemfor Pentek Cobalt, Onyx andFlexor 3U VPX boards. It wascreated to save engineers andsystem integrators the time andexpense associated with buildingand testing a development systemthat ensures optimum perfor-mance of Pentek boards.


Pentek, Inc.



family of high performance 3U VPX boardsbased on the Xilinx Virtex-6 FPGA. A multi-channel, gigabit serial interface, it is idealfor interfacing to Serial FPDP data converterboards or as a chassis-to-chassis data link.


In addition to supporting PCI Expressover the 3U VPX backplane, the Model52611 includes a general-purpose connectorfor application-specific I/O.










Option -104 provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/O. ➤


solution■ Fully compliant with VITA 17.1

specification■ Fiber optic or copper serial



Virtex-6 FPGA for custom I/O■ 3U VPX form factor provides

a compact, rugged platform■ Compatible with several VITA

standards including:VITA-46, VITA-48 andVITA-65 (OpenVPXTM



VIRTEX-6 FPGA


32 16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



GTXGTXGTXGTX

CH 1 CH 2 CH 3 CH 4

LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P1VPX-P2





GTX

4X

x4PCIe



Pentek, Inc.




Memory ResourcesThe 52611 architecture supports up to four

independent memory banks of DDR3SDRAM. Each memory is 512 MB deepand an integral part of the board’s DMAcapabilities, providing FIFO memoryspace for creating DMA packets.






Custom I/OOption -104: Provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/O


PCI-Express InterfacePCI Express Bus: Gen. 1: x4


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)





Options:










versions

Model Description

8267 VPX Development SystemSee 8267 Datasheet forOptions VIRTEX-6 FPGA DATAFLOW DETAILVIRTEX-6 FPGA DATAFLOW DETAIL

4X

PACKETDECONSTRUCT

2K x 32RX FIFO

OPTIONALCRC

CHECK



MUX

DISPARITYCALCULATE

64 x 32COPY MODE

RX FIFO

OPTIONALCRC

GENERATOR

PACKETCONSTRUCT

RATE BALANCEIDLE

INSERT/DELETE

2K x 32TX FIFO

32K x 32FIFO

DMA ENGINE


16K x 32FIFO

DMA ENGINE


CH 1RX

CH 1TX

RX

TX


CH 2

PCIeINTERFACE


RX

TX



RX

TX



Copy modedata path


industry-standard interface fullycompliant with PCI Express Gen. 1bus specifications. Supporting PCIelinks up to x4, the interfaceincludes eight DMA controllers.Each of the four Serial FPDPchannels includes dedicatedDMA engines for transmit andreceive for efficient transfers toand from the board.


52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No




Pentek, Inc.

Quad or Octal Serial FPDP Interface with Virtex-6 FPGA -6U OpenVPX



of the Cobalt® family of high performance6U OpenVPX boards based on the XilinxVirtex-6 FPGA. They consist of one ortwo Model 71611 XMC modules mountedon a VPX carrier board.


These models are fully compatible withthe VITA 17.1 Serial FPDP specification.Their built-in data transfer features makethem complete turnkey solutions. For userswho require application-specific functions,they serve as flexible platforms for developingand deploying custom FPGA processing IP.


one or two Virtex-6 FPGAs. All of the board’sdata and control paths are accessible by theFPGA, enabling factory-installed functionsincluding data transfer and memory control.The Cobalt Architecture organizes the FPGAas a container for data processing applicationswhere each function exists as an intellectualproperty (IP) module.


a PCIe interface complete the factory-installedfunctions and enable these models to operateas complete turnkey solutions withoutthe need to develop any FPGA IP.






Option -104 provides 20 LVDS pairsbetween the FPGA and the VPX P3 connector,Model 57611; P3 and P5, Model 58611. ➤

Features■ Four or eight channels of

Serial FPDP interface

■ Fully compliant with VITA17.1 specification

■ Fiber optic or copper serialinterfaces

■ One or two Virtex-6 FPGAs■ Up to 2 or 4 GB of DDR3

SDRAM■ PCI Express interface up to

x8■ Optional LVDS connections



New!

New!

New!

New!

New!

VIRTEX-6 FPGA


32 16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



GTXGTXGTXGTX

CH 1 CH 2 CH 3 CH 4





LVDS GTX

40 8X

FPGAI/O

Option -104

VPX BACKPLANE

PCIeGen. 2 x8

VPX-P1

PCIe-to PCIeSWITCH

From/To

Other XMC

Module of

Model 58611

VPX-P3







Model 58611


Pentek, Inc.

Quad or Octal Serial FPDP Interface with Virtex-6 FPGA -6U OpenVPX


➤➤➤➤➤ Serial FPDP InterfaceThese models are fully compatible with

the VITA 17.1 Serial FPDP specification.With the capability to support 1.0625, 2.125,2.5, 3.125, and 4.25 Gbaud link rates andthe option for multi-mode and single-modeoptical interfaces, the boards can work invirtually any system. Programmable modesinclude: flow control in both receive andtransmit directions, CRC support, andcopy/loop modes.

Memory ResourcesThe architecture supports up to four or

eight independent memory banks of DDR3SDRAM. Each memory is 512 MB deep andan integral part of the board’s DMA capabili-ties, providing FIFO memory space forcreating DMA packets.






58611 Octal Serial FPDPInterface with twoVirtex-6 FPGAs - 6U VPX

Options:










versions

Model Description

8264 VPX Development System.See 8264 Datasheet forOptions VIRTEX-6 FPGA DATAFLOW DETAILVIRTEX-6 FPGA DATAFLOW DETAIL

8X

PACKETDECONSTRUCT

2K x 32RX FIFO

OPTIONALCRC

CHECK



MUX

DISPARITYCALCULATE

64 x 32COPY MODE

RX FIFO

OPTIONALCRC

GENERATOR

PACKETCONSTRUCT

RATE BALANCEIDLE

INSERT/DELETE

2K x 32TX FIFO

32K x 32FIFO

DMA ENGINE


16K x 32FIFO

DMA ENGINE


CH 1RX

CH 1TX

RX

TX


CH 2

PCIeINTERFACE


RX

TX



RX

TX



Copy modedata path


Number of Connectors: 4 or 8Fiber Optic Connector Type: LC



Field Programmable Gate Arrays: XilinxVirtex-6 XC6VLX240T, XC6VSX315T, orXC6VSX475T

Custom I/OOption -104: Provides 20 LVDS pairsbetween the FPGA and the VPX P3connector, Model 57611; P3 and P5,Model 58611


PCI Express InterfacePCI Express Bus: Gen. 1 or 2: x4 or x8


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) ➤




Pentek, Inc.

Quad or Octal Serial FPDP Interface with Virtex-6 FPGA - cPCIModels 72611,73611 and 74611


members of the Cobalt® family of high-performance CompactPCI boards basedon the Xilinx Virtex-6 FPGA. They consistof one or two Model 71611 XMC modulesmounted on a cPCI carrier board.


These models are fully compatible withthe VITA 17.1 Serial FPDP specification.Their built-in data transfer features makethem complete turnkey solutions. For userswho require application-specific functions,they serve as flexible platforms for developingand deploying custom FPGA processing IP.


one or two Virtex-6 FPGAs. All of the board’sdata and control paths are accessible by theFPGA, enabling factory-installed functionsincluding data transfer and memory control.The Cobalt Architecture organizes the FPGAas a container for data processing applicationswhere each function exists as an intellectualproperty (IP) module.


a cPCI interface complete the factory-installedfunctions and enable these models to operateas a complete turnkey solutions withoutthe need to develop any FPGA IP.







Features■ Four or eight channels of

Serial FPDP interface

■ Fully compliant with VITA17.1 specification

■ Fiber optic or copper serialinterfaces

■ One or two Virtex-6 FPGAs■ Up to 2 or 4 GB of DDR3

SDRAM■ LVDS connections to the


VIRTEX-6 FPGA


32 16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



GTXGTXGTXGTX

CH 1 CH 2 CH 3 CH 4




VIRTEX-6 FPGA

MODEL 73611

INTERFACES ONLY

PCIeto PCI

BRIDGE

40

LVDS GTX

OptionalFPGA I/O(option 104)


J2

PCIeto PCI

BRIDGE

PCIto PCI

BRIDGE

From/To Other

XMC Module of

MODEL 74611

40

LVDS GTX

x4 PCIe


4X

J3







Pentek, Inc.

Quad or Octal Serial FPDP Interface with Virtex-6 FPGA - cPCIModels 72611,73611 and 74611

➤➤➤➤➤ Serial FPDP InterfaceThese models are fully compatible with

the VITA 17.1 Serial FPDP specification.With the capability to support 1.0625, 2.125,2.5, 3.125, and 4.25 Gbaud link rates andthe option for multi-mode and single-modeoptical interfaces, the boards can work invirtually any system. Programmable modesinclude: flow control in both receive andtransmit directions, CRC support, andcopy/loop modes.

Memory ResourcesThe architecture supports up to four or

eight independent memory banks of DDR3SDRAM. Each memory is 512 MB deep andan integral part of the board’s DMA capabili-ties, providing FIFO memory space forcreating DMA packets.



dard interface fully compliant with PCI-Xbus specifications. The interface includesmultiple DMA controllers for efficient trans-fers to and from the board. Data widths of32 or 64 bits (32 bits only, Model 73611) anddata rates of 33 and 66 MHz are supported.Ordering Information

Model Description

72611 Quad Serial FPDPInterface with Virtex-6FPGA - 6U cPCI

73611 Quad Serial FPDPInterface with Virtex-6FPGA - 3U cPCI

74611 Octal Serial FPDPInterface with Virtex-6FPGA - 6U cPCI

Options:




-104 LVDS I/O between theFPGA and J2 connector,Model 73611; J3connector, Model 72611;J3 and J5 connectors,Model 74611




-281 Multi-mode optical serialinterfaces VIRTEX-6 FPGA DATAFLOW DETAILVIRTEX-6 FPGA DATAFLOW DETAIL

4X

PACKETDECONSTRUCT

2K x 32RX FIFO

OPTIONALCRC

CHECK



MUX

DISPARITYCALCULATE

64 x 32COPY MODE

RX FIFO

OPTIONALCRC

GENERATOR

PACKETCONSTRUCT

RATE BALANCEIDLE

INSERT/DELETE

2K x 32TX FIFO

32K x 32FIFO

DMA ENGINE


16K x 32FIFO

DMA ENGINE


CH 1RX

CH 1TX

RX

TX


CH 2

PCIeINTERFACE


RX

TX



RX

TX



Copy modedata path


Number of Connectors: 4 or 8Fiber Optic Connector Type: LC




Custom I/OOption -104: provides 20 LVDS pairsbetween the FPGA and the J2 connector,Model 73611; J3 connector, Model 72611;J3 and J5 connectors, Model 74611


PCI-X InterfacePCI-X Bus: 32- or 64-bit at 33 or 66 MHzModel 73611: 32-bit at 33 or 66 MHz


Size: Standard 6U or 3U cPCI board ➤


Pentek, Inc.

Quad Serial FPDP Interface with Virtex-6 FPGA - AMCModel 56611


family of high-performance AMC modulesbased on the Xilinx Virtex-6 FPGA. A multi-channel, gigabit serial interface, it is idealfor interfacing to Serial FPDP data converterboards or as a chassis-to-chassis data link.

The 56611 is fully compatible with theVITA 17.1 Serial FPDP specification. Itsbuilt-in data transfer features make it acomplete turnkey solution. For users whorequire application-specific functions, the56611 serves as a flexible platform fordeveloping and deploying custom FPGAprocessing IP. In addition to supportingPCI Express Gen. 2 as a native interface,the Model 56611 includes a front panelgeneral-purpose connector for application-specific I/O.



IP modules for DDR3 SDRAM memories,controllers for data routing and flow control,

CRC support, advanced DMA engines, anda PCIe interface complete the factory-installedfunctions and enable the 56611 to operateas a complete turnkey solution withoutthe need to develop any FPGA IP.











x8■ AMC.1 compliant



VIRTEX-6 FPGA


32 16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB



GTXGTXGTXGTX

CH 1 CH 2 CH 3 CH 4





40

LVDSGTX


x8 PCIe

8X

FrontPanel

AMCPorts 4 to 11

IPMICONTROLLER

RS-232

FrontPanel


Pentek, Inc.

Quad Serial FPDP Interface with Virtex-6 FPGA - AMCModel 56611




four independent memory banks of DDR3SDRAM. Each memory is 512 MB deep andan integral part of the module’s DMA capa-bilities, providing FIFO memory spacefor creating DMA packets.



standard interface fully compliant with PCIExpress Gen. 1 bus specifications. SupportingPCIe links up to x8, the interface includeseight DMA controllers. Each of the fourSerial FPDP channels includes dedicatedDMA engines for transmit and receive forefficient transfers to and from the module.





Field Programmable Gate Array: XilinxVirtex-6 XC6VLX240T, XC6VSX315T,or XC6VSX475T






Size: Single-width, full-height AMC mod-ule, 2.89 in. x 7.11 in. ➤➤➤➤➤


56611 Quad Serial FPDPInterface with Virtex-6FPGA - AMC

Options:










versions VIRTEX-6 FPGA DATAFLOW DETAILVIRTEX-6 FPGA DATAFLOW DETAIL

8X

PACKETDECONSTRUCT

2K x 32RX FIFO

OPTIONALCRC

CHECK



MUX

DISPARITYCALCULATE

64 x 32COPY MODE

RX FIFO

OPTIONALCRC

GENERATOR

PACKETCONSTRUCT

RATE BALANCEIDLE

INSERT/DELETE

2K x 32TX FIFO

32K x 32FIFO

DMA ENGINE


16K x 32FIFO

DMA ENGINE


CH 1RX

CH 1TX

RX

TX


CH 2

PCIeINTERFACE


RX

TX



RX

TX



Copy modedata path




Pentek, Inc.

1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch. 6.4 GHz D/A,Kintex UltraScale FPGA - XMCModel 71141

General InformationModel 71141 is a member of the JadeTM

family of high-performance XMC modules.The Jade architecture embodies a new stream-lined approach to FPGA-based boards,simplifying the design to reduce power andcost, while still providing some of the high-est-performance FPGA resources availabletoday. Designed to work with Pentek’s newNavigatorTM Design Suite of tools, the com-bination of Jade and Navigator offers usersan efficient path to developing and deployingFPGA-based data acquisition and processing.

The 71141 is a high-speed analog-to-digi-tal and digital-to-analog converter withprogrammable DDCs (digital downcon-verters) and DUCs (digital upconverters).It is suitable for connection to HF or IF portsof a communications or radar system. Itsbuilt-in data capture and generator featuresoffer an ideal turnkey solution as well as aplatform for developing and deployingcustom FPGA-processing IP.

It includes a 6.4 GHz, 12-bit A/D con-verter, dual 6.4 GHz, 14-bit D/As and alarge DDR4 memory. In addition to support-ing PCI Express Gen. 3 as a native interface,Model 71141 includes optional high-band-width connections to the Kintex UltraScaleFPGA for custom digital I/O.

The Jade ArchitectureEvolved from the proven designs of the

Pentek Cobalt and Onyx families, Jade raisesthe processing performance with the newflagship family of Kintex UltraScale FPGAsfrom Xilinx. As the central feature of theboard architecture, the FPGA has access toall data and control paths, enabling factory-

installed functions including data multi-plexing, channel selection, data packing,gating, triggering and memory control. TheJade architecture organizes the FPGA as acontainer for data-processing applicationswhere each function exists as an intellectualproperty (IP) module.

Each member of the Jade family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The 71141 factory-installed functionsinclude two A/D acquisition and two D/Awaveform generator IP modules. In addi-tion, IP modules for DDR4 SDRAMmemories, a controller for all data clockingand synchronization functions, a test signalgenerator and a PCIe interface completethe factory-installed functions and enablethe 71141 to operate as a complete turnkeysolution, without the need to develop anyFPGA IP.


functions, users can install their own customIP for data processing. Pentek NavigatorFPGA Design Kits include all of the factory-installed modules as documented sourcecode. Developers can integrate their ownIP with the Pentek factory-installed functionsor use the Navigator kit to completelyreplace the Pentek IP with their own.

Xilinx Kintex UltraScale FPGAThe Kintex UltraScale FPGA site can be

populated with a range of FPGAs to matchthe specific requirements of the processingtask, spanning the KU035 through KU115.The KU115 features 5520 DSP48E2 slices ➤



■ Supports Xilinx KintexUltraScale FPGAs



■ Programmable DDCs(Digital Downconverters)

■ Two 6.4 GHz, 14-bit D/As■ Programmable DUCs

(Digital Upconverters)■ 5 GB of DDR4 SDRAM■ µSync clock/sync bus for



with switched fabric interfaces■ Optional LVDS and gigabit

serial connections to theFPGA for custom I/O


NewNewNewNewNew


Pentek, Inc.


➤ and is ideal for modulation/demodulation,encoding/decoding, encryption/decryption,and channelization of the signals betweentransmission and reception. For applicationsnot requiring large DSP resources or logic,a lower-cost FPGA can be installed.

Option -104 installs the P14 PMC connec-tor with 24 pairs of LVDS connections to theFPGA for custom I/O.

Option -105 installs the P16 XMC connec-tor with 8X gigabit link to the FPGA tosupport serial protocols.


inputs on a pair of front panel SSMC connec-tors with transformer-coupling into a TexasInstruments ADC12DJ3200 12-bit A/D.The converter operates in single-channelinterleaved mode with a sampling rate of6.4 GHz and an input bandwidth of 7.9 GHz;or, in dual-channel mode with a sampling rateof 3.2 GHz and input bandwidth of 8.1 GHz.

The A/D’s built-in digital down-convert-ers support 2x decimation in real outputmode and 4x, 8x, or 16x decimation in com-plex output mode. The A/D digital outputsare delivered into the Kintex UltraScaleFPGA for signal processing, data capture orfor routing to other module resources.

Digital Upconverter and D/A StageA TI DAC38RF82 DUC (digital upcon-

verter) and D/A accepts a baseband real orcomplex data stream from the FPGA andprovides that input to the upconvert, inter-polate and dual D/A stages. When operatingas a DUC, it interpolates and translates real

A/D Acquisition IP ModuleThe 71141 features two A/D

Acquisition IP Modules foreasy capture and data moving.The IP module can receive datafrom the A/D, or a test signalgenerator. The IP module hasassociated a 5 GB DDR4memory for buffering data inFIFO mode or for storing datain transient capture mode.

In single-channel mode, allof 5 GB are used to store thesingle-channel of input data. Indual-channel mode, one half ofthe memory stores data frominput channel 1 and the otherhalf stores data from inputchannel 2. In both modes,continuous, full-rate transientcapture of 12-bit data issupported.

The memory bank is support-ed with a DMA engine formoving A/D data through thePCIe interface. This powerfullinked-list DMA engine is capableof a unique Acquisition GateDriven mode. In this mode, thelength of a transfer performedby a link definition need not beknown prior to data acquisition;rather, it is governed by thelength of the acquisition gate.This is extremely useful in appli-cations where an external gatedrives acquisition and the exactlength of that gate is not knownor is likely to vary.


D/A Waveform Generator IPModule

The Model 71141 factory in-stalled functions include asophisticated D/A WaveformGenerator IP module. It allowsusers to easily record to the dualD/As waveforms stored ineither on-board memory or off-board host memory.

or complex baseband input signals. Itdelivers real or quadrature (I+Q) analogoutputs to the dual 14-bit D/A converter.Analog output is through a pair of frontpanel SSMC connectors.

If translation is disabled, the DAC38RF82acts as a dual interpolating 14-bit D/A. Inboth modes the DAC38RF82 provides inter-polation factors from 1x to 24x.

Memory ResourcesThe 71141 architecture supports a 5 GB

bank of DDR4 SDRAM memory.User-installed IP along with the Pentek-

supplied DDR4 controller core within theFPGA can take advantage of the memoryfor custom applications.



Clocking and SynchronizationThe 71141 accepts a sample clock via a

front panel SSMC connector. A second frontpanel SSMC accepts a TTL signal that canfunction as Gate, PPS or Sync.

A front panel µSync bus connector allowsmultiple modules to be synchronized, idealfor multichannel systems. The µSync busincludes gate, reset, and in and out refer-ence clock signals. The Model 7192 high- speedsync module can be used to drive the syncbus to synchronize multichannel systems. ➤


Pentek, Inc.



71141 1-Ch. 6.4 GHz or 2-Ch.3.2 GHz A/D, 2-Ch.6.4 GHz D/A, KintexUltraScale FPGA - XMC

Options:

- 084 XCKU060-2 FPGA


- 104 LVDS FPGA I/O throughP14 connector

- 105 Gigabit serial FPGA I/Othrough P16 connector

- 702 Air cooled, Level L2

- 713 Conduction-cooled,Level L3

Contact Pentek for completespecifications of rugged andconduction-cooled versions



A/D ConverterType: ADC12DJ3200Sampling Rate: Single-channel mode:6.4 GHz; dual-channel mode: 3.2 GHzResolution: 12 bitsInput Bandwidth: single-channel mode:7.9 GHz; dual-channel mode: 8.1 GHz

D/A ConvertersType: Texas Instruments DAC38RF82Output Sampling Rate: 6.4 GHz.Resolution: 14 bits




Field Programmable Gate ArrayStandard: Xilinx Kintex UltraScaleXCKU035-2Option -084: Xilinx Kintex UltraScaleXCKU060-2Option -087: Xilinx Kintex UltraScaleXCKU115-2

Development SystemsThe SPARK Development

Systems are fully-integratedplatforms for Pentek Cobalt,Onyx, Jade and Flexor boards.Available in a PC rackmount(Model 8266), a 3U VPX chassis(Model 8267) or a 6U VPX chassis(Model 8264), they were createdto save engineers and systemintegrators the time and expenseassociated with building and test-ing a development system. EachSPARK system is delivered withthe Pentek board(s) and requiredsoftware installed and equippedwith sufficient cooling and powerto ensure optimum performance.

Custom I/OOption -104: Installs the PMC P14 con-nector with 24 LVDS pairs to the FPGAOption -105 (only available with op-tion -084 or -087): Installs the XMC P16connector configurable as one 8X giga-bit serial link to the FPGA

MemoryType: DDR4 SDRAMSize: 5 GBSpeed: 1200 MHz (2400 MHz DDR)


EnvironmentalStandard: L0 (air cooled)

Operating Temp: 0° to 50° CStorage Temp: –20° to 90° CRelative Humidity: 0 to 95%, non-condensing

Option -702: L2 (air cooled)Operating Temp: –20° to 65° CStorage Temp: –40° to 100° CRelative Humidity: 0 to 95%, non-condensing

Option -713: L3 (conduction cooled)Operating Temp: –40° to 70° CStorage Temp: –50° to 100° CRelative Humidity: 0 to 95%, non-condensing

Size: XMC module 2.910 in x 5.870 in(74.00 mm x 149.00 mm)

Note: Not all combinations of sample rates, decimations and interpolations are availabledue to JESD204B and PCIe rate limitiations.





Pentek, Inc.

1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch. 6.4 GHz D/A,Kintex UltraScale FPGA - PCIeModel 78141


family of high-performance PCIe boards.The Jade architecture embodies a new stream-lined approach to FPGA-based boards,simplifying the design to reduce power andcost, while still providing some of the high-est-performance FPGA resources availabletoday. Designed to work with Pentek’s newNavigatorTM Design Suite of tools, the com-bination of Jade and Navigator offers usersan efficient path to developing and deployingFPGA-based data acquisition and processing.












radio interface solution■ Supports Xilinx Kintex

UltraScale FPGAs■ One-channel mode with


3.2 GHz, 12-bit A/Ds■ Programmable DDCs

(Digital Downconverters)■ Two 6.4 GHz, 14-bit D/As

■ Programmable DUCs(Digital Upconverters)



interface up to x8■ Optional LVDS and gigabit


NewNewNewNewNew

TIMING BUSGENERATOR


KINTEX ULTRASCALE FPGA

KU035, KU060 or KU115


A/D Clock/Sync Bus


48

LVDS

Option -104FPGALVDSI/O

68-pinHeader

GTH

4X

Dual 4XSerialConnector

GTH

PCIeGen. 3 x8

CONFIGFLASH1 GB

DDR4SDRAM

5 GB

808X

Option -105*FPGAGigabitSerial I/O

FREQUENCYSYNTHESIZER

Gate In A

Gate In B

Sync Bus

Sync

Sys Ref

6.4 GHz14-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

RF In

RFXFORMR


3.2 GHz (2 Channel)12-BIT A/D

RF In

RFXFORMR

RF Out

RFXFORMR

RF Out

RFXFORMR

D/A Clock/Sync Bus

6.4 GHz14-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALDOWNCONVERT

*Option 105 available withKU060 or KU115 only


Pentek, Inc.



Option -104 installs 24 pairs of LVDS con-nections from the FPGA to a 68-pin headerfor custom I/O.

Option -105 provides one 8X gigabit linkbetween the FPGA and a serial connectorto support serial protocols.







Acquisition IP Modules foreasy capture and data moving.The IP module can receive datafrom the A/D, or a test signalgenerator. The IP module hasassociated a 5 GB DDR4memory for buffering data inFIFO mode or for storing datain transient capture mode.















A front panel µSync bus connector allowsmultiple boards to be synchronized, ideal formultichannel systems. The µSync bus in-cludes gate, reset, and in and out referenceclock signals. The Model 7892 high- speed syncboard can be used to drive the sync bus tosynchronize multichannel systems. ➤


Pentek, Inc.



78141 1-Ch. 6.4 GHz or 2-Ch.3.2 GHz A/D, 2-Ch.6.4 GHz D/A, KintexUltraScale FPGA - PCIe

Options:



- 104 LVDS FPGA I/O

- 105 Gigabit serial FPGA I/O












Custom I/OOption -104: installs 24 pairs of LVDSconnections from the FPGA to a 68-pinheader for custom I/OOption -105 (only available with op-tion -084 or -087): provides one 8Xgigabit link between the FPGA and aserial connector to support serial protocols






Size: PCIe card 4.380 in x 7.130 in(111.25 mm x 181.10 mm)


to support serial protocols.





Pentek, Inc.

1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch. 6.4 GHz D/A,Kintex UltraScale FPGA - 3U VPXModel 53141


family of high-performance 3U VPX boards.The Jade architecture embodies a new stream-lined approach to FPGA-based boards,simplifying the design to reduce power andcost, while still providing some of the high-est-performance FPGA resources availabletoday. Designed to work with Pentek’s newNavigatorTM Design Suite of tools, the com-bination of Jade and Navigator offers usersan efficient path to developing and deployingFPGA-based data acquisition and processing.


It includes a 6.4 GHz, 12-bit A/D con-verter, dual 6.4 GHz, 14-bit D/As and a largeDDR4 memory. In addition to supporting PCIExpress Gen. 3 as a native interface, Model53141 includes optional high-bandwidthconnections to the Kintex UltraScale FPGAfor custom digital I/O.























NewNewNewNewNew

TIMING BUSGENERATOR



KU035, KU060 or KU115


A/D Clock/Sync Bus



Gate In A

Gate In B

Sync Bus

Sync

Sys Ref

6.4 GHz14-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

RF In

RFXFORMR



RF In

RFXFORMR

RF Out

RFXFORMR

RF Out

RFXFORMR

D/A Clock/Sync Bus

6.4 GHz14-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALDOWNCONVERT

CONFIGFLASH1 GB

DDR4SDRAM

5 GB

80

LVDS

40

Option -104FPGAGPI/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

VPX-P1

GTHGTH

Gigabit Serial I/O

8X 8X

x8PCIe

CROSSBARSWITCH

VPX-P2

VPX BACKPLANE

Model 53141CORS (left)and Rygged versions


Pentek, Inc.



Option -104 installs 24 pairs of LVDS con-nections between the FPGA and the VPX P2connector the for custom I/O.








Acquisition IP Modules foreasy capture and data moving.The IP module can receive datafrom the A/D, or a test signalgenerator. The IP module hasassociated a 5 GB DDR4 memoryfor buffering data in FIFO modeor for storing data in transientcapture mode.















A front panel µSync bus connector allowsmultiple boards to be synchronized, ideal formultichannel systems. The µSync bus in-cludes gate, reset, and in and out referenceclock signals. The Model 5292 high- speed syncboard can be used to drive the sync bus tosynchronize multichannel systems. ➤

fromA/D Ch 1

fromA/D Ch 2

INPUT MULTIPLEXER

D/AWAVEFORMGENERATORIP MODULE

toD/A Ch 1

TESTSIGNAL

GENERATOR

MUX

DATAUNPACKING

PCIe INTERFACE

GigabitSerial I/O

PCIeFPGAGPIO


DDR4Memory

KINTEX ULTRASCALE FPGA DATAFLOW DETAILKINTEX ULTRASCALE FPGA DATAFLOW DETAIL

8X8X 40

DMAENGINE

SINGLE CH

DATAUNPACKING

DMAENGINEDUAL CH

WAVEFORMGENERATOR

DMAENGINE

OUTPUT MULTIPLEXER

toDDR4

Memory

MEMORYCONTROL

TESTSIGNAL

GENERATOR

A/DACQUISITIONIP MODULE 1


METADATAGENERATORto

DDR4SDRAM

MEMORYCONTROL

MUX




METADATAGENERATORto

DDR4SDRAM

MEMORYCONTROL

MUX


toD/A Ch 2


Pentek, Inc.



53141 1-Ch. 6.4 GHz or 2-Ch.3.2 GHz A/D, 2-Ch.6.4 GHz D/A, KintexUltraScale FPGA - 3U VPX

Options:



- 104 LVDS FPGA I/O



- 713 Convection cooled,Level L3


switching configuration. A fabric-transparentcrossbar switch bridges numerous interfacesand components on the board using giga-bit serial data paths with no latency. Datapaths can be selected as single (1X) lanes, orgroups of four lanes (4X).











Custom I/OOption -104 provides 24 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/O.Option -105 provides one 4X gigabit linkbetween the FPGA and the VPX P1 con-nector to support serial protocols.







Size: 3U VPX board 3.037 in. x 6.717 in. (100.0 mm x 170.6 mm)

_______________________________________



52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No


products: the 52xxx and the 53xxx. For moreinformation on a 53xxx product, please referto the product datasheet. The table belowprovides a comparison of their many features.





Pentek, Inc.



family of high-performance PCIe modules.The Jade architecture embodies a new stream-lined approach to FPGA-based boards,simplifying the design to reduce power andcost, while still providing some of the high-est-performance FPGA resources availabletoday. Designed to work with Pentek’s newNavigatorTM Design Suite of tools, the com-bination of Jade and Navigator offers usersan efficient path to developing and deployingFPGA-based data acquisition and processing.

























NewNewNewNewNew

TIMING BUSGENERATOR



KU035, KU060 or KU115


A/D Clock/Sync Bus



Gate In A

Gate In B

Sync Bus

Sync

Sys Ref

6.4 GHz14-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

RF In

RFXFORMR



RF In

RFXFORMR

RF Out

RFXFORMR

RF Out

RFXFORMR

D/A Clock/Sync Bus

6.4 GHz14-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALDOWNCONVERT

VPX BACKPLANE

CONFIGFLASH1 GB

DDR4SDRAM

5 GB

8048

Option -104FPGAGPI/O

Option -105GigabitSerial I/O

8X4X

x4PCIe

VPX-P2 VPX-P1

Model 52141CORS (left)and Rygged versions


Pentek, Inc.



Option -104 installs 24 pairs of LVDS con-nections from the FPGA to a 68-pin headerfor custom I/O.













The Model 52141 factory-installed functions include asophisticated D/A WaveformGenerator IP module. It allowsusers to easily record to the dualD/As waveforms stored ineither on-board memory or off-board host memory.










A front panel µSync bus connector allowsmultiple boards to be synchronized, ideal formultichannel systems. The µSync bus in-cludes gate, reset, and in and out referenceclock signals. The Model 5292 high-speed syncboard can be used to drive the sync bus tosynchronize multichannel systems. ➤

fromA/D Ch 1

fromA/D Ch 2

INPUT MULTIPLEXER


toD/A Ch 1

TESTSIGNAL

GENERATOR

MUX

DATAUNPACKING

PCIe INTERFACE

GigabitSerial I/O

PCIeFPGAGPIO


DDR4Memory


4X8X 48

DMAENGINE

SINGLE CH

DATAUNPACKING

DMAENGINEDUAL CH

WAVEFORMGENERATOR

DMAENGINE

OUTPUT MULTIPLEXER

toDDR4

Memory

MEMORYCONTROL

TESTSIGNAL

GENERATOR



METADATAGENERATORto

DDR4SDRAM

MEMORYCONTROL

MUX




METADATAGENERATORto

DDR4SDRAM

MEMORYCONTROL

MUX


toD/A Ch 2


Pentek, Inc.



52141 1-Ch. 6.4 GHz or 2-Ch.3.2 GHz A/D, 2-Ch.6.4 GHz D/A, KintexUltraScale FPGA - 3U VPX

Options:



- 104 LVDS FPGA I/O














Custom I/OOption -104 provides 24 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/O.Option -105 provides one 8X gigabit linkbetween the FPGA and the VPX P1 con-nector to support serial protocols.


PCI-Express InterfacePCI Express Bus: Gen. 1, 2 or 3: x4





Size: 3U VPX board 3.037 in. x 6.717 in. (100.0 mm x 170.6 mm)

_______________________________________



52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8


20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No

24 pairs on VPX P2


products: the 52xxx and the 53xxx. For moreinformation on a 53xxx product, please referto the product datasheet. The table belowprovides a comparison of their many features.





Pentek, Inc.

Models57141 & 58141

1 or 2-Ch. 6.4 GHz, or 2 or 4-Ch. 3.2 GHz A/D, 2 or 4-Ch.6.4 GHz D/A, 1 or 2 Kintex UltraScale FPGAs - 6U VPX


of the JadeTM family of high-performance 6UVPX boards. The Jade architecture embodiesa new streamlined approach to FPGA-basedboards, simplifying the design to reducepower and cost, while still providing someof the highest-performance FPGA resourcesavailable today. Designed to work withPentek’s new NavigatorTM Design Suite oftools, the combination of Jade and Naviga-tor offers users an efficient path to developingand deploying FPGA-based data acquisitionand processing.

These models consist of one or twoModel 71141 XMC modules mounted on aVPX carrier board. Model 57141 is a 6U boardwith one Model 71141 module while theModel 58141 is a 6U board with two XMCmodules rather than one.

They includet two or four A/Ds, com-plete multiboard clock and sync sections,large DDR4 memories, two or four DDCs,two or four DUCs and two or four D/As.In addition to supporting PCI ExpressGen. 3 as a native interface, these models in-clude optional high-bandwidth connectionsto the Kintex UltraScale FPGAs for customdigital I/O.


Pentek Cobalt and Onyx families, Jade raisesthe processing performance with the newflagship family of Kintex UltraScale FPGAsfrom Xilinx. As the central feature of theboard architecture, the FPGA has access toall data and control paths, enabling factory-installed functions including data multiplexing,

channel selection, data packing, gating,triggering and memory control. The Jadearchitecture organizes the FPGA as a containerfor data-processing applications where eachfunction exists as an intellectual property(IP) module.

Each member of the Jade family isdelivered with factory-installed applicationsideally matched to the board’s analog inter-faces. The factory-installed functions includetwo or four A/D acquisition and two orfour D/A waveform generator IP modules.In addition, IP modules for DDR4 SDRAMmemories, controllers for all data clockingand synchronization functions, one or twotest signal generators and a PCIe interfacecomplete the factory-installed functionsand enable these models to operate ascomplete turnkey solutions, without theneed to develop any FPGA IP.







■ Supports Xilinx KintexUltraScale FPGAs

■ One or two-channel modewith 6.4 GHz, 12-bit A/Ds

■ Two-or four-channel modewith 3.2 GHz, 12-bit A/Ds


■ Two or four-Channel 6.4 GHz,14-bit D/As









NewNewNewNewNew


KU035, KU060 or KU115

CONFIGFLASH1 GB

VPX BACKPLANE

16

LVDS GTH

48 8X

Option -104FPGA

I/O

GTHGTH

4X4X

PCIeGen. 3 x8

PCIeGen. 3 x8

From/ToOther XMCModule ofModel 58841

Option -105Gigabit Serial I/O

DDR4SDRAM

5 GB

80






from the 2nd FPGA to VPX-P5VPX-P1 VPX-P2VPX-P3

PCIe TO PCIeSWITCH

TIMING BUSGENERATOR



A/D Clock/Sync Bus


Gate In A

Gate In B

Sync Bus

Sync

Sys Ref

6.4 GHz14-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

RF In

RFXFORMR



RF In

RFXFORMR

RF Out

RFXFORMR

RF Out

RFXFORMR

D/A Clock/Sync Bus

6.4 GHz14-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALDOWNCONVERT


Model 58141


Pentek, Inc.

Models57141 & 58141



Option -104 provides 24 pairs of LVDSconnections between the FPGA and theVPX P3 connector, Model 57141; P3 andP5 connectors, Model 58141.

Option -105 provides two 4X gigabitlinks between the FPGA and the VPX P2connector to support serial protocols.


inputs on front panel SSMC connectors withtransformer-coupling into a Texas Instru-ments ADC12DJ3200 12-bit A/D. Theconverter operates in single-channel inter-leaved mode with a sampling rate of 6.4GHz and an input bandwidth of 7.9 GHz; or,in dual-channel mode with a sampling rate of3.2 GHz and input bandwidth of 8.1 GHz.

The A/D’s built-in digital downconvert-ers support 2x decimation in real outputmode and 4x, 8x, or 16x decimation in com-plex output mode. The A/D digital outputsare delivered into the Kintex UltraScaleFPGA for signal processing, data capture orfor routing to other module resources.


verter) and D/A accepts a baseband real orcomplex data stream from the FPGA and

A/D Acquisition IP ModuleThese models feature two or

four A/D Acquisition IP Mod-ules for easy capture and datamoving. The IP module can re-ceive data from the A/D, or atest signal generator. The IP mod-ules have associated 5 or 10 GB ofDDR4 memory for buffering datain FIFO mode or for storingdata in transient capture mode.





These models support fac-tory- installed functions whichinclude a sophisticated D/AWaveform Generator IP module.It allows users to easily recordto the D/As waveforms storedin either on-board memory or off-board host memory.

provides that input to the upconvert, inter-polate and dual D/A stages. When operatingas a DUC, it interpolates and translates realor complex baseband input signals. Itdelivers real or quadrature (I+Q) analogoutputs to the dual 14-bit D/A converter.Analog output is through front panel SSMCconnectors.

If translation is disabled, the DAC38RF82acts as a dual interpolating 14-bit D/A. Inboth modes, the DAC38RF82 provides inter-polation factors from 1x to 24x.

Memory ResourcesThe architecture supports 5 or 10 GB bank

of DDR4 SDRAM memory.User-installed IP along with the Pentek-

supplied DDR4 controller core(s) withinthe FPGA can take advantage of the memoryfor custom applications.

PCI Express InterfaceThese models include an industry-stan-

dard interface fully compliant with PCIExpress Gen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the module.

Clocking and SynchronizationThese models accept a sample clock via

front panel SSMC connectors. A second frontpanel SSMC accepts a TTL signal that canfunction as Gate, PPS or Sync.

A front panel µSync bus connector allowsmultiple boards to be synchronized, ideal ➤

fromA/D Ch 1

fromA/D Ch 2

INPUT MULTIPLEXER


toD/A Ch 1

TESTSIGNAL

GENERATOR

MUX

DATAUNPACKING

PCIe INTERFACE


DMAENGINE

SINGLE CH

DATAUNPACKING

DMAENGINEDUAL CH

WAVEFORMGENERATOR

DMAENGINE

OUTPUT MULTIPLEXER

toDDR4

Memory

MEMORYCONTROL

TESTSIGNAL

GENERATOR



METADATAGENERATORto

DDR4SDRAM

MEMORYCONTROL

MUX




METADATAGENERATORto

DDR4SDRAM

MEMORYCONTROL

MUX


toD/A Ch 2

GigabitSerial I/O

PCIeFPGAGPIO


DDR4Memory

8X8X 48


Pentek, Inc.

Models57141 & 58141



57141 1-Ch. 6.4 GHz or 2-Ch.3.2 GHz A/D, 2-Ch.6.4 GHz D/A, KintexUltraScale FPGA - 6UVPX

58141 2-Ch. 6.4 GHz or 4-Ch.3.2 GHz A/D, 4-Ch. 6.4GHz D/A, 2 ea. Ultra-Scale FPGAs - 6U VPX

Options:



- 104 LVDS FPGA I/O




➤ for multichannel systems. The µSyncbus includes gate, reset, and in and outreference clock signals. The Model 5792high-speed sync board can be used to drivethe sync bus to synchronize multichannelsystems.

SpecificationsModel 57141 One A/DModel 58141 Two A/DsFront Panel Analog Signal Inputs (2 or 4)


A/D Converters (1 or 2)Type: ADC12DJ3200Sampling Rate: Single-channel mode:6.4 GHz; dual-channel mode: 3.2 GHzResolution: 12 bitsInput Bandwidth: single-channel mode:7.9 GHz; dual-channel mode: 8.1 GHz

D/A Converters (2 or 4)Type: Texas Instruments DAC38RF82Output Sampling Rate: 6.4 GHz.Resolution: 14 bits

Sample Clock Source (1 or 2)Front panel SSMC connector

Timing Bus (1 or 2)19-pin µSync bus connector includessync and gate/trigger inputs, CML




Field Programmable Gate Arrays (1 or 2)Standard: Xilinx Kintex UltraScaleXCKU035-2Option -084: Xilinx Kintex UltraScaleXCKU060-2Option -087: Xilinx Kintex UltraScaleXCKU115-2

Custom I/OOption -104 provides 24 pairs of LVDSconnections between the FPGA and theVPX P3 connector, Model 57141; P3and P5 connectors, Model 58141.Option -105 provides two 4X gigabitlinks between the FPGA and the VPXP2 connector to support serial protocols.

Memory (1 or 2)Type: DDR4 SDRAMSize: 5 or 10 GBSpeed: 1200 MHz (2400 MHz DDR)






Size: 6U Board 9.187 in x 6.717 in(233.3 mm x 170.6 mm)






Pentek, Inc.

Models 72141,73141 and 74141

1 or 2-Ch. 6.4 GHz, or 2 or 4-Ch. 3.2 GHz A/D, 2 or 4-Ch.6.4 GHz D/A, 1 or 2 Kintex UltraScale FPGAs - cPCI

General InformationModels 72141, 73141and 74141 are mem-

bers of the JadeTM family of high-performancecPCI boards. The Jade architecture embodiesa new streamlined approach to FPGA-basedboards, simplifying the design to reducepower and cost, while still providing someof the highest-performance FPGA resourcesavailable today. Designed to work withPentek’s new NavigatorTM Design Suite oftools, the combination of Jade and Navigatoroffers users an efficient path to developingand deploying FPGA-based data acquisitionand processing.

These models consist of one or two Model71141 XMC modules mounted on a cPCIcarrier board. Model 72141 is a 6U cPCIboard while the Model 73141 is a 3U cPCIboard; both are equipped with one Model71141 XMC. Model 74141 is a 6U cPCI boardwith two XMC modules rather than one.

They includet two or four A/Ds, completemultiboard clock and sync sections, largeDDR4 memories, two or four DDCs, twoor four DUCs and two or four D/As. Thesemodels include optional high-bandwidthconnections to the Kintex UltraScale FPGAsfor custom digital I/O.


Pentek Cobalt and Onyx families, Jade raisesthe processing performance with the newflagship family of Kintex UltraScale FPGAsfrom Xilinx. As the central feature of theboard architecture, the FPGA has access toall data and control paths, enabling factory-installed functions including data multiplexing,

channel selection, data packing, gating,triggering and memory control. The Jadearchitecture organizes the FPGA as a containerfor data-processing applications where eachfunction exists as an intellectual property(IP) module.

Each member of the Jade family is deliveredwith factory-installed applications ideallymatched to the board’s analog interfaces.The factory-installed functions include twoor four A/D acquisition IP modules.

Each of the acquisition IP modules containsa programmable DDC IP core; IP modulesfor DDR4 SDRAM memory; controllers forall data clocking and synchronization functions;test signal generators; and a PCI-X interfacecomplete the factory-installed functions andenable these models to operate as completeturnkey solutions for many applications,thereby saving the cost and time of customIP development.




populated with a range of FPGAs to matchthe specific requirements of the processingtask, spanning the KU035 through KU115. ➤

CONFIGFLASH1 GB

DDR4SDRAM

5 GB

80


MODEL 73141

INTERFACES ONLY

PCIeto PCI

BRIDGE

40

LVDS GTX


J2

PCIeto PCI

BRIDGE

PCIto PCI

BRIDGE

From/To OtherXMC Module ofMODEL 74141

GTH


4X40

LVDS

Option -104FPGAGPIO

Option -104FPGAGPIO

J3




TIMING BUSGENERATOR



A/D Clock/Sync Bus



Gate In A

Gate In B

Sync Bus

Sync

Sys Ref

6.4 GHz14-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

RFXFORMR



RFXFORMR

RFXFORMR

RFXFORMR

D/A Clock/Sync Bus

6.4 GHz14-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALDOWNCONVERT


KU035, KU060 or KU115

RF In RF In RF Out RF Out

New!

New!

New!

New!

New!

Features■ Ideal radar and software radio

interface solution■ Supports Xilinx Kintex Ultra-

Scale FPGAs■ One or two-channel mode

with one or two 6.4 GHz,12-bit A/Ds

■ Two or four-channel modewith two or four 3.2 GHz,12-bit A/Ds

■ Two or four-channel modewith two or four 6.4 GHz,14-bit D/As


■ 5 or 10 GB of DDR4 SDRAM

■ µSync clock/sync bus formultiboard synchronization\

■ Optional LVDS connectionsto the FPGA for custom I/O



Pentek, Inc.

Models 72141,73141 and 74141


➤ The KU115 features 5520 DSP48E2 slicesand is ideal for modulation/demodulation,encoding/decoding, encryption/decryption,and channelization of the signals betweentransmission and reception. For applicationsnot requiring large DSP resources or logic, alower-cost FPGA can be installed.

Option -104 provides 20 pairs of LVDSconnections between the FPGA and the J3(or J2 connector, Model 73141) for customI/O.


inputs on front panel SSMC connectors withtransformer coupling into Texas InstrumentsADC12D1800 12-bit A/Ds. The convert-ers operate in single-channel interleavedmode with a sampling rate of 3.6 GHz and aninput bandwidth of 1.75 GHz; or, in dual-chan-nel mode with a sampling rate of 1.8 GHzand input bandwidth of 2.8 GHz.

The full-scale input level of theADC12D1800 can be digitally trimmedfrom +2 dBm to +4 dBm to simplify systemcalibration. A built-in AutoSync featuresupports A/D synchronization acrossmultiple boards.

The A/D digital outputs are deliveredinto the Kintex UltraScale FPGAs for sig-nal processing, data capture or for routingto other board resources.

Clocking and SynchronizationThese models accept a 1.8 GHz dual-edge


A front panel µSync bus connector allowsmultiple boards to be synchronized, ideal formultichannel systems. The µSync bus includesgate, reset, and in and out reference clocksignals. Two units can be synchronizedwith a simple cable. For larger systems,multiple units can be synchronized usingthe Model 7292 high-speed sync boards todrive the sync bus.

Memory ResourcesThe architecture supports 5 or 10 GB banks

of DDR4 SDRAM memory. User-installed IPalong with the Pentek- supplied DDR4controller core(s) within the FPGA(s) cantake advantage of the memory for customapplications.

PCI-X InterfaceThese models include an industry-

standard interface fully compliant withPCI-X bus specifications. The interfaceincludes multiple DMA controllers for effi-cient transfers to and from the board. Datawidths of 32 or 64 bits and data rates of 33and 66 MHz are supported. Model 73141:32 bits only. ➤

A/D Acquisition IP ModuleThese models feature two or

four A/D Acquisition IP Mod-ules for easy capture and datamoving. The IP module can re-ceive data from the A/D, or atest signal generator. The IP mod-ules have associated 5 or 10 GB ofDDR4 memory for buffering datain FIFO mode or for storingdata in transient capture mode.





These models support factory-installed functions which includea sophisticated D/A WaveformGenerator IP module. It allowsusers to easily record to the D/Aswaveforms stored in either on-board memory or off-board hostmemory.

fromA/D Ch 1

fromA/D Ch 2

INPUT MULTIPLEXER


toD/A Ch 1

TESTSIGNAL

GENERATOR

MUX

DATAUNPACKING

PCIe INTERFACE


DMAENGINE

SINGLE CH

DATAUNPACKING

DMAENGINEDUAL CH

WAVEFORMGENERATOR

DMAENGINE

OUTPUT MULTIPLEXER

toDDR4

Memory

MEMORYCONTROL

TESTSIGNAL

GENERATOR



METADATAGENERATORto

DDR4SDRAM

MEMORYCONTROL

MUX




METADATAGENERATORto

DDR4SDRAM

MEMORYCONTROL

MUX


toD/A Ch 2

PCIeFPGAGPIO


DDR4Memory

4X40


Pentek, Inc.

Models 72141,73141 and 74141


SpecificationsModel 72141 or Model 73141: Two A/DsModel 74141: Four A/DsModel 72141 or Model 73141: Two D/AsModel 74141: Four D/AsFront Panel Analog Signal Inputs (2 or 4)


A/D Converter (2 or 4)Type: ADC12DJ3200Sampling Rate: Single-channel mode:6.4 GHz; dual-channel mode: 3.2 GHzResolution: 12 bitsInput Bandwidth: single-channel mode:7.9 GHz; dual-channel mode: 8.1 GHz

D/A Converters (2 or 4)Type: Texas Instruments DAC38RF82Output Sampling Rate: 6.4 GHz.Resolution: 14 bits

Sample Clock Source (1 or 2)Front panel SSMC connector

Timing Bus (1 or 2)19-pin µSync bus connector includesync and gate/trigger inputs, CML



72141 1 or 2-Ch. 6.4 GHz or2 or 4-Ch. 3.2 GHz A/D,with 2 or 4-Ch. 6.4 GHzD/A and one KintexUltraScale FPGA - 6UcPCI

73141 1 or 2-Ch. 6.4 GHz or2 or 4-Ch. 3.2 GHz A/D,with 2 or 4-Ch. 6.4 GHzD/A and one KintexUltraScale FPGA - 6UcPCI

74141 2-Ch. 6.4 GHz or 4-Ch.3.2 GHz A/D, with 2 or4-Ch. 6.4 GHz D/A andtwo Kintex UltraScaleFPGAs - 6U cPCI

Options:




-702 Air cooled, Level L2

Field Programmable Gate Array (1 or 2)Standard: Xilinx Kintex UltraScaleXCKU035-2Option -084: Xilinx Kintex UltraScaleXCKU060-2Option -087: Xilinx Kintex UltraScaleXCKU115-2


Memory (1 or 2)Type: DDR4 SDRAMSize: GBSpeed: 1200 MHz (2400 MHz DDR)





Size: 6U board 9.187 in x 6.717 in(233.3 mm x 170.6 mm)3U board 3.937 in. x 6.717 in.(100.00 mm x 170.61 mm)


Pentek, Inc.

1-Ch. 6.4 GHz or 2-Ch. 3.2 GHz A/D, 2-Ch. 6.4 GHz D/A,Kintex UltraScale FPGA - AMCModel 56141


family of high-performance AMC boards.The Jade architecture embodies a new stream-lined approach to FPGA-based boards,simplifying the design to reduce power andcost, while still providing some of the high-est-performance FPGA resources availabletoday. Designed to work with Pentek’s newNavigatorTM Design Suite of tools, the com-bination of Jade and Navigator offers usersan efficient path to developing and deployingFPGA-based data acquisition and processing.






















■ AMC 1 compliant■ IPMI 2.0 compliant MMC



NewNewNewNewNew

TIMING BUSGENERATOR



KU035, KU060 or KU115


A/D Clock/Sync Bus



Gate In A

Gate In B

Sync Bus

Sync

Sys Ref

6.4 GHz14-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

RF In

RFXFORMR



RF In

RFXFORMR

RF Out

RFXFORMR

RF Out

RFXFORMR

D/A Clock/Sync Bus

6.4 GHz14-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALDOWNCONVERT

CONFIGFLASH1 GB

DDR4SDRAM

5 GB

80

PCIeGen. 3 x8

GTH LVDS

Option -104FPGAGPIO

488X

FrontPanel

FrontPanelPorts 4 to 11

IPMICONTROLLER

RS-232

AMC

Model 56141


Pentek, Inc.



Option -104 provides 24 pairs of LVDSconnections between the FPGA and a front-panel connector for custom I/O.



The A/D’s built-in digital downconvert-ers support 2x decimation in real outputmode and 4x, 8x, or 16x decimation in com-plex output mode. The A/D digital outputsare delivered into the Kintex UltraScaleFPGA for signal processing, data capture orfor routing to other module resources.


verter) and D/A accepts a baseband real orcomplex data stream from the FPGA andprovides that input to the upconvert, inter-polate and dual D/A stages. When operatingas a DUC, it interpolates and translates realor complex baseband input signals. It







The Model 56141 factory-installed functions include asophisticated D/A WaveformGenerator IP module. It allowsusers to easily record to thedual D/As waveforms storedin either on-board memory oroff-board host memory.

delivers real or quadrature (I+Q) analogoutputs to the dual 14-bit D/A converter.Analog output is through a pair of frontpanel SSMC connectors.

If translation is disabled, the DAC38RF82acts as a dual interpolating 14-bit D/A. Inboth modes, the DAC38RF82 provides inter-polation factors from 1x to 24x.








A front panel µSync bus connector allowsmultiple boards to be synchronized, ideal formultichannel systems. The µSync bus in-cludes gate, reset, and in and out referenceclock signals. The Model 5692 high-speed syncboard can be used to drive the sync bus tosynchronize multichannel systems. ➤

fromA/D Ch 1

fromA/D Ch 2

INPUT MULTIPLEXER


toD/A Ch 1

TESTSIGNAL

GENERATOR

MUX

DATAUNPACKING

PCIe INTERFACE

PCIeFPGAGPIO


DDR4Memory


8X48

DMAENGINE

SINGLE CH

DATAUNPACKING

DMAENGINEDUAL CH

WAVEFORMGENERATOR

DMAENGINE

OUTPUT MULTIPLEXER

toDDR4

Memory

MEMORYCONTROL

TESTSIGNAL

GENERATOR



METADATAGENERATORto

DDR4SDRAM

MEMORYCONTROL

MUX




METADATAGENERATORto

DDR4SDRAM

MEMORYCONTROL

MUX


toD/A Ch 2


Pentek, Inc.



56141 1-Ch. 6.4 GHz or 2-Ch.3.2 GHz A/D, 2-Chan.6.4 GHz D/A, KintexUltraScale FPGA - AMC

Options:



- 104 LVDS FPGA I/O



➤➤➤➤➤ AMC InterfaceThe Model 56141 complies with the

AMC.1 specification by providing an x8 PCIeconnection to Advanced TCA carriers orµTCA chassis. Module management isprovided by an IPMI 2.0 MMC (ModuleManagement Controller).









Custom I/OOption -104 provides 24 pairs of LVDSconnections between the FPGA and afront- panel connector for custom I/O.







Size: Single-width, full-height AMC module2.890 in x 7.110 in(73.40 mm x 180.60 mm)






Pentek, Inc.

3U OpenVPX Virtex-7 Processor and FMC CarrierModel 5973

General InformationThe Flexor® Model 5973 is a high-per-

formance 3U OpenVPX board based on theXilinx Virtex-7 FPGA. As a stand-aloneprocessor board, it provides an ideal devel-opment and deployment platform fordemanding signal-processing applications.

The 5973 includes a VITA-57.1 FMC siteproviding access to a wide range of I/Ooptions. When combined with any ofPentek’s analog interface FMCs, it becomes acomplete multichannel data conversionand processing subsystem suitable forconnection to IF, HF or RF ports of a commu-nications or radar system.

The 5973 architecture includes an optionalbuilt-in gigabit serial optical interface. Up to 12high-speed duplex optical lanes are availableon an MTP connector. With the installationof a serial protocol in the FPGA, this inter-face enables a high-bandwidth connectionbetween 5973s mounted in the same chassis oreven over extended distances between them.

Board ArchitectureBased on the proven design of the Pentek

Onyx family of Virtex-7 products, the 5973retains all the key features of that family.As a central foundation of the board archi-tecture, the FPGA has access to all data andcontrol paths of both the main board andthe FMC, enabling factory-installed functionsThat Include data multiplexing, channelselection, data packing, gating, triggeringand memory control.

The architecture organizes the FPGA as acontainer for data-processing applicationswhere each function exists as an intellectualproperty (IP) module.

When integrated with a Pentek FMC,the 5973 is delivered with factory-installedapplications ideally matched to the board’sanalog or digital interfaces. These caninclude A/D acquisition and D/A waveformplayback engines for simplifying datacapture and playback.

Data tagging and metadata packet genera-tion, in conjunction with powerful linked- listDMA engines, provide a streamlined inter-face for moving data on and off the boardand identifying data packets with chan-nel, timing and sample count information.

IP modules for DDR3 SDRAM memories,controllers for all data clocking and synchro-nization functions, a test signal generator,and a PCIe interface complete the factory-installed functions and enable the 5973 andits installed FMC to operate as a completeturnkey solution without the need to developany FPGA IP.


functions, users can install their own customIP for data processing. Pentek GateFlowFPGA Design Kits include all of the factory-installed modules as documented sourcecode. Developers can integrate their ownIP with the Pentek factory-installed func-tions or use the GateFlow kit to completelyreplace the Pentek IP with their own. ➤

Features■ VITA-57.1 FMC site offers

access to a wide range ofpossible I/O

■ Supports Xilinx Virtex-7 VXTFPGAs



■ PCI Express (Gen. 1, 2 and 3)interface up to x8

■ User-configurable gigabitserial interface

■ Optional optical Interfacefor backplane gigabit serialinterboard communication


■ Compatible with several VITAstandards including:VITA-46, VITA-48, VITA-66.4and VITA-65 (OpenVPXTM



FMCCONNECTOR

10X160

FPGA GigabitSerial I/O

GTX LVDSGTX

FPGALVDSGPIO

PCIeGen. 3 x8

4X

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

16pairs

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

VPX BACKPLANE

VPX-P1 VPX-P2 (½)

LVDS GTX

VPX-P0

OPTICALTRANSCEIVER

(Optional)

FPGAGigabitSerial I/O

GTX

12X

VPX-P2 (½)VITA 66.4

New!

New!

New!

New!

New!


Pentek, Inc.

3U OpenVPX Virtex-7 Processor and FMC CarrierModel 5973

Xilinx Virtex-7 FPGAThe 5973 can be optionally populated

with one of two Virtex-7 FPGAs to matchthe specific requirements of the process-ing task. Supported FPGAs are VX330T orVX690T. The VX690T features 3600 DSP48E1slices and is ideal for modulation/demodu-lation, encoding/decoding, encryption/decryption, and channelization of the signalsbetween transmission and reception. Forapplications not requiring large DSP resourcesor logic, the lower-cost VX330T can be installed.

Sixteen pairs of LVDS connections areoptionally provided between the FPGAand the VPX P2 connector for custom I/O.For applications requiring custom gigabitlinks, a 4X connection is supported betweenthe FPGA and the VPX P1 connector to sup-port serial protocols.

The 5973 supports the emerging VITA-66.4 standard, that provides 12 opticalduplex lanes to the backplane. With theinstallation of a serial protocol, the VITA-66.4 interface enables gigabit backplanecommunications between boards indepen-dent of the PCIe interface.

GateXpress for FPGA ConfigurationThe 5973 architecture includes GateXpress,

a sophisticated FPGA-PCIe configurationmanager for loading and reloading the FPGA.At power up, GateXpress immediately pre-sents a PCIe target for the host computer todiscover, effectively giving the FPGA timeto load from FLASH. This is especially impor-tant for larger FPGAs where the loadingtimes can exceed the PCIe discovery window,typically 100 msec on most SBCs.

The board’s configuration FLASH canhold four FPGA images. Images can be fac-tory-installed IP or custom IP created by theuser, and programmed into the FLASH viaJTAG using Xilinx iMPACT or through theboard’s PCIe interface. At power up the usercan choose which image will load based ona hardware switch setting.





SpecificationsI/O Module Interface: VITA-57.1, High Pin

Count FMC siteField Programmable Gate Array

Standard: Xilinx Virtex-7 XC7VX330T-2Optional: Xilinx Virtex-7 XC7VX690T-2

Custom FPGA I/O4X gigabit links between the FPGAand the VPX P1 connector to supportserial protocols.Parallel (Option -104): 16 pairs ofLVDS connections between the FPGAand the VPX P2 connector for custom I/OOptical (Option -110): VITA-66.4, 12Xduplex lanes



Environmental: Level L1 & L2 air-cooled,Level L3 conduction-cooled, ruggedized

Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)


5973 3U OpenVPX Virtex-7Processor and FMCCarrier

Options:



-110 VITA-66.4 12X opticalinterface


versions

Model Description




FMC Product CombinationsIf you wish to purchase this

FMC Carrier in combination withan A/D FMC module, please see:

●●●●● FlexorSet Model 5973-312

● ● ● ● ● FlexorSet Model 5973-316●●●●● FlexorSet Model 5973-320



Pentek, Inc.

PCI Express Virtex-7 Processor and FMC Carrier - x8 PCIeModel 7070

General InformationThe Flexor® Model 7070 is a high-perfor-

mance PCIe board based on the XilinxVirtex-7 FPGA. As a stand-alone processorboard, it provides an ideal developmentand deployment platform for demandingsignal processing applications.

The 7070 includes a VITA-57.1 FMC siteproviding access to a wide range of I/Ooptions. When combined with any ofPentek’s analog interface FMCs, it becomesa complete multichannel data conversionand processing subsystem suitable forconnection to IF, HF or RF ports of a commu-nications or radar system.

The 7070 architecture includes an optionalbuilt-in gigabit serial optical interface. Up to 12high-speed duplex optical lanes are availableon an MTP connector. With the installationof a serial protocol in the FPGA, this inter-face enables a high-bandwidth connectionbetween 7070s mounted in the same chassis oreven over extended distances between them.

Board ArchitectureBased on the proven design of the Pentek

Onyx family of Virtex-7 products, the 7070retains all of the key features of that family.As a central foundation of the board archi-tecture, the FPGA has access to all data andcontrol paths of both the main board andthe FMC module, enabling factory-installedfunctions including data multiplexing, channelselection, data packing, gating, triggeringand memory control.

The architecture organizes the FPGA asa container for data processing applicationswhere each function exists as an intellectualproperty (IP) module.

When integrated with a Pentek FMC,the 7070 is delivered with factory-installedapplications ideally matched to the board’sanalog or digital interfaces. These caninclude A/D acquisition and D/A waveformplayback engines for simplifying datacapture and playback.

Data tagging and metadata packet gen-eration, in conjunction with powerfullinked-list DMA engines, provide a stream-lined interface for moving data on and off theboard and identifying data packets withchannel, timing and sample -count information.

IP modules for DDR3 SDRAM memories,controllers for all data clocking and synchro-nization functions, a test signal generator,and a PCIe interface complete the factory-installed functions and enable the 7070 andinstalled FMC to operate as a completeturnkey solution without the need todevelop any FPGA IP.


functions, users can install their own customIP for data processing. Pentek GateFlowFPGA Design Kits include all of the factory-installed modules as documented sourcecode. Developers can integrate their own IPwith the Pentek factory-installed functionsor use the GateFlow kit to completely replacethe Pentek IP with their own. ➤

Features■ VITA-57.1 FMC site offers

access to a wide range ofpossible I/O

■ Supports Xilinx Virtex-7 VXTFPGAs


■ 4 GB of DDR3 SDRAM■ PCI Express (Gen. 1, 2 and

3) interface up to x8■ Optional user-configurable

12X optical gigabit serialinterface


■ Commercial and extended-temperature versionsavailable

FMCCONNECTOR

10X160

LVDSGTX

FPGALVDSGPIO

PCIeGen. 3 x8

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

16pairs

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

Card Edge ConnectorPCIe Gen 3 x8

LVDS GTX

OPTICALTRANSCEIVER

(optional)


GTX

12X

To Second SlotFront Panel

MTP Connector

Model 7070 shownwith Model 3312multichannel A/D& D/A FMC module

New!

New!

New!

New!

New!


Pentek, Inc.

PCI Express Virtex-7 Processor and FMC Carrier - x8 PCIeModel 7070

Xilinx Virtex-7 FPGAThe 7070 can be optionally populated

with one of two Virtex-7 FPGAs to matchthe specific requirements of the processingtask. Supported FPGAs are VX330T orVX690T. The VX690T features 3600 DSP48E1slices and is ideal for modulation/demodu-lation, encoding/decoding, encryption/decryption, and channelization of the signalsbetween transmission and reception. Forapplications not requiring large DSP resourcesor logic, the lower-cost VX330T can be installed.

Sixteen pairs of LVDS connections areoptionally provided between the FPGAand a card edge connector for custom I/O.For applications requiring custom gigabitlinks, up to 12 high-speed, full-duplex FPGAGTX lanes driven via an optical transceiversupport serial protocols. A 12-lane MTPoptical connector is presented on a PCIeslot panel that can be installed in an empty,adjacent PCIe slot.

When configured with a VX330T FPGA,four duplex lanes are available.

GateXpress for FPGA ConfigurationThe 7070 architecture includes GateXpress,

a sophisticated FPGA-PCIe configurationmanager for loading and reloading the FPGA.At power up, GateXpress immediately pre-sents a PCIe target for the host computer todiscover, effectively giving the FPGA timeto load from FLASH. This is especially impor-tant for larger FPGAs where the loadingtimes can exceed the PCIe discovery window,typically 100 msec on most SBCs.

The board’s configuration FLASH canhold four FPGA images. Images can be fac-tory-installed IP or custom IP created by theuser, and programmed into the FLASH viaJTAG using Xilinx iMPACT or through theboard’s PCIe interface. At power up theuser can choose which image will load basedon a hardware switch setting.





SpecificationsI/O Module Interface: VITA-57.1, High Pin

Count FMC siteField Programmable Gate Array

Standard: Xilinx Virtex-7 XC7VX330T-2Optional: Xilinx Virtex-7 XC7VX690T-2

Custom FPGA I/OParallel, Option -104: 16 pairs of LVDSconnections between the FPGA and acard-edge connector.Optical (Option -110): User-configurable12X (VX690T) or 4X (VX 330T) opticalgigabit serial interface, MTP connectorinstalled in an empty adjacent slot



Environmental: Level L1 & L2 air cooled,Size: Half-length PCIe card


7070 PCI Express Virtex-7Processor and FMCCarrier - x8 PCIe

Options:


-104 16 pairs LVDS FPGA I/O

-110 12x gigabit serial opticalI/O

Contact Pentek for availabilityof extended-temperature versions

Model Description




FMC Product CombinationsIf you wish to purchase this

FMC Carrier in combination withan A/D FMC module, please see:


● ● ● ● ● FlexorSet Model 7070-316●●●●● FlexorSet Model 7070-320



Pentek, Inc.

4-Ch. 250 MHz, 16-bit A/D, 2-Ch. 800 MHz, 16-bit D/A - FMCModel 3312

General InformationThe Flexor® Model 3312 is a multichannel,

high-speed data converter FMC module. Itis suitable for connection to HF or IF ports ofa communications or radar system. It includesfour 250 MHz, 16-bit A/Ds, two 800 MHz,16-bit D/As, programmable clocking, andmultiboard synchronization for support oflarger high-channelcount systems.

The 3312 is sold as a complete turnkeydata acquisition and signal generationsolution as the FlexorSetTM 5973-312 3U VPXor the FlexorSet 7070-312 PCIe board. Forapplications that require custom processing,the FlexorSets are ideal for IP developmentand deployment.

A/D ConvertersThe front end accepts four analog HF

or IF inputs on front-panel connectors withtransformer-coupling into two Texas Instru-ments ADS42LB69 Dual 250 MHz, 16-bitA/D converters.

Performance of the Model 3312The true performance of the 3312 can be

unlocked only when used with the PentekModel 5973 or Model 7070 FMC carriers.With factory-installed IP, the board-set pro-vides a turnkey data acquisition subsystemeliminating the need to create any FPGA IP.Installed features include flexible A/D acqui-sition, programmable linked-list DMAengines, and a D/A waveform playback IPmodule.

A/D Acquisition IP ModulesWith the 3312 installed on either the

5973 or the 7070 carrier, the board-set featuresfour A/D acquisition IP modules for easilycapturing and moving data. Each module

can receive data from any of the four A/Ds, atest signal generator or from the D/A wave-form playback IP module in loopback mode.

Each IP module can have an associatedmemory bank on the FMC carrier for buffer-ing data in FIFO mode or for storing data intransient capture mode. All memory banksare supported with DMA engines for eas-ily moving A/D data through the FMCcarrier’s PCIe interface.

These powerful linked-list DMA enginesare capable of a unique acquisition gate-driven mode. In this mode, the length ofa transfer performed by a link definitionneed not be known prior to data acquisition;rather, it is governed by the length of theacquisition gate. This is extremely usefulin applications where an external gate drivesacquisition and the exact length of that gateis not known or is likely to vary.

For each transfer, the DMA engine canautomatically construct metadata packetscontaining A/D channel ID, a sample-accu-rate time stamp and data length information.These actions simplify the host processor’stask of identifying and executing on the data.

D/A Waveform Playback IP ModuleWith the 5973 or the 7070, the 3312

features a sophisticated D/A waveform play-back IP module. A linked-list controllerallows users to easily play back to the D/Aswaveforms stored in either on-board or off-board host memory.

Parameters including length of waveform,delay from playback trigger, waveform rep-etition, etc. can be programmed for eachwaveform. Up to 64 individual link entriescan be chained together to create complexwaveforms with minimum programming. ➤

Features■ Sold as the:


● ● ● ● ● FlexorSet Model 7070-312■ Four 250 MHz 16-bit A/Ds■ One digital upconverter

■ Two 800 MHz 16-bit D/As■ Sample clock synchronization

to an external system reference■ VITA 57 FMC compatible■ Complete radar or software

radio interface solution whencombined with the Model 59733U OpenVPX or Model 7070PCIe Virtex-7 FMC carriers


TIMING BUSGENERATOR


VCXO

250 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

250 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

RF In

RFXFORMR

250 MHz16-BIT A/D

16

RF In

RFXFORMR

250 MHz16-BIT A/D

16


FMCCONNECTOR

Control& Status

RFXFORMR

800 MHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

D/A Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

New!

New!

New!

New!

New!


Pentek, Inc.

4-Ch. 250 MHz, 16-bit A/D, 2-Ch. 800 MHz, 16-bit D/A - FMCModel 3312

Digital Upconverter and D/A StageA TI DAC5688 DUC (digital upconverter)

and D/A accepts a baseband real or complexdata stream from the FPGA and providesthat input to the upconvert, interpolate andD/A stages.

When operating as a DUC, it interpolatesand translates real or complex basebandinput signals to any IF center frequency upto 360 MHz. It delivers the output to the16-bit D/A converter. Analog outputs arethrough front panel connectors.

If translation is disabled, the DAC5688acts as a dual interpolating 16-bit D/A withoutput sampling rates up to 800 MHz. Inboth modes the DAC5688 provides interpo-lation factors of 2x, 4x and 8x.

Clocking and SynchronizationTwo internal timing buses provide all

timing and synchronization required bythe A/D and D/A converters. Each includesa clock, sync and gate or trigger signals. Anon-board clock generator receives an exter-nal sample clock from the front panelcoaxial connector. This clock can be useddirectly by the A/D or D/A sections ordivided by a built-in clock synthesizercircuit to provide different A/D and D/Aclocks. In an alternate mode, the sampleclock can be sourced from an on-boardprogrammable VCXO (Voltage-ControlledCrystal Oscillator). In this mode, the frontcoaxial panel connector can be used toprovide a 10 MHz reference clock for synchro-nizing the internal oscillator.

A front panel LVTTL Gate/Trigger/Syncconnector can receive an external timingsignal allowing multiple modules to besynchronized thereby creating larger multi-board systems.

ReadyFlow Board Support PackageWhen used with the 5973 or the 7070,

Pentek’s ReadyFlow® BSP provides controlof all the 3312’s hardware and IP-basedfunctions. Ready to run examples and afully-sourced C library provide a quick-start and powerful platform to create customapplications. ReadyFlow is compatible withWindows and Linux operating systems.


functions, users can install their own customIP for data processing. Pentek’s GateFlow®

FPGA Design Kits include all of the factory-installed Virtex-7-based 5973/3312 or7070/3312 IP modules as documentedsource code. Using Xilinx Vivado tools,developers can integrate their own IP with


3312 4-Channel 250 MHz,16-bit A/D, 2-Channel800 MHz, 16-bit D/A -FMC


versions

Model Description



the Pentek factory-installed functions or usethe GateFlow kit to completely replace thePentek 5973/7070 IP with their own.

FMC InterfaceThe Model 3312 complies with the VITA

57 High Pin Count FMC specification. Theinterface provides all data, clocking, synchro-nization, control and status signals betweenthe 3312 and the FMC carrier.

Model 3312 SpecificationsFront Panel Analog Signal Inputs

Input Type: Transformer-coupled, frontpanel connectorsTransformer Type: Coil Craft WBC4-6TLBFull Scale Input: +4 dBm into 50 ohms3 dB Passband: 300 kHz to 700 MHz

A/D ConvertersType: Texas Instruments ADS42LB69Sampling Rate: 10 MHz to 250 MHzResolution: 16 bits

D/A ConvertersType: Texas Instruments DAC5688Input Data Rate: 250 MHz max.Output IF: DC to 400 MHz max.Output Sampling Rate: 800 MHz max.with interpolationResolution: 16 bits

Front Panel Analog Signal OutputsOutput Type: Transformer-coupled,front panel connectorTransformer Type: Coil Craft WBC4-6TLBFull Scale Output: +4 dBm into 50 ohms3 dB Passband: 300 kHz to 700 MHz

Sample Clock Sources: On-board clocksynthesizer generates two clocks: anA/D clock and a D/A clock

Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO (10 to 810 MHz)or front panel external clockSynchronization: VCXO can be phase-locked to an external 4 to 180 MHz PLLsystem reference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16 for theA/D or D/A clocks

External ClockType: Front panel connector, sine wave,0 to +10 dBm, AC-coupled, 50 ohms, ac-cepts 10 to 800 MHz divider input clockor PLL system reference

External Trigger InputType: Front panel connector, LVTTLFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Environmental: Level L1 & L2 air cooled,Level L3 conduction-cooled, ruggedized

I/O Module Interface: VITA-57.1, High-PinCount FMC




integrated PC developmentsystem for Pentek Cobalt, Onyxand Flexor PCI Express boards.It was created to save engineersand system integrators the timeand expense associated withbuilding and testing a develop-ment system that ensuresoptimum performance ofPentek boards.


Pentek, Inc.

4-Ch. 250 MHz 16-bit A/D, 2-Ch. 800 MHz 16-bit D/A - 3U VPXFlexorSetModel 5973-312

10X160


GTX LVDSGTX

FPGALVDSGPIO

PCIeGen. 3 x8

4X

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

16pairs

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

VPX BACKPLANE

VPX-P1 VPX-P2 (½)

LVDS GTX

VPX-P0

OPTICALTRANSCEIVER

(Optional)


GTX

12X


FMC CONNECTOR

FMC CONNECTOR

Model 3312 FMC

Model 5973 FMC Carrier

TIMING BUSGENERATOR


VCXO

250 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

250 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

RF In

RFXFORMR

250 MHz16-BIT A/D

16

RF In

RFXFORMR

250 MHz16-BIT A/D

16


Control& Status

RFXFORMR

800 MHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

D/A Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

General InformationModel 5973-312 is a member of the Flexor®

family of high-performance 3U VPX boardsbased on the Xilinx Virtex-7 FPGA.

As a FlexorSetTM integrated solution, theModel 3312 FMC is factory-installed on the5973 FMC carrier. The required FPGA IP isinstalled and the board set is delivered readyfor immediate use.

The delivered FlexorSet is a multichannel,high-speed data converter and is suitable forconnection to the HF or IF ports of a com-munications or radar system. Its built-in datacapture features offer an ideal turnkey solutionas well as a platform for developing anddeploying custom FPGA processing IP.

It includes four 250 MHz, 16-bit A/Ds,one digital upconverter, two 800 MHz, 16-bitD/As, and four banks of memory. In addi-tion to supporting PCIe Gen. 3 as a nativeinterface, the Model 5973-312 includesoptional copper and optical connections tothe Virtex-7 FPGA for custom I/O.

The Flexor ArchitectureBased on the proven design of the Pentek

Onyx family of Virtex-7 products, the 5973FMC carrier retains all the key features ofthat family. As a central foundation of theboard architecture, the FPGA has access toall data and control paths of both the carrierboard and the FMC module, enabling factory-installed functions that include datamultiplexing, channel selection, data pack-ing, gating, triggering and memory control.

When delivered as an assembled boardset, the 5973-312 includes factory-installed

applications ideally matched to the board’sanalog interfaces. The functions include fourA/D acquisition IP modules for simplifyingdata capture and data transfer.

Each of the four acquisition IP modulescontains IP modules for DDR3 SDRAMmemories.

The 5973-312 features a sophisticatedD/A waveform playback IP module. Alinked-list controller allows users to easilyplay back to the D/As waveforms stored ineither on-board or off-board host memory.Parameters including length of waveform,delay from playback trigger, waveform rep-etition, etc. can be programmed for eachwaveform.

Up to 64 individual link entries can bechained together to create complex wave-forms with a minimum of programming.

A controller for all data clocking andsynchronization functions, a test signalgenerator, and a PCIe interface complete thefactory-installed functions and enable the5973-312 to operate as a turnkey solutionwithout the need to develop any FPGA IP.



FPGA Design Kits include all of the factory-installed modules as documented sourcecode. Developers can integrate their ownIP with the Pentek factory-installed functionsor use the GateFlow kit to completelyreplace the Pentek IP with their own. ➤

New!

New!

New!

New!

New!

Features■ Supports Xilinx Virtex-7 VXT

FPGAs


■ Four 250 MHz 16-bit A/Ds

■ One digital upconverter■ Two 800 MHz 16-bit D/As■ 4 GB of DDR3 SDRAM


■ PCI Express (Gen. 1, 2 & 3)interface up to x8







Model 5973-312


Pentek, Inc.


the FPGA time to load from FLASH. This isespecially important for larger FPGAs wherethe loading times can exceed the PCIe dis-covery window, typically 100 msec on manysystems.

The board’s configuration FLASH canhold four FPGA images. Images can befactory-installed IP or custom IP createdby the user, and programmed into theFLASH via JTAG using Xilinx iMPACT orthrough the board’s PCIe interface. Atpower-up the user can choose which imagewill load based on a hardware switch setting.

Once booted, GateXpress allows the userthree options for dynamically reconfiguringthe FPGA with a new IP image. The firstoption to load is an alternate image fromFLASH through software control. The userselects the desired image and issues areload command.

The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. This isimportant in security situations where therecan be no latent user image left in non-volatile memory when power is removed.In applications where the FPGA IP mayneed to change many times during the courseof a mission, images can be stored on thehost computer and loaded through PCIe asneeded.

The third option, typically used duringdevelopment, allows the user to directly loadthe FPGA through JTAG using XilinxiMPACT. ➤

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

toD/A


FPGAGPIO

D/A loopback

DETAILS OF VIRTEX-7 FPGA IP

INSTALLED IN MODEL 5973-312



A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 4


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 1

MEMORYCONTROL

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 4

MEMORYCONTROL

8X 4X 32

A/D

ACQUISITION

IP MODULES

2 & 3

MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

toA/D AcqModule 1

toA/D AcqModule 2

toA/D AcqModule 3

toA/D AcqMod 4 &D/A Mod

➤➤➤➤➤ Xilinx Virtex-7 FPGAThe 5973-312 can be optionally popu-

lated with one of two Virtex-7 FPGAs tomatch the specific requirements of theprocessing task. Supported FPGAs areVX330T or VX690T. The VX690T features3600 DSP48E1 slices and is ideal for modula-tion/demodulation, encoding/decoding,encryption/decryption, and channelizationof the signals between transmission andreception. For applications not requiringlarge DSP resources or logic, the lower-costVX330T can be installed.

A 4X connection between the FPGA andthe VPX P1 connector supports gigabitserial protocols.


Option -110 supports the VITA-66.4standard that provides 12 optical duplexlanes to the backplane. With the installationof a serial protocol, the VITA-66.4 interfaceenables gigabit backplane communicationsbetween boards independent of the PCIeinterface.

GateXpress for FPGA ConfigurationThe Flexor architecture includes

GateXpress®, a sophisticated FPGA-PCIeconfiguration manager for loading andreloading the FPGA. At power-up, GateXpressimmediately presents a PCIe target for thehost computer to discover, effectively giving

A/D Acquisition IP ModulesThe 5973-312 features four

A/D Acquisition IP Modulesfor easy capture and data mov-ing. Each IP module can receivedata from any of the four A/Ds,a test signal generator or fromthe D/A Waveform Playback IPModule in loopback mode.

Each IP module has anassociated memory bank forbuffering data in FIFO mode orfor storing data in transient cap-ture mode. All memory banksare supported with DMA enginesfor moving A/D data throughthe PCIe interface.

These powerful linked-listDMA engines are capable of aunique Acquisition Gate Drivenmode. In this mode, the length ofa transfer performed by a linkdefinition need not be knownprior to data acquisition; rather,it is governed by the length ofthe acquisition gate. This isextremely useful in applicationswhere an external gate drivesacquisition and the exact lengthof that gate is not known or islikely to vary.

For each transfer, the DMAengine can can automaticallyconstruct metadata packets con-taining A/D channel ID, a sampleaccurate time stamp, and datalength information. These actionssimplify the host processor’s jobof identifying and executing onthe data.


The 5973-312 factory-installedfunctions include a sophisti-cated D/A Waveform PlaybackIP module. A linked-list control-ler allows users to easily playback waveforms stored in eitheron-board or off-board hostmemory to the dual D/As.

Parameters including length ofwaveform, delay from playbacktrigger, waveform repetition,etc. can be programmed for eachwaveform. Up to 64 individuallink entries can be chained togetherto create complex waveformswith a minimum of program-ming.


Pentek, Inc.


3 dB Passband: 300 kHz to 700 MHzA/D Converters

Type: Texas Instruments ADS42LB69Sampling Rate: 10 MHz to 250 MHzResolution: 16 bits




Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO (10 to 810 MHz),front panel external clock or LVPECLtiming busSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLL systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8 or 16 for theA/D clock

External ClockType: Front panel female SSMC connector,sine wave, 0 to +10 dBm, AC-coupled,50 ohms, accepts 10 to 800 MHz dividerinput clock or PLL system reference

External Trigger InputType: Front panel connectorFunction: Programmable functionsinclude: trigger, gate, sync and PPS

Field Programmable Gate ArrayStandard: Xilinx Virtex-7 XC7VX330T-2Option -076: Xilinx Virtex-7 XC7VX690T-2





Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

➤ In all three FPGA loading scenarios,GateXpress handles the hardware negotia-tion simplifying and streamlining theloading task. In addition, GateXpress pre-serves the PCIe configuration space allowingdynamic FPGA reconfiguration withoutneeding to reset the host computer to redis-cover the board. After the reload, the hostsimply continues to see the board with theexpected device ID.

A/D Converter StageThe front end accepts four analog HF

or IF inputs on front-panel connectors withtransformer-coupling into two Texas Instru-ments ADS42LB69 dual 250 MHz, 16-bitA/D converters.

Digital Upconverter and D/A StageA TI DAC5688 DUC and D/A accepts a

baseband real or complex data stream fromthe FPGA and provides that input to theupconvert, interpolate and D/A stages.




timing and synchronization required bythe A/D and D/A converters. Each includesa clock, sync and gate or trigger signals. Anon-board clock generator receives an exter-nal sample clock from the front panelcoaxial connector. This clock can be useddirectly by the A/D or D/A sections ordivided by a built-in clock synthesizercircuit to provide different A/D and D/Aclocks. In an alternate mode, the sampleclock can be sourced from an on-boardprogrammable VCXO. In this mode, thefront coaxial panel connector can be usedto provide a 10 MHz reference clock for syn-chronizing the internal oscillator.

A front panel LVTTL Gate/Trigger/Syncconnector can receive an external timingsignal to synchronize multiple modules.


Input Type: Transformer-coupled, frontpanel connectorsTransformer Type: Coil Craft WBC4-6TLBFull Scale Input: +4 dBm into 50 ohms

PCI Express InterfaceThe Model 5973-312 includes

an industry-standard interfacefully compliant with PCI ExpressGen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8,the interface includes multipleDMA controllers for efficienttransfers to and from the board.

Memory ResourcesThe 5973-312 architecture sup-

ports four independent DDR3SDRAM memory banks. Eachbank is 1 GB deep and is anintegral part of the board’sDMA capabilities, providingFIFO memory space for creat-ing DMA packets.




5973-312 4-Channel 250 MHz A/D,2-Channel 800 MHz16-bit D/A with Virtex-7FPGA - 3U VPX

Options:





versions

Model Description



Pentek, Inc.

4-Ch. 250 MHz 16-bit A/D, 2-Ch. 800 MHz 16-bit D/A - x8 PCIeFlexorSetModel 7070-312

10X160

FMC CONNECTOR

FMC CONNECTOR

Model 3312 FMC


TIMING BUSGENERATOR


VCXO

250 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

250 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

RF In

RFXFORMR

250 MHz16-BIT A/D

16

RF In

RFXFORMR

250 MHz16-BIT A/D

16


Control& Status

RFXFORMR

800 MHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

D/A Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

LVDSGTX

FPGALVDSGPIO

PCIeGen. 3 x8

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

16pairs

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

PCIe Gen. 3 x8 Card Edge Connector

LVDS GTX

MTP Connector

OPTICALTRANSCEIVER

(Optional)


GTX

12X


family of high-performance PCIe boardsbased on the Xilinx Virtex-7 FPGA.

As a FlexorSetTM integrated solution, the Model 3312 FMC is factory-installed on the 7070 FMC carrier. The required FPGA IP is installed and the board set is delivered ready for immediate use.

The delivered FlexorSet is a multichannel,high-speed data converter and is suitable forconnection to the HF or IF ports of a com-munications or radar system. Its built-in datacapture features offer an ideal turnkey solutionas well as a platform for developing anddeploying custom FPGA processing IP.

It includes four 250 MHz, 16-bit A/Ds,one digital upconverter, two 800 MHz, 16-bitD/As, and four banks of memory. In addi-tion to supporting PCIe Gen. 3 as a nativeinterface, the Model 7070-312 includesoptional copper and optical connections tothe Virtex-7 FPGA for custom I/O.



When delivered as an assembled boardset, the 7070-312 includes factory-installed

applications ideally matched to the board’sanalog interfaces. The functions include fourA/D acquisition IP modules for simplifyingdata capture and data transfer.


The 7070-312 features a sophisticatedD/A waveform playback IP module. Alinked-list controller allows users to easilyplay back to the D/As waveforms stored ineither on-board or off-board host memory.Parameters including length of waveform,delay from playback trigger, waveform rep-etition, etc. can be programmed for eachwaveform.

Up to 64 individual link entries can bechained together to create complex wave-forms with a minimum of programming.




FPGA Design Kits include all of the factory-installed modules as documented sourcecode. Developers can integrate their ownIP with the Pentek factory-installed functionsor use the GateFlow kit to completelyreplace the Pentek IP with their own. ➤

New!

New!

New!

New!

New!


FPGAs



■ One digital upconverter■ Two 800 MHz 16-bit D/As■ 4 GB of DDR3 SDRAM



■ Optional optical Interfacefor gigabit serial interboardcommunication


Model 7070-312


Pentek, Inc.





The third option, typically used duringdevelopment, allows the user to directly loadthe FPGA through JTAG using XilinxiMPACT.

In all three FPGA loading scenarios,GateXpress handles the hardware negotia-tion simplifying and streamlining the ➤

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

toD/A

PCIeFPGAGPIO

D/A loopback





A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 4


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 1

MEMORYCONTROL

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 4

MEMORYCONTROL

8X 32

A/D

ACQUISITION

IP MODULES

2 & 3

MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

toA/D AcqModule 1

toA/D AcqModule 2

toA/D AcqModule 3

toA/D AcqMod 4 &D/A Mod

➤➤➤➤➤ Xilinx Virtex-7 FPGAThe 7070-312 can be optionally popu-


Option -104 provides 16 pairs of LVDSconnections between the FPGA and a card-edge connector for custom I/O.

Option -110: For applications requiringoptical gigabit links, up to 12 high-speed,full-duplex FPGA GTX lanes driven via anoptical transceiver support serial protocols.A 12-lane MTPoptical connector is presentedon the PCIe slot panel.


GateXpress®, a sophisticated FPGA-PCIeconfiguration manager for loading andreloading the FPGA. At power-up, GateXpressimmediately presents a PCIe target for thehost computer to discover, effectively givingthe FPGA time to load from FLASH. This isespecially important for larger FPGAs wherethe loading times can exceed the PCIediscovery window, typically 100 msec onmany systems.


A/D Acquisition IP Modulesfor easy capture and data mov-ing. Each IP module can receivedata from any of the four A/Ds,a test signal generator or fromthe D/A Waveform Playback IPModule in loopback mode.





The 7070-312 factory-installedfunctions include a sophisti-cated D/A Waveform PlaybackIP module. A linked-list control-ler allows users to easily playback waveforms stored in eitheron-board or off-board hostmemory to the dual D/As.

Parameters including length ofwaveform, delay from playbacktrigger, waveform repetition,etc. can be programmed for eachwaveform. Up to 64 individuallink entries can be chained togetherto create complex waveformswith a minimum of program-ming.


Pentek, Inc.










Custom FPGA I/OParallel (Option -104): 16 pairs of LVDSconnections between the FPGA and acard-edge connector for custom I/OOptical (Option -110): 12x gigabit serialoptical I/O with XC7VX690T FPGA, 4xwith XC7VX330T



Environmental: Level L1 & L2 air-cooled,Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

➤ loading task. In addition, GateXpresspreserves the PCIe configuration space allow-ing dynamic FPGA reconfiguration withoutneeding to reset the host computer to redis-cover the board. After the reload, the hostsimply continues to see the board with theexpected device ID.


or IF inputs on front-panel connectors withtransformer-coupling into two Texas Instru-ments ADS42LB69 dual 250 MHz, 16-bitA/D converters.

Digital Upconverter and D/A StageA TI DAC5688 DUC and D/A accepts a

baseband real or complex data stream fromthe FPGA and provides that input to theupconvert, interpolate and D/A stages.















7070-312 4-Channel 250 MHz A/D,2-Channel 800 MHz 16-bit D/A with Virtex-7FPGA - x8 PCIe

Options:


-104 LVDS FPGA I/O to card-edge connector

-110 12x gigabit serial optical

I/O with XC7VX690TFPGA, 4x w. XC7VX330T

Model Description



Pentek, Inc.

8-Channel 250 MHz, 16-bit A/D - FMCModel 3316

General InformationThe Flexor® Model 3316 is a multichannel,

high-speed data converter FMC module. It issuitable for connection to HF or IF ports of acommunications or radar system. It includeseight 250 MHz, 16-bit A/Ds, programmableclocking, and multiboard synchronizationfor support of larger high-channelcountsystems.

The 3316 is sold as a complete turnkeydata acquisition solution as the FlexorSetTM

5973-316 3U VPX or the FlexorSet 7070-316PCIe board. For applications that requirecustom processing, the FlexorSets are idealfor IP development and deployment.

A/D ConvertersThe front end accepts eight analog HF

or IF inputs on front-panel connectors withtransformer-coupling into four Texas Instru-ments ADS42LB69 Dual 250 MHz, 16-bitA/D converters.


unlocked only when used with the PentekModel 5973 or Model 7070 FMC carriers.With factory-installed IP, the board-set pro-vides a turnkey data acquisition subsystemeliminating the need to create any FPGA IP.Installed features include flexible A/D acqui-sition, programmable linked-list DMAengines, and a metadata packet creator.


5973 or the 7070 FMC carrier, the board-setfeatures eight A/D Acquisition IP modulesfor easily capturing and moving data. Eachmodule can receive data from any of theeight A/Ds, or a test signal generator.

Each IP module can have an associatedmemory bank on the Pentek FMC carrier forbuffering data in FIFO mode or for storingdata in transient capture mode. All memorybanks are supported with DMA engines foreasily moving A/D data through the FMCcarrier’s PCIe interface.

These powerful linked-list DMA enginesare capable of a unique acquisition gatedriven mode. In this mode, the length ofa transfer performed by a link definitionneed not be known prior to data acquisition;rather, it is governed by the length of theacquisition gate. This is extremely usefulin applications where an external gatedrives acquisition and the exact length ofthat gate is not known or is likely to vary.

For each transfer, the DMA engine canautomatically construct metadata packetscontaining A/D channel ID, a sample-accu-rate time stamp and data-length information.These actions simplify the host processor’stask of identifying and executing on thedata. ➤



● ● ● ● ● FlexorSet Model 7070-316■ Eight 250 MHz, 16-bit A/Ds■ On-board timing bus generator

with multiboard synchronization■ Sample clock synchronization

to an external system reference■ VITA 57 FMC compatible■ Complete radar or software

radio interface solution whencombined with the Model 59733U OpenVPX or Model 7070PCIe Virtex-7 FMC carrier


TIMING BUSGENERATOR


VCXO

250 MHz16-BIT A/D

RF In

RFXFORMRSample Clk /

Reference Clk In A/DClock/SyncBus

16


Control& Status

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

FMCCONNECTOR

New!

New!

New!

New!

New!


Pentek, Inc.

8-Channel 250 MHz, 16-bit A/D - FMCModel 3316

➤➤➤➤➤ Clocking and SynchronizationAn internal timing bus provides all

timing and synchronization required bythe A/D converters. Included are a clock,sync and gate or trigger signals. An on-boardclock generator can receive an external sampleclock from the front-panel coaxial connector.This clock can be used directly by theA/D section or divided by a built-in clocksynthesizer circuit. In an alternate mode,the sample clock can be sourced from anon-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode,the front-panel coaxial connector can beused to provide a 10 MHz reference clockfor synchronizing the internal oscillator.

A front panel Gate/Trigger/PPS connec-tor can receive an external timing signalallowing multiple modules to be synchro-nized to create larger multiboard systems.


Pentek’s ReadyFlow® BSP provides controlof all the 3316’s hardware and IP-basedfunctions. Ready to run examples and afully-sourced C library provide a quick-start and powerful platform to create customapplications. ReadyFlow is compatible withWindows and Linux operating systems.



FPGA Design Kits include all of the factory-installed Virtex-7-based 5973/3316 or7070/3316 IP modules as documentedsource code. Using Xilinx Vivado tools,developers can integrate their own IP withthe Pentek factory-installed functions or usethe GateFlow kit to completely replace thePentek 5973/7070 IP with their own.


57 High Pin Count FMC specification. Theinterface provides all data, clocking, synchro-nization, control and status signals betweenthe 3316 and the FMC carrier.


3316 8-Channel 250 MHz,16-bit A/D - FMC


versions

Model Description






Sample Clock Source: On-board clocksynthesizer

Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO (10 to 810 MHz)or front-panel external clockSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLL systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16

External ClockType: Front panel connector, sine wave,0 to +10 dBm, AC-coupled, 50 ohms,accepts 10 to 800 MHz divider inputclock or PLL system reference



I/O Module Interface: VITA-57.1, High-PinCount FMC






Pentek, Inc.

8-Channel 250 MHz A/D with Virtex-7 FPGA - 3U VPXFlexorSetModel 5973-316

10X160


GTX LVDSGTX

FPGALVDSGPIO

PCIeGen. 3 x8

4X

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

16pairs

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

VPX BACKPLANE

VPX-P1 VPX-P2 (½)

LVDS GTX

VPX-P0

OPTICALTRANSCEIVER

(Optional)


GTX

12X


TIMING BUSGENERATOR


VCXO

250 MHz16-BIT A/D

RF In

RFXFORMR


A/DClock/SyncBus

16


Control& Status

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

FMC CONNECTOR

FMC CONNECTOR

Model 3316 FMC





The delivered FlexorSet is a multichannel,high-speed data converter and is suitable forconnection to the HF or IF ports of a com-munications or radar system. Its built-in datacapture features offer an ideal turnkey solu-tion as well as a platform for developingand deploying custom FPGA processing IP.

It includes eight A/Ds and four banks ofmemory. In addition to supporting PCIeGen. 3 as a native interface, the Model 5973-316includes optional copper and optical connec-tions to the Virtex-7 FPGA for custom I/O.



When delivered as an assembled boardset, the 5973-316 includes factory-installedapplications ideally matched to the board’sanalog interfaces. The functions include eight

A/D acquisition IP modules for simplifyingdata capture and data transfer.

Each of the eight acquisition IP modulescontains IP modules for DDR3 SDRAMmemories. A controller for all data clockingand synchronization functions, a test signalgenerator, and a PCIe interface complete thefactory-installed functions and enable the5973-316 to operate as a turnkey solutionwithout the need to develop any FPGA IP.



FPGA Design Kits include all of the factory-installed modules as documented sourcecode. Developers can integrate their ownIP with the Pentek factory-installed functionsor use the GateFlow kit to completelyreplace the Pentek IP with their own.

Xilinx Virtex-7 FPGAThe 5973-316 can be optionally popu-

lated with one of two Virtex-7 FPGAs tomatch the specific requirements of theprocessing task. Supported FPGAs areVX330T or VX690T. The VX690T features3600 DSP48E1 slices and is ideal for modula-tion/demodulation, encoding/decoding,encryption/decryption, and channelizationof the signals between transmission andreception. For applications not requiring largeDSP resources or logic, the lower-cost VX330Tcan be installed.

A 4X connection between the FPGA andthe VPX P1 connector supports gigabit serialprotocols. ➤

New!

New!

New!

New!

New!




■ Eight 250 MHz 16-bit A/Ds■ 4 GB of DDR3 SDRAM









Model 5973-316


Pentek, Inc.


FLASH through software control. The userselects the desired image and issues areload command.



In all three FPGA loading scenarios,GateXpress handles the hardware negotia-tion simplifying and streamlining theloading task. In addition, GateXpress pre-serves the PCIe configuration space allowingdynamic FPGA reconfiguration withoutneeding to reset the host computer to redis-cover the board. After the reload, the hostsimply continues to see the board with theexpected device ID.

A/D Converter StageThe front end accepts eight analog HF

or IF inputs on front-panel connectors withtransformer-coupling into four Texas Instru-ments ADS42LB69 dual 250 MHz, 16-bitA/D converters. ➤

PCIe INTERFACE

fromA/D Ch 1

PCIe

8X





A/D

ACQUISITION

IP MODULE 1

A/D

ACQUISITION

IP MODULE 2

A/D

ACQUISITION

IP MODULE 8




METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATOR

toMem

Bank 1

toMem

Bank 1

toMem

Bank 4

MEMORYCONTROL

MEMORYCONTROL

MEMORYCONTROLMUX MUX MUX

INPUT MULTIPLEXER

DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

TESTSIGNAL

GENERATOR

8XFPGAGPIO

32MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

toA/D Acq

Mod 1 & 2

toA/D Acq

Mod 3 & 4

toA/D Acq

Mod 5 & 6

toA/D Acq

Mod 7 & 8

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

fromA/D Ch 5

fromA/D Ch 6

fromA/D Ch 7

fromA/D Ch 8

A/D

ACQUISITION

IP MODULES

3 - 7

GigabitSerial I/O

4X

A/D Acquisition IP ModulesThe 5973-316 features eight

A/D Acquisition IP Modulesfor easily capturing and movingdata. Each IP module can receivedata from any of the eight A/Dsor a test signal generator.

Each IP module has anassociated memory bank forbuffering data in FIFO mode orfor storing data in transientcapture mode. All memorybanks are supported with DMAengines for easily moving A/Ddata through the PCIe interface.These powerful linked-list DMAengines are capable of a uniqueAcquisition Gate Driven mode.In this mode, the length of atransfer performed by a linkdefinition need not be knownprior to data acquisition; rather,it is governed by the length of theacquisition gate. This is extremelyuseful in applications where anexternal gate drives acquisitionand the exact length of that gateis not known or is likely to vary.

For each transfer, the DMAengine can automaticallyconstruct metadata packetscontaining A/D channel ID, asample-accurate time stamp anddata length information. Theseactions simplify the host proces-sor’s job of identifying andexecuting on the data.

➤ Option -104 provides 16 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/O.

Option -110 supports the VITA-66.4standard that provides 12 optical duplexlanes to the backplane. With the installationof a serial protocol, the VITA-66.4 interfaceenables gigabit backplane communicationsbetween boards independent of the PCIeinterface.


GateXpress®, a sophisticated FPGA-PCIeconfiguration manager for loading andreloading the FPGA. At power-up, GateXpressimmediately presents a PCIe target for thehost computer to discover, effectively givingthe FPGA time to load from FLASH. This isespecially important for larger FPGAs wherethe loading times can exceed the PCIe dis-covery window, typically 100 msec on manysystems.

The board’s configuration FLASH canhold four FPGA images. Images can be fac-tory-installed IP or custom IP created bythe user, and programmed into the FLASHvia JTAG using Xilinx iMPACT or throughthe board’s PCIe interface. At power-up theuser can choose which image will load basedon a hardware switch setting.

Once booted, GateXpress allows the userthree options for dynamically reconfiguringthe FPGA with a new IP image. The firstoption to load is an alternate image from


Pentek, Inc.










Custom FPGA I/O4X gigabit links between the FPGA andthe VPX P1 connector to support serialprotocols.Parallel (Option -104): 16 pairs ofLVDS connections between the FPGAand the VPX P2 connector for custom I/OOptical (Option -110): VITA-66.4, 12Xduplex lanes




Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

➤➤➤➤➤ Memory ResourcesThe 5973-316 architecture supports four

independent DDR3 SDRAM memory banks.Each bank is 1 GB deep and is an integralpart of the board’s DMA capabilities, pro-viding FIFO memory space for creatingDMA packets.



timing and synchronization required bythe A/D converters. Included are a clock,sync and gate or trigger signals. An on-boardclock generator can receive an external sampleclock from the front-panel coaxial connector.This clock can be used directly by theA/D section or divided by a built-in clocksynthesizer circuit. In an alternate mode,the sample clock can be sourced from anon-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode,the front-panel coaxial connector can beused to provide a 10 MHz reference clock forsynchronizing the internal oscillator.

A front panel Gate/Trigger/PPS connec-tor can receive an external timing signalallowing multiple boards to be synchronizedto create larger multiboard systems.

PCI Express InterfaceThe Model 5973-316 includes an indus-

try-standard interface fully compliant withPCI Express Gen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the board.




5973-316 8-Channel 250 MHz A/Dwith Virtex-7 FPGA - 3UVPX

Options:





versions

Model Description



Pentek, Inc.

8-Channel 250 MHz A/D with Virtex-7 FPGA - x8 PCIeFlexorSetModel 7070-316

10X160

LVDSGTX

FPGALVDSGPIO

PCIeGen. 3 x8

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

16pairs

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER


LVDS GTX

MTP Connector

OPTICALTRANSCEIVER

(Optional)


GTX

12X

TIMING BUSGENERATOR


VCXO

250 MHz16-BIT A/D

RF In

RFXFORMR


A/DClock/SyncBus

16


Control& Status

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

FMC CONNECTOR

FMC CONNECTOR

Model 3316 FMC





The delivered FlexorSet is a multichannel,high-speed data converter and is suitablefor connection to the HF or IF ports of a com-munications or radar system. Its built-in datacapture features offer an ideal turnkey solu-tion as well as a platform for developingand deploying custom FPGA processing IP.

It includes eight A/Ds and four banks ofmemory. In addition to supporting PCIeGen. 3 as a native interface, the Model 7070-316includes optional copper and optical connec-tions to the Virtex-7 FPGA for custom I/O.



When delivered as an assembled boardset, the 7070-316 includes factory-installedapplications ideally matched to the board’s

analog interfaces. The functions include eightA/D acquisition IP modules for simplifyingdata capture and data transfer.

Each of the eight acquisition IP modulescontains IP modules for DDR3 SDRAMmemories. A controller for all data clockingand synchronization functions, a test signalgenerator, and a PCIe interface complete thefactory-installed functions and enable the7070-316 to operate as a turnkey solutionwithout the need to develop any FPGA IP.





lated with one of two Virtex-7 FPGAs tomatch the specific requirements of theprocessing task. Supported FPGAs areVX330T or VX690T. The VX690T features3600 DSP48E1 slices and is ideal for modula-tion/demodulation, encoding/decoding,encryption/decryption, and channelizationof the signals between transmission andreception. For applications not requiring largeDSP resources or logic, the lower-cost VX330Tcan be installed. ➤

New!

New!

New!

New!

New!




■ Eight 250 MHz 16-bit A/Ds■ 4 GB of DDR3 SDRAM





Model 7070-316


Pentek, Inc.


selects the desired image and issues areload command.




A/D Converter StageThe front end accepts eight analog HF

or IF inputs on front-panel connectors withtransformer-coupling into four Texas Instru-ments ADS42LB69 dual 250 MHz, 16-bitA/D converters. ➤

PCIe INTERFACE

fromA/D Ch 1

PCIe

8X





A/D

ACQUISITION

IP MODULE 1

A/D

ACQUISITION

IP MODULE 2

A/D

ACQUISITION

IP MODULE 8




METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATOR

toMem

Bank 1

toMem

Bank 1

toMem

Bank 4

MEMORYCONTROL

MEMORYCONTROL

MEMORYCONTROLMUX MUX MUX

INPUT MULTIPLEXER

DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

TESTSIGNAL

GENERATOR

8XFPGAGPIO

32MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

toA/D Acq

Mod 1 & 2

toA/D Acq

Mod 3 & 4

toA/D Acq

Mod 5 & 6

toA/D Acq

Mod 7 & 8

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

fromA/D Ch 5

fromA/D Ch 6

fromA/D Ch 7

fromA/D Ch 8

A/D

ACQUISITION

IP MODULES

3 - 7

A/D Acquisition IP ModulesThe 7070-316 features eight

A/D Acquisition IP Modulesfor easily capturing and movingdata. Each IP module can receivedata from any of the eight A/Dsor a test signal generator.

Each IP module has anassociated memory bank forbuffering data in FIFO mode orfor storing data in transientcapture mode. All memorybanks are supported with DMAengines for easily moving A/Ddata through the PCIe interface.These powerful linked-list DMAengines are capable of a uniqueAcquisition Gate Driven mode.In this mode, the length of atransfer performed by a linkdefinition need not be knownprior to data acquisition; rather,it is governed by the length of theacquisition gate. This is extremelyuseful in applications where anexternal gate drives acquisitionand the exact length of that gateis not known or is likely to vary.

For each transfer, the DMAengine can automaticallyconstruct metadata packetscontaining A/D channel ID, asample-accurate time stamp anddata length information. Theseactions simplify the host proces-sor’s job of identifying andexecuting on the data.

➤ Option -104 provides 16 pairs of LVDSconnections between the FPGA and a card-edge connector for custom I/O.




The board’s configuration FLASH canhold four FPGA images. Images can be fac-tory-installed IP or custom IP created bythe user, and programmed into the FLASHvia JTAG using Xilinx iMPACT or throughthe board’s PCIe interface. At power-up theuser can choose which image will load basedon a hardware switch setting.

Once booted, GateXpress allows the userthree options for dynamically reconfiguringthe FPGA with a new IP image. The firstoption to load is an alternate image fromFLASH through software control. The user


Pentek, Inc.










Custom FPGA I/OParallel (Option -104): 16 pairs of LVDSconnections between the FPGA and thecard-edge connector for custom I/OOptical (Option -110): 12x gigabit serialoptical I/O with XC7VX690T FPGA, 4xwith XC7VX330T



Environmental: Level L1 & L2 air-cooled,Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

➤➤➤➤➤ Memory ResourcesThe 7070-316 architecture supports four

independent DDR3 SDRAM memory banks.Each bank is 1 GB deep and is an integralpart of the board’s DMA capabilities, pro-viding FIFO memory space for creatingDMA packets.



timing and synchronization required bythe A/D converters. Included are a clock,sync and gate or trigger signals. An on-boardclock generator can receive an external sampleclock from the front-panel coaxial connector.This clock can be used directly by theA/D section or divided by a built-in clocksynthesizer circuit. In an alternate mode,the sample clock can be sourced from anon-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode,the front-panel coaxial connector can beused to provide a 10 MHz reference clock forsynchronizing the internal oscillator.

A front panel Gate/Trigger/PPS connec-tor can receive an external timing signalallowing multiple boards to be synchronizedto create larger multiboard systems.






7070-316 8-Channel 250 MHz A/Dwith Virtex-7 FPGA - x8PCIe

Options:





Model Description



Pentek, Inc.

Model 3320 2-Channel 3.0 GHz A/D, 2-Channel 2.8 GHz D/A - FMC

General InformationThe FlexorTM Model 3320 is a multichannel,

high-speed data converter FMC. It is suitablefor connection to RF or IF ports of a commu-nications or radar system. It includes two3.0 GHz A/Ds, two 2.8 GHz D/As,programmable clocking and multiboardsynchronization for support of larger high-channel-count systems.



unlocked only when used with the PentekModel 5973 or Model 7070 FMC carriers.With factory-installed IP, the board-set pro-vides a turnkey data acquisition subsystemeliminating the need to create any FPGA IP.Installed features include flexible A/D acqui-sition, programmable linked-list DMAengines, and D/A waveform playback IPmodules.

Designed to allow users to optimizedata conversion rates and modes for specificapplication requirements, the FlexorSet pro-vides preconfigured conversion profiles.Users can use these profiles which include:digital downconverter and digital upconvertermodes, conversion resolution and A/D andD/A sample rates, or program their ownprofiles. In addition to supporting PCIeGen. 3 as a native interface, the FlexorSetincludes optional copper and optical connec-tions to the Virtex-7 FPGA for custom I/O.

A/D and Digital Downconverter StageThe front end accepts two analog RF

or IF inputs on front-panel connectors with

transformer-coupling into a Texas InstrumentsADC32RF45 dual channel A/D. With dualbuilt-in digital downconverters and program-mable decimations, the converter serves as anideal interface for a range of radar, signalintelligence and electronic countermeasuresapplications. The ADC32RF45 can oper-ate within a range of different conversionspeeds and resolutions. See the table on thelast page for supported modes.


5973 or the 7070 carrier, the board-set featurestwo A/D Acquisition IP Modules for easilycapturing and moving data. Each module canreceive data from either of the two A/Ds, a testsignal generator or from the two D/A wave-form playback IP modules in loopback mode.

Each IP module can have an associatedmemory bank on the FMC carrier for buffer-ing data in FIFO mode or for storing data intransient capture mode. All memory banksare supported with DMA engines for easilymoving A/D data through the FMC carrier’sPCIe interface.

These powerful linked-list DMA enginesare capable of a unique acquisition gate-driven mode. In this mode, the length ofa transfer performed by a link definitionneed not be known prior to data acquisition;rather, it is governed by the length of theacquisition gate. This is extremely usefulin applications where an external gatedrives acquisition and the exact length ofthat gate is not known or is likely to vary.

For each transfer, the DMA engine canautomatically construct metadata packetscontaining A/D channel ID, a sample-accu-rate time stamp and data-length information.These actions simplify the host processor’sjob of identifying and executing on the data. ➤



● ● ● ● ● FlexorSet Model 7070-320■ Supports Xilinx Virtex-7 VXT

FPGAs


■ Two 3.0 GHz* A/Ds

■ Two 2.8 GHz* D/As■ Two digital downconverters■ Two digital upconverters

■ 4 GB of DDR3 SDRAM■ Sample clock synchronization

to an external system reference■ VITA 57 FMC compatible■ Ruggedized and conduction-


New!

New!

New!

New!

New!

RF In RF OutRF In RF Out

TIMING BUSGENERATOR


VCXO

3.0 GHz

14-BIT A/D

*

RFXFORMR


A/DClock/SyncBus


Control& Status

RFXFORMR

2.8 GHz

16-BIT D/A

*

DIGITALUPCONVERT

RFXFORMR

DIGITALUPCONVERT

D/AClock/SyncBus

FMC CONNECTOR

DIGITALDOWNCONVERT

3.0 GHz

14-BIT A/D

*

RFXFORMR

DIGITALDOWNCONVERT

RFXFORMR

2.8 GHz

16-BIT D/A

*

DIGITALUPCONVERT

RFXFORMR

DIGITALUPCONVERT

* See last page for configuration profiles


Pentek, Inc.


➤ ➤ ➤ ➤ ➤ Digital Upconverter and D/A StageTwo Texas Instruments DAC39J84

D/As accept two baseband real or complexdata streams from the FPGA. Each stream thenpasses through the upconvert, interpolateand D/A stages of the converter.

When operating as DUCs (digital upcon-verters), the converters interpolate andtranslate real or complex baseband inputsignals to a programmable IF center frequency.The data is then delivered to the dual 16-bitD/A converter stages. Analog outputs arethrough front panel connectors.

If translation is disabled, the D/As actas interpolating 16-bit D/As with outputsampling rates up to 2.8 GHz. In both modesthe D/As provide interpolation factorsfrom 1x to 16x.

D/A Waveform Playback IP ModulesA Texas Instruments DAC39J84 D/A

accepts two baseband real or complex datastreams from the FPGA. Each stream thenpasses through the upconvert, interpolateand D/A stages of the converter.


If translation is disabled, the D/As actas interpolating 16-bit D/As with outputsampling rates up to 2.8 GHz. In both modesthe D/As provide programmable interpo-lation.

Clocking and SynchronizationThe 3320 architecture includes a timing

bus generator, responsible for providingclocking to the data converters, FPGA andall synchronization circuits. When pairedwith the 5973 or the 7070, the FlexorSet’sbuilt-in functions include setup and supportof the timing generator to produce the pre-defined data conversion profiles. Thissimplifies operation by allowing users toeasily change profiles through software.

The timing bus generator has a built-infrequency synthesizer that allows the boardto operate without the need for an externalsample clock. If users prefer, an externalclock can be accepted on a front panel coaxconnector. In addition, the connector can beprogrammed to accept a 10 MHz systemreference, locking the on-board clock to thereference that enables synchronization acrossmultiple boards.

A front panel LVTTL Gate/Trigger/Syncconnector is also included on the board.Users can program the connector’s functionto operate in one of three modes to matchthe application requirements.


Pentek’s ReadyFlow® BSP provides controlof all the 3320’s hardware and IP-basedfunctions. Ready to run examples and afully-sourced C library provide a quick-startand powerful platform to create customapplications. ReadyFlow is compatible withWindows and Linux operating systems.



FPGA Design Kits include all of the factory-installed Virtex-7-based 5973/320 or7070/320 modules as documented sourcecode. Using Xilinx Vivado tools, developerscan integrate their own IP with the Pentekfactory-installed functions or use theGateFlow kit to completely replace thePentek 5973/7070 IP with their own.


57 High-Pin Count FMC specification. Theinterface provides all data, clocking, synchro-nization, control and status signals betweenthe 3320 and the FMC carrier. ➤




integrated VPX developmentsystem for Pentek Cobalt, Onyxand Flexor VPX boards. It wascreated to save engineers andsystem integrators the time andexpense associated with build-ing and testing a developmentsystem that ensures optimumperformance of Pentek boards.


Pentek, Inc.


➤➤➤➤➤ Model 3320 SpecificationsFront Panel Analog Signal Inputs

Input Type: Transformer-coupled, frontpanel SSMC connectorsTransformer Type: Mini-CircuitsTC1-1-13MFull Scale Input: +6.6 dBm into 50 ohms3 dB Passband: 4.5 to 3000 MHz

A/D ConvertersType: Texas Instruments ADC32RF45Sampling Rate and Resolution: Seetable below

Front Panel Analog Signal OutputsOutput Type: Transformer-coupled, front

panel SSMC connectorsTransformer Type: Coil Craft WBC4-14LFull-Scale Output: +4 dBm into 50 ohms3 dB Passband: 1.5 MHz to 1200 MHzD/A Converters

Type: Texas Instruments DAC39J84Sampling Rate and Resolution: Seetable below

Sample Clock Sources: Timing bus gen-erator provides A/D and D/A clocks

Timing Bus GeneratorClock Source: Selectable from on-boardfrequency synthesizer or front panelexternal clockSynchronization: Frequency synthesizercan be locked to an external 10 MHzPLL system reference

External ClockType: Front panel SSMC connector, sinewave, 0 to +10 dBm, AC-coupled,50 ohms

External Trigger InputType: Front panel SSMC connectorFunction: Programmable functionsinclude: trigger, gate, sync and PPS


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

Pre-configured Conversion Profiles*

ConverterSample Rate

OutputResolution

DecimationReal /

ComplexInterpolation

Real /Complex

Input DataRate**

A/D Converter D/A Converter

2.8 GHz 16 bit 4 complex 2 5.6 GB/sec complex

3.0 GHz 16 bit 4 complex n/a n/a n/a

* Other modes can be custom-configured by the user

OutputData Rate**

2.8 GB/sec

3.0 GB/sec

2.8 GHz 16 bit 4 complex 4 2.8 GB/sec complex2.8 GB/sec

2.0 GHz 14 bit bypass real 2 4.0 GB/sec complex4.0 GB/sec

2.0 GHz 14 bit bypass real 2 2.0 GB/sec real4.0 GB/sec

2.5 GHz 12 bit bypass real5.0 GB/sec n/a n/a n/a


** Per channel, output data rates are subject to maximum PCIe bus speeds of the host computer


5973-320 2-Channel 3.0 GHz A/D,2-Channel 2.8 GHz D/Awith Virtex-7 FPGA - 3UVPX

Options:



-110 VITA-66.4 12X (withVX690T), 4X (withVX330T) opticalinterface


versions


7070-320 2-Channel 3.0 GHz A/D,2-Channel 2.8 GHz D/Awith Virtex-7 FPGA - x8PCIe

Options:






Pentek, Inc.

2-Ch. 3.0 GHz A/D, 2-Ch. 2.8 GHz D/A wth Virtex-7 - 3U VPXFlexorSetModel 5973-320

10X160


GTX LVDSGTX

FPGALVDSGPIO

PCIeGen. 3 x8

4X

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

16pairs

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

VPX BACKPLANE

VPX-P1 VPX-P2 (½)

LVDS GTX

VPX-P0

OPTICALTRANSCEIVER

(Optional)


GTX

12X


FMC CONNECTORModel 5973 FMC Carrier

Model 3320 FMC

TIMING BUSGENERATOR


VCXO

3.0 GHz

14-BIT A/D

*

RF In

RFXFORMR


A/DClock/SyncBus


Control& Status

RFXFORMR

2.8 GHz

16-BIT D/A

*

DIGITALUPCONVERT

RF Out

RFXFORMR

DIGITALUPCONVERT

D/AClock/SyncBus

FMC CONNECTOR

DIGITALDOWNCONVERT

3.0 GHz

14-BIT A/D

*

RF In

RFXFORMR

DIGITALDOWNCONVERT

RFXFORMR

2.8 GHz

16-BIT D/A

*

DIGITALUPCONVERT

RF Out

RFXFORMR

DIGITALUPCONVERT




The delivered FlexorSet is a multichannel,high-speed data converter and is suitable forconnection to the RF or IF ports of a com-munications or radar system. Its built-in datacapture and playback features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGA-processing IP.

Designed to allow users to optimizedata conversion rates and modes for specificapplication requirements, the FlexorSet pro-vides preconfigured conversion profiles.Users can use these profiles which include:digital downconverter and digital upconvertermodes, conversion resolution and A/D andD/A sample rates, or program their ownprofiles. In addition to supporting PCIeGen. 3 as a native interface, the Model 5973-320includes optional copper and optical connec-tions to the Virtex-7 FPGA for custom I/O.



When delivered as an assembled boardset, the 5973-320 includes factory-installedapplications ideally matched to the board’sanalog interfaces. The functions include twoA/D acquisition IP modules for simplifyingdata capture and data transfer.

Each of the acquisition IP modulescontains IP modules for DDR3 SDRAMmemories.

The 5973-320 features two sophisticatedD/A waveform playback IP modules. Alinked-list controller allows users to easilyplay back to the D/As waveforms stored ineither on-board or off-board host memory.Parameters including length of waveform,delay from playback trigger, waveformrepetition, etc. can be programmed for eachwaveform. ➤

New!

New!

New!

New!

New!




■ Two 3.0 GHz* A/Ds■ Two 2.8 GHz* D/As

■ Two digital downconverters■ Two digital upconverters■ 4 GB of DDR3 SDRAM








cooled versions available * See last page for configuration profiles

Model 5973-320


Pentek, Inc.



Option -110 supports the VITA-66.4standard that provides up to 12 opticalduplex lanes to the backplane. With theinstallation of a serial protocol, theVITA-66.4 interface enables gigabit com-munications between boards independentof the PCIe interface.



The board’s configuration FLASH canhold four FPGA images. Images can befactory-installed IP or custom IP created bythe user, and programmed into the FLASHvia JTAG using Xilinx iMPACT or throughthe board’s PCIe interface. At power-upthe user can choose which image will loadbased on a hardware switch setting.

Once booted, GateXpress allows the userthree options for dynamically reconfiguringthe FPGA with a new IP image. The firstoption to load is an alternate image fromFLASH through software control. The userselects the desired image and issues areload command. ➤

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE 2

D/A

WAVEFORM

PLAYBACK

IP MODULE 1

FromA/D Ch 1

FromA/D Ch 2

ToD/A Ch 2

ToD/A Ch 1


FPGAGPIO

D/A loopback

D/A loopback





A/D

ACQUISITION

IP MODULE 1


METADATAGENERATOR

A/D

ACQUISITION

IP MODULE 2


METADATAGENERATOR

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUXMUX



toMemBank

toMemBank

MEMORYCONTROL

MEMORYCONTROL

8X 4X32 MemoryBanks 3 & 4

32MemoryBanks 1 & 2

32

To Acquisition /PlaybackModule

MUX

toMemBank

MEMORYCONTROL

DATAPACKING& FLOW

CONTROL

MUX

toMemBank

MEMORYCONTROL

DATAPACKING& FLOW

CONTROL


➤ In each playback module, up to 64 indi-vidual link entries can be chained together tocreate complex waveforms with a minimumof programming.





Xilinx Virtex-7 FPGAThe 5973-320 can be optionally populated

with one of two Virtex-7 FPGAs to matchthe specific requirements of the process-ing task. Supported FPGAs are VX330T orVX690T. The VX690T features 3600 DSP48E1slices and is ideal for modulation/demodu-lation, encoding/decoding, encryption/decryption, and channelization of the signalsbetween transmission and reception. Forapplications not requiring large DSPresources or logic, the lower-cost VX330Tcan be installed.


A/D Acquisition IP ModulesThe 5973-320 features two

A/D Acquisition IP Modulesfor easy capture and data mov-ing. Each IP module can receivedata from any of the two A/Ds,a test signal generator or fromthe two D/A Waveform PlaybackIP modules in loopback mode.



For each transfer, the DMAengine can automaticallyconstruct metadata packets con-taining A/D channel ID, a sampleaccurate time stamp, and datalength information. These actionssimplify the host processor’s jobof identifying and executing onthe data.

D/A Waveform Playback IPModules

The 5973-320 factory-installedfunctions include two sophis-ticated D/A Waveform PlaybackIP modules. A linked-list control-ler allows users to easily playback waveforms stored in eitheron-board or off-board hostmemory to the two D/As.

Parameters including length ofwaveform, delay from playbacktrigger, waveform repetition,etc. can be programmed for eachwaveform. Up to 64 individuallink entries per module can bechained together to createcomplex waveforms with aminimum of programming.


Pentek, Inc.


Digital Upconverter and D/A StageA Texas Instruments DAC39J84 D/A





bus generator, responsible for providingclocking to the data converters, FPGA andall synchronization circuits. When pairedwith the 7070, the FlexorSet’s built-in func-tions include setup and support of the timinggenerator to produce the predefined dataconversion profiles. This simplifies opera-tion by allowing users to easily changeprofiles through software.

The timing bus generator has a built infrequency synthesizer that allows the boardto operate without the need of an externalsample clock. If users prefer, an externalclock can be accepted on a front panel coaxconnector. In addition, the connector can beprogrammed to accept a 10 MHz systemreference, locking the on-board clock to thereference that enables synchronization acrossmultiple boards.

A front panel LVTTL Gate/Trigger/Syncconnector is also included on the board.Users can program the connector’s functionto operate in one of three modes to matchthe application requirements. ➤

➤ The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. This isimportant in security situations where therecan be no latent user image left in non-volatile memory when power is removed. Inapplications where the FPGA IP may needto change many times during the course of amission, images can be stored on the hostcomputer and loaded through PCIe as needed.



Memory ResourcesThe 5973-320 architecture supports four

independent DDR3 SDRAM memory banks.Each bank is 1 GB deep and is an integralpart of the board’s waveform playbackcapabilities, providing local storage foruser waveforms.



A/D Converter and Digital Downcon-verter Stage

The front end accepts two analog RFor IF inputs on front-panel connectors withtransformer-coupling into a Texas InstrumentsADC32RF45 dual channel A/D. With dualbuilt-in digital downconverters and program-mable decimations, the converter serves as anideal interface for a range of radar, signalintelligence and electronic countermea-sures applications. The ADC32RF45 canoperate within a range of different con-version speeds and resolutions. See thetable on next page for supported modes.




Pentek, Inc.



5973-320 2-Channel 3.0 GHz A/D,2-Channel 2.8 GHz D/Awith Virtex-7 FPGA - 3UVPX

Options:



-110 VITA-66.4 12X (withVX690T), 4X (withVX330T) optical interface


versions

Model Description









Timing Bus GeneratorClock Source: Selectable from on-boardfrequency synthesizer or front panel ex-ternal clockSynchronization: Frequency synthesizercan be locked to an external 10 MHzPLL system reference




Custom FPGA I/O4X gigabit links between the FPGAand the VPX P1 connector to supportserial protocols.Parallel (Option -104): 16 pairs ofLVDS connections between the FPGAand the VPX P2 connector for custom I/OOptical (Option -110): User configurableVITA-66.4, 12X (with VX690T) or 4X(with VX330T) duplex lanes




Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)



OutputResolution

DecimationReal /


Real /Complex

Input DataRate**





OutputData Rate**

2.8 GB/sec

3.0 GB/sec








Pentek, Inc.

2-Ch. 3.0 GHz A/D, 2-Ch. 2.8 GHz D/A with Virtex-7 - x8 PCIeFlexorSetModel 7070-320

10X160


LVDSGTX

FPGALVDSGPIO

PCIeGen. 3 x8

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

16pairs

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER


LVDS GTX

MTP Connector

OPTICALTRANSCEIVER

(Optional)


GTX

12X

Model 3320 FMC

TIMING BUSGENERATOR


VCXO

3.0 GHz

14-BIT A/D

*

RF In

RFXFORMR


A/DClock/SyncBus


Control& Status

RFXFORMR

2.8 GHz

16-BIT D/A

*

DIGITALUPCONVERT

RF Out

RFXFORMR

DIGITALUPCONVERT

D/AClock/SyncBus

FMC CONNECTOR

DIGITALDOWNCONVERT

3.0 GHz

14-BIT A/D

*

RF In

RFXFORMR

DIGITALDOWNCONVERT

RFXFORMR

2.8 GHz

16-BIT D/A

*

DIGITALUPCONVERT

RF Out

RFXFORMR

DIGITALUPCONVERT




The delivered FlexorSet is a multichannel,high-speed data converter and is suitable forconnection to the RF or IF ports of a com-munications or radar system. Its built-in datacapture and playback features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGA-processing IP.

Designed to allow users to optimizedata conversion rates and modes for specificapplication requirements, the FlexorSet pro-vides preconfigured conversion profiles.Users can use these profiles which include:digital downconverter and digital upconvertermodes, conversion resolution and A/D andD/A sample rates, or program their ownprofiles. In addition to supporting PCIeGen. 3 as a native interface, the Model 5973-320includes optional copper and optical connec-tions to the Virtex-7 FPGA for custom I/O.



When delivered as an assembled boardset, the 7070-320 includes factory-installedapplications ideally matched to the board’sanalog interfaces. The functions include twoA/D acquisition IP modules for simplifyingdata capture and data transfer.

Each of the acquisition IP modulescontains IP modules for DDR3 SDRAMmemories.

The 7070-320 features two sophisticatedD/A waveform playback IP modules. Alinked-list controller allows users to easilyplay back to the D/As waveforms stored ineither on-board or off-board host memory.Parameters including length of waveform,delay from playback trigger, waveformrepetition, etc. can be programmed for eachwaveform. ➤

New!

New!

New!

New!

New!




■ Two 3.0 GHz* A/Ds■ Two 2.8 GHz* D/As

■ Two digital downconverters■ Two digital upconverters■ 4 GB of DDR3 SDRAM





* See last page for configuration profiles

Model 7070-320


Pentek, Inc.


Option -104 provides 16 pairs of LVDSconnections between the FPGA and acard-edge connector for custom I/O.

Option -110 supports the VITA-66.4standard that provides up to 12 opticalduplex lanes to the backplane. With theinstallation of a serial protocol, theVITA-66.4 interface enables gigabit com-munications between boards independentof the PCIe interface.



The board’s configuration FLASH canhold four FPGA images. Images can befactory-installed IP or custom IP created bythe user, and programmed into the FLASHvia JTAG using Xilinx iMPACT or throughthe board’s PCIe interface. At power-upthe user can choose which image will loadbased on a hardware switch setting.

Once booted, GateXpress allows the userthree options for dynamically reconfiguringthe FPGA with a new IP image. The firstoption to load is an alternate image fromFLASH through software control. The userselects the desired image and issues areload command. ➤

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE 2

D/A

WAVEFORM

PLAYBACK

IP MODULE 1

FromA/D Ch 1

FromA/D Ch 2

ToD/A Ch 2

ToD/A Ch 1

PCIeFPGAGPIO

D/A loopback

D/A loopback





A/D

ACQUISITION

IP MODULE 1


METADATAGENERATOR

A/D

ACQUISITION

IP MODULE 2


METADATAGENERATOR

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUXMUX



toMemBank

toMemBank

MEMORYCONTROL

MEMORYCONTROL

8X32 MemoryBanks 3 & 4

32MemoryBanks 1 & 2

32


MUX

toMemBank

MEMORYCONTROL

DATAPACKING& FLOW

CONTROL

MUX

toMemBank

MEMORYCONTROL

DATAPACKING& FLOW

CONTROL


➤ In each playback module, up to 64 indi-vidual link entries can be chained together tocreate complex waveforms with a minimumof programming.





Xilinx Virtex-7 FPGAThe 7070-320 can be optionally populated

with one of two Virtex-7 FPGAs to matchthe specific requirements of the process-ing task. Supported FPGAs are VX330T orVX690T. The VX690T features 3600 DSP48E1slices and is ideal for modulation/demodu-lation, encoding/decoding, encryption/decryption, and channelization of the signalsbetween transmission and reception. Forapplications not requiring large DSP re-sources or logic, the lower-cost VX330Tcan be installed.

A/D Acquisition IP ModulesThe 7070-320 features two

A/D Acquisition IP Modulesfor easy capture and data mov-ing. Each IP module can receivedata from any of the two A/Ds,a test signal generator or fromthe two D/A Waveform PlaybackIP modules in loopback mode.





The 7070-320 factory-installedfunctions include two sophis-ticated D/A Waveform PlaybackIP modules. A linked-list control-ler allows users to easily playback waveforms stored in eitheron-board or off-board hostmemory to the two D/As.

Parameters including length ofwaveform, delay from playbacktrigger, waveform repetition,etc. can be programmed for eachwaveform. Up to 64 individuallink entries per module can bechained together to createcomplex waveforms with aminimum of programming.


Pentek, Inc.


Digital Upconverter and D/A StageA Texas Instruments DAC39J84 D/A





bus generator, responsible for providingclocking to the data converters, FPGA andall synchronization circuits. When pairedwith the 7070, the FlexorSet’s built-in func-tions include setup and support of the timinggenerator to produce the predefined dataconversion profiles. This simplifies opera-tion by allowing users to easily changeprofiles through software.

The timing bus generator has a built infrequency synthesizer that allows the boardto operate without the need of an externalsample clock. If users prefer, an externalclock can be accepted on a front panel coaxconnector. In addition, the connector can beprogrammed to accept a 10 MHz systemreference, locking the on-board clock to thereference that enables synchronization acrossmultiple boards.

A front panel LVTTL Gate/Trigger/Syncconnector is also included on the board.Users can program the connector’s functionto operate in one of three modes to matchthe application requirements. ➤

➤ The second option is for applicationswhere the FPGA image must be loadeddirectly through the PCIe interface. This isimportant in security situations where therecan be no latent user image left in non-volatile memory when power is removed. Inapplications where the FPGA IP may needto change many times during the course of amission, images can be stored on the hostcomputer and loaded through PCIe as needed.



Memory ResourcesThe 7070-320 architecture supports four

independent DDR3 SDRAM memory banks.Each bank is 1 GB deep and is an integralpart of the board’s waveform playbackcapabilities, providing local storage foruser waveforms.



A/D Converter and Digital Downcon-verter Stage

The front end accepts two analog RFor IF inputs on front-panel connectors withtransformer-coupling into a Texas InstrumentsADC32RF45 dual channel A/D. With dualbuilt-in digital downconverters and program-mable decimations, the converter serves as anideal interface for a range of radar, signalintelligence and electronic countermea-sures applications. The ADC32RF45 canoperate within a range of different con-version speeds and resolutions. See thetable on next page for supported modes.


Pentek, Inc.



7070-320 2-Channel 3.0 GHz A/D,2-Channel 2.8 GHz D/Awith Virtex-7 FPGA - x8PCIe

Options:




Model Description









Timing Bus GeneratorClock Source: Selectable from on-boardfrequency synthesizer or front panel ex-ternal clockSynchronization: Frequency synthesizercan be locked to an external 10 MHzPLL system reference




Custom FPGA I/OParallel (Option -104): 16 pairs of LVDSconnections between the FPGA and acard-edge connector for custom I/OOptical (Option -110): User configurableVITA-66.4, 12X (with VX690T) or 4X(with VX330T) duplex lanes



Environmental: Level L1 & L2 air-cooledSize: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)





OutputResolution

DecimationReal /


Real /Complex

Input DataRate**





OutputData Rate**

2.8 GB/sec

3.0 GB/sec








Pentek, Inc.

4-Ch. 500 MHz 16-bit A/D, 4-Ch. 2 GHz 16-bit D/A-FMCModel 3324

General InformationThe FlexorTM Model 3324 is a multichannel,

high-speed data converter FMC. It is suitablefor connection to HF or IF ports of a commu-nications or radar system. It includes four500 MHz, 16-bit A/Ds, four 2 GHz, 16-bitD/As, programmable clocking, and multi-board synchronization for support of largerhigh-channelcount systems.


A/D ConvertersThe front end accepts four analog HF

or IF inputs on front-panel connectors withtransformer-coupling into four 500 MHz,16-bit A/D converters.


unlocked only when used with the PentekModel 5973 or Model 7070 FMC carriers.With factory-installed IP, the board-set pro-vides a turnkey data acquisition subsystemeliminating the need to create any FPGA IP.Installed features include flexible A/D acqui-sition, programmable linked-list DMAengines, and a D/A waveform playback IPmodule.


5973 or the 7070 carrier, the board-set featuresfour A/D Acquisition IP Modules for easilycapturing and moving data. Each modulecan receive data from any of the four A/Ds,

a test signal generator or from the D/Awaveform playback IP module in loopbackmode.

Each IP module can have an associatedmemory bank on the FMC carrier for buffer-ing data in FIFO mode or for storing data intransient capture mode. All memory banksare supported with DMA engines for easilymoving A/D data through the FMC carrier’sPCIe interface.

These powerful linked-list DMA enginesare capable of a unique acquisition gate-driven mode. In this mode, the length ofa transfer performed by a link definitionneed not be known prior to data acquisition;rather, it is governed by the length of theacquisition gate. This is extremely usefulin applications where an external gatedrives acquisition and the exact length ofthat gate is not known or is likely to vary.

For each transfer, the DMA engine canautomatically construct metadata packetscontaining A/D channel ID, a sample-accu-rate time stamp and data-length information.These actions simplify the host processor’sjob of identifying and executing on the data.

D/A Waveform Playback IP ModulesWhith the 5973 or the 7070, the 3324

features four sophisticated D/A waveformplayback IP modules. A linked-list con-troller allows users to easily play backvia the D/As waveforms stored in eitheron-board or off-board host memory.

Parameters including length of wave-form, delay from playback trigger, waveformrepetition, etc. can be programmed for eachwaveform. Up to 64 individual link entriesper module can be chained together to createcomplex waveforms with a minimum ofprogramming. ➤



● ● ● ● ● FlexorSet Model 7070-324■ Four 500 MHz, 16-bit A/Ds

■ Four digital upconverters■ Four 2 GHz, 16-bit D/As

(500 MHz input data rate,2 GHz output sample ratewith interpolation)

■ On-board timing bus generatorwith multiboard synchronization


■ VITA 57 FMC compatible

■ Complete radar or softwareradio interface solution whencombined with the Model 59733U OpenVPX or Model 7070PCIe Virtex-7 FMC carrier


TIMING BUSGENERATOR


VCXO

500 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

500 MHz16-BIT A/D


A/DClock/SyncBus

RF In

RFXFORMR

500 MHz16-BIT A/D

RF In

RFXFORMR

500 MHz16-BIT A/D


FMCCONNECTOR

Control& Status

RFXFORMR

2 GHz16-BIT D/A

DIGITALUPCONVERT

RF Out

RFXFORMR

RFXFORMR

2 GHz16-BIT D/A

DIGITALUPCONVERT

RF Out

RFXFORMR

RFXFORMR

RF Out

RFXFORMR

RFXFORMR

RF Out

RFXFORMR

D/AClock/SyncBus

2 GHz16-BIT D/A

2 GHz16-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

New!

New!

New!

New!

New!


Pentek, Inc.

4-Ch. 500 MHz 16-bit A/D, 4-Ch. 2 GHz 16-bit D/A-FMCModel 3324

➤➤➤➤➤ Digital Upconverters and D/AsFour D/As accept baseband real or com-

plex data streams from the FPGA. Each streamthen passes through the upconvert, interpo-late and D/A stages of the converter.

When operating as DUCs (digital upcon-verters), the converters interpolate andtranslate real or complex baseband inputsignals to a programmable IF center frequency.The data is then delivered to the 16-bit D/Aconverter stages. Analog outputs are throughfront panel connectors.

If translation is disabled, the D/As actas interpolating 16-bit D/As with outputsampling rates up to 1.5 GHz. In both modesthe D/As provide interpolation factors of2x, 4x, 8x and 16x.


timing and synchronization required bythe A/D and D/A converters. Each includesa clock, sync and gate or trigger signals. Anon-board clock generator receives an exter-nal sample clock from the front panelcoaxial connector. This clock can be useddirectly by the A/D or D/A sections ordivided by a built-in clock synthesizercircuit to provide different A/D and D/Aclocks. In an alternate mode, the sampleclock can be sourced from an on-boardprogrammable VCXO (Voltage-ControlledCrystal Oscillator). In this mode, the frontcoaxial panel connector can be used toprovide a 10 MHz reference clock for synchro-nizing the internal oscillator.

A front panel Gate/Trigger/PPS connec-tor can receive an external timing signalallowing multiple modules to be synchro-nized and create larger multiboard systems.


Pentek’s ReadyFlow® BSP provides controlof all the 3324’s hardware and IP-basedfunctions. Ready to run examples and afully-sourced C library provide a quick-startand powerful platform to create customapplications. ReadyFlow is compatible withWindows and Linux operating systems.



FPGA Design Kits include all of the factory-installed Virtex-7-based 5973/3324 or7070/3324 modules as documented


3324 4-Channel 500 MHz16-bit A/D, 4-Channel2 GHz 16-bit D/A - FMC


versions

Model Description



source code. Using Xilinx Vivado tools,developers can integrate their own IP withthe Pentek factory-installed functions oruse the GateFlow kit to completely replacethe Pentek 5973/7070 IP with their own.


57 High-Pin Count FMC specification. Theinterface provides all data, clocking, synchro-nization, control and status signals betweenthe 3324 and the FMC carrier.



A/D ConvertersType: Texas Instruments ADS54J60Sampling Rate: up to 500 MHzResolution: 16 bits


panel connectorsTransformer Type: Coil Craft WBC4-6TLBFull-Scale Output: +4 dBm into 50 ohms3 dB Passband: 300 kHz to 700 MHzD/A Converters

Type: Texas Instruments DAC38J84Input Data Rate: Up to 500 MHzOutput Sample Rate: Up to 2 GHz (withinterpolation)Resolution: 16 bits

Sample Clock Source: On-board clocksynthesizer

Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO (10 to 810 MHz)or front-panel external clockSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLL systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16 for theA/D and D/A clocks




I/O Module Interface: VITA-57.1, High-pin-count FMC




integrated VPX developmentsystem for Pentek Cobalt, Onyxand Flexor VPX boards. It wascreated to save engineers andsystem integrators the time andexpense associated with buildingand testing a developmentsystem that ensures optimumperformance of Pentek boards.


Pentek, Inc.

4-Ch. 500 MHz 16-bit A/D, 4-Ch. 2 GHz 16-bit D/A - 3U VPXFlexorSetModel 5973-324

10X160


GTX LVDSGTX

FPGALVDSGPIO

PCIeGen. 3 x8

4X

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

16pairs

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

VPX BACKPLANE

VPX-P1 VPX-P2 (½)

LVDS GTX

VPX-P0

OPTICALTRANSCEIVER

(Optional)


GTX

12X



Model 3324 FMC

TIMING BUSGENERATOR


VCXO

500 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

500 MHz16-BIT A/D


A/DClock/SyncBus

RF In

RFXFORMR

500 MHz16-BIT A/D

RF In

RFXFORMR

500 MHz16-BIT A/D


Control& Status

RFXFORMR

2 GHz16-BIT D/A

DIGITALUPCONVERT

RF Out

RFXFORMR

RFXFORMR

2 GHz16-BIT D/A

DIGITALUPCONVERT

RF Out

RFXFORMR

RFXFORMR

RF Out

RFXFORMR

RFXFORMR

RF Out

RFXFORMR

D/AClock/SyncBus

2 GHz16-BIT D/A

2 GHz16-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

FMC CONNECTOR




The delivered FlexorSet is a multichannel,high-speed data converter and is suitable forconnection to the HF or IF ports of a com-munications or radar system. Its built-in datacapture and playback features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGAprocessing IP.

It includes four 500 MHz, 16-bit A/Ds,four digital upconverters, four 2 GHz, 16-bit D/As, and four banks of memory. Inaddition to supporting PCIe Gen. 3 as anative interface, the Model 5973-324 includesoptional copper and optical connections tothe Virtex-7 FPGA for custom I/O.


Onyx family of Virtex-7 products, the 5973FMC carrier retains all the key features ofthat family. As a central foundation of theboard architecture, the FPGA has access toall data and control paths of both the carrier

board and the FMC module, enabling factory-installed functions that include datamultiplexing, channel selection, data pack-ing, gating, triggering and memory control.

When delivered as an assembled boardset, the 5973-324 includes factory-installedapplications ideally matched to the board’sanalog interfaces. The functions include fourA/D acquisition IP modules for simplifyingdata capture and data transfer.


The 5973-324 features four sophisticatedD/A waveform playback IP modules. Alinked-list controller allows users to easilyplay back to the D/As waveforms stored ineither on-board or off-board host memory.Parameters including length of waveform,delay from playback trigger, waveform rep-etition, etc. can be programmed for eachwaveform.

In each playback module, up to 64 indi-vidual link entries can be chained togetherto create complex waveforms with a mini-mum of programming.

A controller for all data clocking andsynchronization functions, a test signalgenerator, and a PCIe interface complete thefactory-installed functions and enable the5973-324 to operate as a turnkey solutionwithout the need to develop any FPGA IP. ➤

New!

New!

New!

New!

New!


FPGAs



■ Four digital upconverters■ Four 2 GHz 16-bit D/As

(500 MHz input sample rate,2 GHz output sample ratewith interpolation)










Model 5973-324


Pentek, Inc.


configuration manager for loading andreloading the FPGA. At power-up, GateXpressimmediately presents a PCIe target for thehost computer to discover, effectively givingthe FPGA time to load from FLASH. This isespecially important for larger FPGAs wherethe loading times can exceed the PCIe dis-covery window, typically 100 msec on manysystems.




The third option, typically used duringdevelopment, allows the user to directly loadthe FPGA through JTAG using XilinxiMPACT. ➤

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE 4

D/A

WAVEFORM

PLAYBACK

IP MODULE 1

FromA/D Ch 1

FromA/D Ch 2

FromA/D Ch 3

FromA/D Ch 4

ToD/A Ch 4

ToD/A Ch 1

ToD/A Ch 2


FPGAGPIO

D/A loopback

D/A loopback





A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 4


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUXMUX



toMem

Bank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROL

MEMORYCONTROL

8X 4X32

A/D

ACQUISITION

IP MODULES

2 & 3

2 goes to

Mem Bank 1

3 goes to

Mem Bank 2

MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

To A/D AcqModules 1 & 2


To D/A PlaybackModules 1 & 2


D/A

WAFEFORM

PLAYBACK

IP MODULES

2 & 3

2 goes to

Mem Bank 3

3 goes to

Mem Bank 4

ToD/A Ch3

➤➤➤➤➤ Extendable IP DesignFor applications that require specialized







Option -110 supports the VITA-66.4standard that provides 12 optical duplexlanes to the backplane. With the installationof a serial protocol, the VITA-66.4 interfaceenables gigabit communications betweenboards independent of the PCIe interface.


GateXpress®, a sophisticated FPGA-PCIe


A/D Acquisition IP Modulesfor easy capture and data mov-ing. Each IP module can receivedata from any of the four A/Ds,a test signal generator or fromthe four D/A Waveform PlaybackIP modules in loopback mode.





The 5973-324 factory-installedfunctions include four sophis-ticated D/A Waveform PlaybackIP modules. A linked-list control-ler allows users to easily playback waveforms stored in eitheron-board or off-board hostmemory to the four D/As.

Parameters including length ofwaveform, delay from playbacktrigger, waveform repetition,etc. can be programmed for eachwaveform. Up to 64 individuallink entries per module can bechained together to create com-plex waveforms with aminimum of programming.


Pentek, Inc.


Full Scale Input: +4 dBm into 50 ohms3 dB Passband: 300 kHz to 750 MHz

A/D ConvertersType: Texas Instruments ADS54J60 Sampling Rate: Up to 500 MHz Resolution: 16 bits





Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO (10 to 810 MHz),front panel external clock or LVPECLtiming busSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLL systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8 or 16 for theA/D and D/A clocks








Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

➤ In all three FPGA loading scenarios,GateXpress handles the hardware negotia-tion simplifying and streamlining theloading task. In addition, GateXpress pre-serves the PCIe configuration space allowingdynamic FPGA reconfiguration withoutneeding to reset the host computer to redis-cover the board. After the reload, the hostsimply continues to see the board with theexpected device ID.


or IF inputs on front-panel connectors withtransformer-coupling into 500 MHz, 16-bitA/D converters.

Digital Upconverter and D/A StageFour D/As accept baseband real or com-



If translation is disabled, the D/As actas interpolating 16-bit D/As with outputsampling rates up to 2 GHz. In both modesthe D/As provide interpolation factors of2x, 4x, 8x and 16x.





Input Type: Transformer-coupled, frontpanel connectorsTransformer Type: Coil Craft WBC1-1TLB








5973-324 4-Channel 500 MHz 16-bitA/D, 4-Channel 2 GHz16-bit D/A with Virtex-7FPGA - 3U VPX

Options:





versions

Model Description



Pentek, Inc.

4-Ch. 500 MHz 16-bit A/D, 4-Ch. 2 GHz 16-bit D/A - x8 PCIeFlexorSetModel 7070-324

Model 3324 FMC

TIMING BUSGENERATOR


VCXO

500 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

500 MHz16-BIT A/D


A/DClock/SyncBus

RF In

RFXFORMR

500 MHz16-BIT A/D

RF In

RFXFORMR

500 MHz16-BIT A/D


Control& Status

RFXFORMR

2 GHz16-BIT D/A

DIGITALUPCONVERT

RF Out

RFXFORMR

RFXFORMR

2 GHz16-BIT D/A

DIGITALUPCONVERT

RF Out

RFXFORMR

RFXFORMR

RF Out

RFXFORMR

RFXFORMR

RF Out

RFXFORMR

D/AClock/SyncBus

2 GHz16-BIT D/A

2 GHz16-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

FMC CONNECTOR

10X160


LVDSGTX

FPGALVDSGPIO

PCIeGen. 3 x8

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

16pairs

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER


LVDS GTX

MTP Connector

OPTICALTRANSCEIVER

(Optional)


GTX

12X




The delivered FlexorSet is a multichannel,high-speed data converter and is suitable forconnection to the HF or IF ports of a com-munications or radar system. Its built-in datacapture and playback features offer an idealturnkey solution as well as a platform fordeveloping and deploying custom FPGAprocessing IP.

It includes four 500 MHz, 16-bit A/Ds,four digital upconverters, four 2 GHz,16-bit D/As, and four banks of memory. Inaddition to supporting PCIe Gen. 3 as anative interface, the Model 7070-324 includesoptional copper and optical connections tothe Virtex-7 FPGA for custom I/O.


Onyx family of Virtex-7 products, the 7070FMC carrier retains all the key features ofthat family. As a central foundation of theboard architecture, the FPGA has access toall data and control paths of both the carrierboard and the FMC module, enabling factory-installed functions that include data

multiplexing, channel selection, data pack-ing, gating, triggering and memory control.

When delivered as an assembled boardset, the 7070-324 includes factory-installedapplications ideally matched to the board’sanalog interfaces. The functions include fourA/D acquisition IP modules for simplifyingdata capture and data transfer.


The 7070-324 features four sophisticatedD/A waveform playback IP modules. Alinked-list controller allows users to easilyplay back to the D/As waveforms stored ineither on-board or off-board host memory.Parameters including length of waveform,delay from playback trigger, waveform rep-etition, etc. can be programmed for eachwaveform.

In each playback module, up to 64 indi-vidual link entries can be chained togetherto create complex waveforms with a mini-mum of programming.



functions, users can install their custom ➤

New!

New!

New!

New!

New!


FPGAs



■ Four digital upconverters■ Four 2 GHz 16-bit D/As

(500 MHz input data rate,

2 GHz output sample ratewith interpolation)

■ 4 GB of DDR3 SDRAM■ Sample clock synchronization





Model 7070-324


Pentek, Inc.


especially important for larger FPGAs wherethe loading times can exceed the PCIediscovery window, typically 100 msec onmany systems.




The third option, typically used duringdevelopment, allows the user to directlyload the FPGA through JTAG usingXilinx iMPACT.

In all three FPGA loading scenarios,GateXpress handles the hardware negotia-tion simplifying and streamlining theloading task. In addition, GateXpress pre-serves the PCIe configuration space ➤

PCIe INTERFACE

D/A

WAVEFORM

PLAYBACK

IP MODULE 4

D/A

WAVEFORM

PLAYBACK

IP MODULE 1

FromA/D Ch 1

FromA/D Ch 2

FromA/D Ch 3

FromA/D Ch 4

ToD/A Ch 4

ToD/A Ch 1

ToD/A Ch 2

PCIeFPGAGPIO

D/A loopback

D/A loopback





A/D

ACQUISITION

IP MODULE 1


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

A/D

ACQUISITION

IP MODULE 4


DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUXMUX



toMem

Bank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROL

MEMORYCONTROL

8X32

A/D

ACQUISITION

IP MODULES

2 & 3

2 goes to

Mem Bank 1

3 goes to

Mem Bank 2

MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32





D/A

WAFEFORM

PLAYBACK

IP MODULES

2 & 3

2 goes to

Mem Bank 3

3 goes to

Mem Bank 4

ToD/A Ch3

➤ IP for data processing. Pentek Gate-Flow® FPGA Design Kits include all of thefactory-installed modules as documentedsource code. Developers can integrate theirown IP with the Pentek factory-installedfunctions or use the GateFlow kit to com-pletely replace the Pentek IP with their own.



Option -104 provides 16 pairs of LVDSconnections between the FPGA and a card-edge connector for custom I/O.



GateXpress®, a sophisticated FPGA-PCIeconfiguration manager for loading andreloading the FPGA. At power-up, GateXpressimmediately presents a PCIe target for thehost computer to discover, effectively givingthe FPGA time to load from FLASH. This is


A/D Acquisition IP Modulesfor easy capture and data mov-ing. Each IP module can receivedata from any of the four A/Ds,a test signal generator or fromthe D/A Waveform Playback IPModules in loopback mode.





The 7070-324 factory-installedfunctions include four sophis-ticated D/A Waveform PlaybackIP modules. A linked-list control-ler allows users to easily playback waveforms stored in eitheron-board or off-board hostmemory to the four D/As.

Parameters including length ofwaveform, delay from playbacktrigger, waveform repetition, etc.can be programmed for eachwaveform. Up to 64 individuallink entries per module can bechained together to create com-plex waveforms with aminimum of programming.


Pentek, Inc.


A/D ConvertersType: Texas Instruments ADS54J60 Sampling Rate: Up to 500 MHz Resolution: 16 bits





Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO (10 to 810 MHz),front panel external clock or LVPECLtiming busSynchronization: VCXO can be lockedto an external 4 to 180 MHz PLL systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8 or 16 for theA/D and D/A clocks




Custom FPGA I/OParallel (Option -104): 16 pairs of LVDSconnections between the FPGA and acard-edge connector for custom I/OOptical (Option -110): 12x gigabit serialoptical I/O with XC7VX690T FPGA,4x with XC7VX330T




Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)

➤ allowing dynamic FPGA reconfigurationwithout needing to reset the host computerto rediscover the board. After the reload, thehost simply continues to see the board withthe expected device ID.


or IF inputs on front-panel connectors withtransformer-coupling into 500 MHz, 16-bitA/D converters.

Digital Upconverter and D/A StageFour D/As accept baseband real or com-



If translation is disabled, the D/As actas interpolating 16-bit D/As with outputsampling rates up to 2 GHz. In both modesthe D/As provide interpolation factors of2x, 4x, 8x and 16x.





Input Type: Transformer-coupled, frontpanel connectorsTransformer Type: Coil Craft WBC1-1TLBFull-Scale Input: +4 dBm into 50 ohms3 dB Passband: 300 kHz to 750 MHz








7070-324 4-Channel 500 MHz 16-bitA/D, 4-Channel 2 GHz16-bit D/A with Virtex-7FPGA - x8 PCIe

Options:





Model Description



Pentek, Inc.

Bandit Two-Channel Analog RF WidebandDownconverter - PMC/XMCModel 7120

General InformationThe Bandit® Model 7120 is a two-channel,

high-performance, stand-alone analog RFwideband downconverter. Packaged in asmall, shielded PMC/XMC module withfront-panel connectors for easy integrationinto RF systems, the module offers program-mable gain, high dynamic range and a lownoise figure.

With an input frequency range from 400to 4000 MHz and a wide IF bandwidth ofup to 390 MHz, the 7120 is an ideal solutionfor amplifying and downconverting antennasignals for communications, radar andsignal intelligence systems.

Programmable Input LevelThe 7120 accepts RF signals on two

front-panel SSMC connectors. LNAs (LowNoise Amplifiers) are provided, along withtwo programmable attenuators allowingdownconversion of input signals rangingfrom –60 dBm to –20 dBm in steps of 0.5 dB.Higher level signals can be attenuated priorto input.

Input Filter OptionsAn optional five-stage lowpass or

bandpass input filter can be included withseveral available frequency and attenuationcharacteristics for RF image rejection andharmonic suppression.

Quadrature MixersThe 7120 features a pair of Analog

Devices ADL5380 quadrature mixers. TheADL5380’s are capable of excellent accuracy

with amplitude and phase balances of~0.07 dB and ~0.2°, respectively.

Tuning AccuracyThe 7120 uses an Analog Devices

ADF4351 low-noise, on-board frequencysynthesizer as the LO (Local Oscillator).Locked to an external input reference foraccuracy with a fractional-N phase-lockedloop, its frequency is programmable acrossthe 400 to the 4000 MHz band with a tuningresolution of better than 100 kHz.

On-board Reference ClockIn addition to accepting a 10 MHz refer-

ence signal on the front panel, the 7120includes an on-board 10 MHz crystal oscil-lator which can be used as the reference tolock the internal LO frequency synthesizer.

This reference is an OCXO (Oven Con-trolled Crystal Oscillator), which providesan exceptionally precise frequency standardwith excellent phase noise characteristics.

Wideband OutputOutput is provided as baseband I and Q

signals at bandwidths up to 390 MHz. Alter-natively, either I or Q output can be used atsome intermediate offset frequency con-venient to the application. User-providedin-line output IF filters allow customizingthe output bandwidth and offset frequencyto the specific application requirements.This output is suitable for A/D conversionusing Pentek high-performance signalacquisition products, such as those in theCobalt and Onyx families. ➤


400 MHz to 4000 MHz■ Accepts RF input levels from

-60 dBm to -20 dBm■ Baseband IF output with

up to 390 MHz bandwidth■ Internal OCXO or external

10 MHz frequency reference

RF In

USB

I/QDOWNCONVERTER

SYNTHESIZER

Ref In

RF InI/Q

DOWNCONVERTER

SYNTHESIZER

I

Q

I

Q

Gain 1 Control

Gain 2 Control

Tuning Control

USBINTERFACE

Gain 1 Control

Gain 1 Control

Tuning Control

Tuning Control

IF I Out

IF Q Out

IF I Out

IF Q Out

(option 015)

Ref Out

OVENCONTROLLEDREFERENCEOSCILLATOR

(optional)

LOWPASSOR

BANDPASSFILTER

Gain 2 Control

(optional)

LOWPASSOR

BANDPASSFILTER

Gain 2 Control

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP


Pentek, Inc.

Bandit Two-Channel Analog RF WidebandDownconverter - PMC/XMCModel 7120


7120 Bandit Two-ChannelAnalog RF WidebandDownconverter -PMC/XMC

Option Description

-015 Oven ControlledRefernece Oscillator

-104 PMC P11 Power

-105 XMC P15 Power

-106 PCIe 6-pin connector(Power only)

-145 1.45 GHz lowpass inputfilter


➤➤➤➤➤ SpecificationsRF Input

Connector Type: SSMCInput Impedance: 50 ohmsInput Level Range: –60 dBm to –20 dBm

Flatness: ±2 dB from 400 MHz to 1 GHz,±3 dB from 1 GHz to 3 GHz, ±5 dB from3 GHz to 4 GHz

RF Attenuator: Programmable from 0 to63 dB in 0.5 dB steps

LO Synthesizer TuningFrequency range: 400–4000 MHz,Resolution: < 10 kHzTuning Speed: < 500 µsecPhase-Locked Loop Bandwidth: 100 kHz

Phase Noise1 kHz: –90 dBc/Hz100 kHz: –110 dBc/Hz1 MHz: –130 dBc/Hz

Noise Figure (referred to input)60 dB gain: 2.6 dB

Inband Output IP320 dB gain: +10 dBm60 dB gain: +42 dBm

Reference Input/OutputConnector Type: SSMCInput/Output Impedence: 50 ohmsReference Input Signal

Frequency: 10 MHzLevel: 0 dBm, sine wave

Reference Output SignalFrequency: 10 MHzLevel: 0 dBm, sine wave

OCXO ReferenceCenter Frequency: 10 MHzFrequency Stability vs. Change in Temperature: ±50.0 ppbFrequency Calibration: ±1.0 ppmAging Daily: ±10 ppb/day First Year: ±300 ppbTotal Frequency Tolerance (20 years): ±4.60 ppmPhase Noise 1 Hz Offset: –67 dBc/Hz 10 Hz Offset: –100 dBc/Hz 100 Hz Offset: –130 dBc/Hz 1 KHz Offset: –148 dBc/Hz 10 KHz Offset: –154 dBc/Hz 100 KHz Offset: –155 dBc/Hz

IF OutputConnector Type: SSMCOutput Impedance: 50 ohmsCenter Frequency: User definableOutput Level: 0 dBm, nominal

ProgrammingFunctions: RF Atten, IF Atten, Int/ExtReference Select, LO Synthesizer FrequencyInterface: USBConnector Type: MicroUSB

PowerVoltage: +12 VDCCurrent: 1.5 A

PMC/XMC Interface: Power only on PMCP11 (option -104) or XMC P15 (option -105)

Size: Standard PMC module, 2.91 in. x 5.87 in.


Pentek, Inc.

Bandit Two-Channel Analog RF Wideband Downconverter - PCIeModel 7820


high-performance, stand-alone analog RFwideband downconverter. Packaged in asmall, shielded PCIe board with front-panelconnectors for easy integration into RF sys-tems, the board offers programmable gain,high dynamic range and a low noise figure.





















RF In

USB

I/QDOWNCONVERTER

SYNTHESIZER

Ref In

RF InI/Q

DOWNCONVERTER

SYNTHESIZER

I

Q

I

Q

Gain 1 Control

Gain 2 Control

Tuning Control

USBINTERFACE

Gain 1 Control

Gain 1 Control

Tuning Control

Tuning Control

IF I Out

IF Q Out

IF I Out

IF Q Out

(option 015)

Ref Out


(optional)

LOWPASSOR

BANDPASSFILTER

Gain 2 Control

(optional)

LOWPASSOR

BANDPASSFILTER

Gain 2 Control

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP


Pentek, Inc.

Bandit Two-Channel Analog RF Wideband Downconverter - PCIeModel 7820


7820 Bandit Two-ChannelAnalog RF WidebandDownconverter - PCIe

Option Description

-015 Oven ControlledReference Oscillator


















PCI-Express InterfacePCI Express Bus: x4 or x8, power only




Pentek, Inc.

Bandit Two-Channel Analog RF WidebandDownconverter - 3U VPXModel 5220


high-performance, stand-alone analog RFwideband downconverter. Packaged in asmall, shielded 3U VPX board with front-panelconnectors for easy integration into RF sys-tems, the board offers programmable gain,high dynamic range and a low noise figure.





















RF In

USB

I/QDOWNCONVERTER

SYNTHESIZER

Ref In

RF InI/Q

DOWNCONVERTER

SYNTHESIZER

I

Q

I

Q

Gain 1 Control

Gain 2 Control

Tuning Control

USBINTERFACE

Gain 1 Control

Gain 1 Control

Tuning Control

Tuning Control

IF I Out

IF Q Out

IF I Out

IF Q Out

(option 015)

Ref Out


(optional)

LOWPASSOR

BANDPASSFILTER

Gain 2 Control

(optional)

LOWPASSOR

BANDPASSFILTER

Gain 2 Control

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP



Pentek, Inc.

Bandit Two-Channel Analog RF WidebandDownconverter - 3U VPXModel 5220


5220 Bandit Two-ChannelAnalog RF WidebandDownconverter - 3U VPX

Option Description



















PCI Express InterfacePCIe Bus: x4, power only


Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)


Pentek, Inc.

Bandit Two- or Four-Channel Analog RF WidebandDownconverter - 6U OpenVPX

Models5720 & 5820

RF In

USB

I/QDOWNCONVERTER

SYNTHESIZER

Ref In

RF InI/Q

DOWNCONVERTER

SYNTHESIZER

I

Q

I

Q

Gain 1 Control

Gain 2 Control

Tuning Control

USBINTERFACE

Gain 1 Control

Gain 1 Control

Tuning Control

Tuning Control

IF I Out

IF Q Out

IF I Out

IF Q Out

(option 015)

Ref Out


(optional)

LOWPASSOR

BANDPASSFILTER

Gain 2 Control

(optional)

LOWPASSOR

BANDPASSFILTER

Gain 2 Control

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

General InformationThese Bandit® models are two- or four-chan-

nel, high-performance, stand-alone analogRF wideband downconverters. Packagedin small, shielded 6U VPX boards withfront-panel connectors for easy integrationinto RF systems, they offer programmablegain, high dynamic range and a low noisefigure.

Model 5720 is a 6U VPX board thatprovides two channels, while Model 5820 isa double-density 6U VPX board that providesfour channels.

With an input frequency range from 400to 4000 MHz and a wide IF bandwidth ofup to 390 MHz, these models are ideal solu-tions for amplifying and downconvertingantenna signals for communications, radarand signal intelligence systems.

Programmable Input LevelThe models accept RF signals on two

or four front-panel SSMC connectors. LNAs(Low Noise Amplifiers) are provided, alongwith two programmable attenuators allow-ing downconversion of input signals rangingfrom –60 dBm to –20 dBm in steps of 0.5 dB.



Quadrature MixersThese models feature Analog Devices

ADL5380 quadrature mixers. The ADL5380’s

are capable of excellent accuracy withamplitude and phase balances of ~0.07 dBand ~0.2°, respectively.

Tuning AccuracyThese models use the Analog Devices



ence signal on the front panel, these modelsinclude on-board 10 MHz crystal oscillatorswhich can be used as the reference to lockthe internal LO frequency synthesizers.


Wideband OutputOutputs are provided as baseband I and

Q signals at bandwidths up to 390 MHz.Alternatively, either I or Q output can beused at some intermediate offset frequencyconvenient to the application. User-providedin-line output IF filters allow customizingthe output bandwidth and offset frequencyto the specific application requirements.This output is suitable for A/D conversionusing Pentek high-performance signalacquisition products, such as those in theCobalt and Onyx families. ➤

Features■ Accept RF signals from

400 MHz to 4000 MHz

■ Accept RF input levels from-60 dBm to -20 dBm

■ Baseband IF output withup to 390 MHz bandwidth

■ Internal OCXO or external10 MHz frequency reference

New!

New!

New!

New!

New!

Model 5820

Model 5720 Block DiagramModel 5820 Doubles all Resources.


Pentek, Inc.

Bandit Two- or Four-Channel Analog RF WidebandDownconverter - 6U OpenVPX

Models5720 & 5820


5720 Bandit Two-ChannelAnalog RF WidebandDownconverter - 6U VPX

Single Density

5820 Bandit Four-ChannelAnalog RF WidebandDownconverter - 6U VPXDouble Density

Option Description



















PCI Express InterfacePCI Bus: x4 or x8, power only


Size: 233 mm x 160 mm (9.173 in. x 6.299 in.)


Pentek, Inc.

Bandit Two- or Four-Channel Analog RF WidebandDownconverter - 6U/3U cPCI

Models 7220, 7420and 7320

RF In

USB

I/QDOWNCONVERTER

SYNTHESIZER

Ref In

RF InI/Q

DOWNCONVERTER

SYNTHESIZER

I

Q

I

Q

Gain 1 Control

Gain 2 Control

Tuning Control

USBINTERFACE

Gain 1 Control

Gain 1 Control

Tuning Control

Tuning Control

IF I Out

IF Q Out

IF I Out

IF Q Out

(option 015)

Ref Out


(optional)

LOWPASSOR

BANDPASSFILTER

Gain 2 Control

(optional)

LOWPASSOR

BANDPASSFILTER

Gain 2 Control

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

General InformationThese Bandit® models are two- or four-chan-

nel, high-performance, stand-alone analogRF wideband downconverters. Packagedin small, shielded cPCI boards with front-panel connectors for easy integration intoRF systems, they offer programmable gain,high dynamic range and a low noise figure.

Model 7320 is a 3U cPCI booard whileModel 7220 is a 6U cPCI board; both providetwo channels, while Model 7420 is a double-density 6U cPCI board that provides fourchannels.

With an input frequency range from 400to 4000 MHz and a wide IF bandwidth ofup to 390 MHz, these models are ideal solu-tions for amplifying and downconvertingantenna signals for communications, radarand signal intelligence systems.

Programmable Input LevelThe models accept RF signals on two

or four front-panel SSMC connectors. LNAs(Low Noise Amplifiers) are provided, alongwith two programmable attenuators allow-ing downconversion of input signals rangingfrom –60 dBm to –20 dBm in steps of 0.5 dB.



Quadrature MixersThese models feature Analog Devices

ADL5380 quadrature mixers. The ADL5380’s

are capable of excellent accuracy withamplitude and phase balances of ~0.07 dBand ~0.2°, respectively.

Tuning AccuracyThese models use the Analog Devices



ence signal on the front panel, these modelsinclude on-board 10 MHz crystal oscillatorswhich can be used as the reference to lockthe internal LO frequency synthesizers.


Wideband OutputOutputs are provided as baseband I and

Q signals at bandwidths up to 390 MHz.Alternatively, either I or Q output can beused at some intermediate offset frequencyconvenient to the application. User-providedin-line output IF filters allow customizingthe output bandwidth and offset frequencyto the specific application requirements.This output is suitable for A/D conversionusing Pentek high-performance signalacquisition products, such as those in theCobalt and Onyx families. ➤

Features■ Accept RF signals from

400 MHz to 4000 MHz

■ Accept RF input levels from-60 dBm to -20 dBm

■ Baseband IF output withup to 390 MHz bandwidth


Model 7420 Model 7320


Pentek, Inc.

Bandit Two- or Four-Channel Analog RF WidebandDownconverter - 6U/3U cPCI

Models 7220, 7420and 7320


7220 Bandit Two-ChannelAnalog RF WidebandDownconverter - 6U cPCI

7320 Bandit Two-ChannelAnalog RF WidebandDownconverter - 3U cPCI

7420 Bandit Four-ChannelAnalog RF WidebandDownconverter - 6U cPCI

Option Description



















PCI InterfacePCI Bus: 32-bit, 66 MHz (supports33 MHz), power only




Pentek, Inc.

Bandit Two-Channel Analog RF Wideband Downconverter - AMCModel 5620


high-performance, stand-alone analog RFwideband downconverter. Packaged in asmall, shielded AMC board with front-panelconnectors for easy integration into RF sys-tems, the board offers programmable gain,high dynamic range and a low noise figure.





















RF In

USB

I/QDOWNCONVERTER

SYNTHESIZER

Ref In

RF InI/Q

DOWNCONVERTER

SYNTHESIZER

I

Q

I

Q

Gain 1 Control

Gain 2 Control

Tuning Control

USBINTERFACE

Gain 1 Control

Gain 1 Control

Tuning Control

Tuning Control

IF I Out

IF Q Out

IF I Out

IF Q Out

(option 015)

Ref Out


(optional)

LOWPASSOR

BANDPASSFILTER

Gain 2 Control

(optional)

LOWPASSOR

BANDPASSFILTER

Gain 2 Control

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP

LOWNOISEAMP


Pentek, Inc.

Bandit Two-Channel Analog RF Wideband Doanconverter - AMCModel 5620


5620 Bandit Two-ChannelAnalog RF WidebandDownconverter - AMC

Option Description



















PCI-Express InterfacePCI Express Bus: Gen. 1 x4 or x8, poweronly




Pentek, Inc.

Bandit Modular Analog RF Slot Downconverter SeriesModel 8111

General InformationThe Bandit® Model 8111 provides a seriesof high-performance, stand-alone analog RFslot downconverter modules. Packaged ina small, shielded enclosure with connec-tors for easy integration into RF systems, themodules offer programmable gain, highdynamic range and a low noise figure.With input options to cover specific frequencybands of the RF spectrum, and an IF outputoptimized for A/D converters, the 8111 is anideal solution for amplifying and down-converting antenna signals for communica-tions, radar and signal intelligence systems.

Programmable Input LevelThe 8111 accepts RF signals on a front

panel SMA connector. An LNA (Low Noise-figure Amplifier) is provided along withtwo programmable attenuators allowingdownconversion of input signals rangingfrom -60 dBm to -20 dBm in steps of 0.5 dB.Higher level signals can be attenuated priorto input.

Preselector OptionsSeven different input-frequency band

options are offered, each tunable across a400 MHz band, with an overlap of 100 MHzbetween adjacent bands. As a group, theseseven options accommodate RF input signalsfrom 800 MHz to 3.000 GHz as follows:

Option Frequency Band001 800-1200 MHz002 1100-1500 MHz003 1400-1800 MHz004 1700-2100 MHz005 2000-2400 MHz006 2300-2700 MHz007 2600-3000 MHz

Tuning AccuracyThe 8111 uses a low-noise, on-board

frequency synthesizer as the LO (LocalOscillator). Locked to an external inputreference for accuracy, its frequency is pro-grammable across the 400 MHz band witha tuning resolution of 1 MHz. Alternatively,for applications demanding custom localoscillator characteristics, an external LOinput signal can be accepted on a front panelconnector and used instead of the on-boardfrequency synthesizer.

On-board Reference ClockIn addition to accepting a reference sig-

nal on the front panel, the 8111 includes anon-board 10 MHz crystal oscillator whichcan be used as the reference to lock theinternal LO frequency synthesizer.


IF OutputAn 80 MHz-wide IF output is provided

at a 225 MHz center frequency . This out-put is suitable for A/D conversion usingPentek high-performance signal acquisitionproducts, such as those in the Cobalt andOnyx families. ➤


800 MHz to 3.000 GHz inseven different models

■ Accepts RF input levels from-60 to -20 dBm

■ 225 MHz IF output with80 MHz output bandwidth


RF SWITCH

RF In IF Out

RefIn

ExtLOIn

BANDPASSFILTER

STEPATTENUATOR

STEPATTENUATOR

MIXER IF FILTER

RF Attenuation

IF Attenuation

LO Select

LO Synthesizer Tuning Frequency

USBINTERFACE

LOWNOISEAMP

GAINBLOCK

GAINBLOCK

GAINBLOCK

GAINBLOCK

ControlIn

OVENCONTROLLED

CRYSTALOSCILLATOR

RefOut

LO


Pentek, Inc.

Bandit Modular Analog RF Slot Downconverter SeriesModel 8111


8111 Bandit Modular AnalogRF Slot Downconverter

Option Input Frequency Band

-001 800-1200 MHz

-002 1100-1500 MHz

-003 1400-1800 MHz

-004 1700-2100 MHz

-005 2000-2400 MHz

-006 2300-2700 MHz

-007 2600-3000 MHz

SpecificationsRF Input

Connector Type: SMAInput Impedance: 50 ohmsInput Level Range: -60 dBm to -20 dBm

Flatness: ±1 dB typical over each 400 MHzrange

RF Attenuator: Programmable from 0 to31.5 dB in 0.5 dB steps

LO Synthesizer TuningFrequency range: 800-3000 MHz, across seven different optionsResolution: 1 MHz

Tuning Speed: < 500 µsecPLL Loop Bandwidth: 100 kHzPhase Noise

1 kHz: -90 dBc/Hz100 kHz: -110 dBc/Hz1 MHz: -130 dBc/Hz



Reference / External LO InputConnector Type: SMAInput Impedence: 50 ohmsReference Input Signal

Frequency: 10 MHzLevel: 0 dBm to +20 dBm, sinewave

External LO Input SignalFrequency: ƒIN+225 MHz, where

ƒIN= RF input signal frequencyLevel: 0 dBm ±2 dBm

OCXO Reference OutputConnector Type: SMACenter Frequency: 10 MHzOutput Impedance: 50 ohmsOutput Level: +10 dBm, nominal,

sine waveFrequency Stability vs. Change in Temperature: ±50.0 ppbFrequency Calibration: ±1.0 ppmAging Daily: ±10 ppb/day First Year: ±300 ppbTotal Frequency Tolerance (20 years): ±4.60 ppmPhase Noise 1 Hz Offset: -67 dBc/Hz 10 Hz Offset: -100 dBc/Hz 100 Hz Offset: -130 dBc/Hz 1 KHz Offset: -148 dBc/Hz 10 KHz Offset: -154 dBc/Hz 100 KHz Offset: -155 dBc/Hz

IF Attenuator: Programmable from 0 to31.5 dB in 0.5 dB steps

IF OutputConnector Type: SMAOutput Impedance: 50 ohmsCenter Frequency: 225 MHzOutput Level: 0 dBm, nominal

ProgrammingFunctions: RF Atten, IF Atten, Int/ExtLO Select, LO Synthezier FrequencyInterface: USBConnector Type: MicroUSB

PowerVoltage: +12VDCCurrent: 1.5 AConnector Type: Micro DB-9, female

Size: Module, 3.75 in x 7.5 in x 0.7 in


Pentek, Inc.

Model 8264 6U OpenVPX Development System for Cobalt and Onyx Boards

General InformationThe Model 8264 is a fully-integrated,

6U VPX development system for PentekCobalt® and Onyx® software radio, dataacquisition, and I/O boards. It was createdto save engineers and system integratorsthe time and expense associated with build-ing and testing a development system thatensures optimum performance of Pentekboards.

A fully-integrated system-level solution,the 8264 provides the user with a stream-lined out-of-the-box experience. It comespreconfigured with Pentek hardware, driversand software examples installed and testedto allow development engineers to runexample applications out of the box.

ReadyFlow SoftwarePentek ReadyFlow drivers and board

support libraries are preinstalled and testedwith the 8264. ReadyFlow includes exampleapplications with full source code, acommand line interface for custom con-trol over hardware, and Pentek’s SignalAnalyzer, a full-featured analysis tool thatcontinuously displays live signals in bothtime and frequency domains.

System ImplementationBuilt on a professional 9U rackmount

workstation, the 8264 is equipped with thelatest Intel i7 processor, DDR3 SDRAM anda high-performance single-board computer.These features accelerate application codedevelopment and provide unhindered accessto the high-bandwidth data available withCobalt and Onyx analog and digital inter-faces. The 8264 can be configured with 64-bitWindows or Linux operating systems.

New!

New!

New!

New!

New!

Features■ 9U 19-inch rackmount, 9-slot,

16-inch deep chassis whichhouses 6U VPX boards

■ 64-bit Windows® 7 Professionalor Linux® workstation

■ Intel® CoreTM i7 3.6 GHzprocessor

■ 16 GB DDR3 SDRAM

■ ReadyFlow® drivers andboard support librariesinstalled

■ Out-of-the-box ready-to-runexamples

The 8264 uses a 19” 9U rackmount chas-sis that is 16” deep. Nine VPX slots provideample space for an SBC, a switch card andmultiple Pentek boards. Enhanced forced-air ventilation assures adequate cooling forall boards and dual 500-W power suppliesgurantee more than adequate power for allinstalled boards. Mounting provisions fortwo 3.5 in. drives with front-accessible traysallow for easy removable storage. Front-panelaccess to USB, display, Ethernet and RS-232ports simplifies development; an optional reartransition module supplements the front-panel connections with SATA, audio, a secondvideo interface, and additional USB ports.

ConfigurationAll 8264 systems come with software and

hardware installed and tested. Up to sevenPentek boards in the 8264 can be supported.Please contact Pentek to configure a systemthat matches your specific requirements.

OptionsAvailable options include high-end multi-

core CPUs and choice of Windows or Linux.

SpecificationsOperating System: 64-bit Windows 7

Professional or LinuxProcessor: Intel Core i7 processor Clock Speed: 3.6 GHzSDRAM: 16 GBDimensions: 6U Chassis, 19" W x 16" D x

10.5" HWeight: 50 lb, approx.Operating Temp: 0° to +50° CStorage Temp: –40° to +85° CRelative Humidity: 5 to 95%, non-condensingPower Requirements: 100 to 240 VAC,

50 to 60 Hz, 1000 W max.


8264 6U VPX DevelopmentSystem for Cobalt andOnyx Boards

Options:

-094 64-bit Linux OS

-095 64-bit Windows 7 OS

The addition of third-party VPXboards may affect system per-formance. Please consult withus before doing so.


Pentek, Inc.

Model 8266 PC Development System for PCIe Cobalt, Onyx and Flexor Boards

General InformationThe Model 8266 is a fully-integrated

PC development system for Pentek Cobalt®,Onyx® and FlexorTM PCI Express softwareradio, data acquisition, and I/O boards. Itwas created to save engineers and systemintegrators the time and expense associatedwith building and testing a development sys-tem that ensures optimum performanceof Pentek boards.





workstation, the 8266 is equipped with thelatest Intel processor, DDR3 SDRAM and ahigh-performance motherboard. Thesefeatures accelerate application code devel-opment and provide unhindered access tothe high-bandwidth data available with Cobalt,Onyx and Flexor analog and digital interfaces.

Features■ 4U 19-inch rackmount PC

server chassis, 21-inch deep■ 64-bit Windows® 7 Professional

or Linux® workstation■ Intel® CoreTM i7 3.6 GHz

processor■ 8 GB DDR3 SDRAM■ ReadyFlow® drivers and

board support librariesinstalled

■ Out-of-the-box test examples

The 8266 can be configured with 64-bitWindows or Linux operating systems.

The 8266 uses a 19” 4U rackmountchassis that is 21” deep. Enhanced forced-air ventilation assures adequate cooling forPentek Cobalt, Onyx and Flexor boards.

The chassis is designed to draw cool airfrom the front and push warm air out theback. A 1000 W, 80+ Gold Power Supplyguarantees more than enough power foradditional boards.

ConfigurationPentek uses a variety of motherboards

to provide the flexibility for operation andcooling of each system. Up to four PentekCobalt, Onyx or Flexor boards in the 8266can be supported. Please contact Pentek toconfigure a system that requires additionalPCIe slots for 3rd party hardware.

OptionsOptions for high-end multicore CPUs

and extended memory support applicationsthat require additional horsepower areavailable.


Professional or LinuxProcessor: Intel Core i7 processorClock Speed: 3.6 GHzSDRAM: 8 GBDimensions: 4U Chassis, 19" W x 21" D x 7" HWeight: 35 lb, approx.Operating Temp: 0° to +50° CStorage Temp: –40° to +85° CRelative Humidity: 5 to 95%, non-condensingPower Requirements: 100 to 240 VAC,

50 to 60 Hz, 1000 W max.


8266 PC Development Systemfor PCIe Cobalt, Onyx andFlexor Boards

Options:



-101 Upgrade to 64 GBDDR3 SDRAM

The addition of third-party PCIecards may affect system perfor-mance. Please consult with usbefore doing so.


Pentek, Inc.

Model 8267 3U VPX Development System for Cobalt, Onyx and Flexor Boards

General InformationThe Model 8267 is a fully-integrated,

3U VPX development system for PentekCobalt®, Onyx® and FlexorTM softwareradio, data acquisition, and I/O boards. Itwas created to save engineers and systemintegrators the time and expense associatedwith building and testing a developmentsystem that ensures optimum performanceof Pentek boards.





workstation, the 8267 is equipped with thelatest Intel i7 processor, DDR3 SDRAM anda high-performance single-board computer.These features accelerate application codedevelopment and provide unhindered accessto the high-bandwidth data available withCobalt, Onyx and Flexor analog and digitalinterfaces. The 8267 can be configured with64-bit Windows or Linux operating systems.

New!

New!

New!

New!

New!

Features■ 9-slot, 4U 19-inch rackmount,

12-inch deep chassis whichhouses 3U VPX boards

■ 64-bit Windows® 7 Professionalor Linux® workstation

■ Intel® CoreTM i7 3.6 GHzprocessor

■ 8 GB DDR3 SDRAM

■ ReadyFlow® drivers andboard support librariesinstalled

■ Out-of-the-box ready-to-runexamples

The 8267 uses a 19” 4U rackmount chas-sis that is 12” deep. Nine VPX slots provideample space for an SBC, a switch card andmultiple Pentek boards. Enhanced forced-air ventilation assures adequate cooling forall boards and dual 250-W power suppliesgurantee more than adequate power for allinstalled boards. Mounting provisions fortwo 3.5 in. drives with front-accessible traysallow for easy removable storage. Front-panelaccess to USB, display, Ethernet and RS-232ports simplifies development; an optional reartransition module supplements the front-panel connections with SATA, audio, a secondvideo interface, and additional USB ports.

ConfigurationAll 8267 systems come with software and

hardware installed and tested. Up to sevenPentek boards in the 8267 can be supported.Please contact Pentek to configure a systemthat matches your specific requirements.

OptionsAvailable options include high-end multi-

core CPUs and extended memory support.


Professional or LinuxProcessor: Intel Core i7 processorClock Speed: 3.6 GHzSDRAM: 8 GB standard, 16 GB optionalDimensions: 4U Chassis, 19" W x 12" D x 7" HWeight: 35 lb, approx.Operating Temp: 0° to +50° CStorage Temp: –40° to +85° CRelative Humidity: 5 to 95%, non-condensingPower Requirements: 100 to 240 VAC,

50 to 60 Hz, 1000 W max.


8267 3U VPX DevelopmentSystem for Cobalt, Onyxand Flexor Boards

Options:



-101 Upgrade to 16 GBDDR3 SDRAM

The addition of third-party VPXboards may affect system per-formance. Please consult withus before doing so.

www.pentek.com

Customer InformationPlacing an Order

When placing a purchase order for Pentek products,please provide the model number and product description.You may place your orders by letter, telephone, email or fax;you should confirm a verbal order by mail, email or fax.

All orders should specify a purchase order number, bill-toand ship-to address, method of shipment, and a contactname and telephone number.

U.S. orders should be made out to Pentek, Inc. and maybe placed directly at our office address, or c/o our autho-rized sales representative in your area.

International orders may be placed with us, or with ourauthorized distributor in your country. They have pricingand availability information and they will be pleased toassist you.

Prices and Price QuotationsAll prices are F.O.B. factory in U.S. dollars. Shipping

charges and applicable import, federal, state or local taxes,are paid by the purchaser.

We’re glad to respond to your request for price quotationjust contact the corporate office, or your local representative.Price and delivery quotations are valid for 30 days, unlessotherwise stated.

Quantity discounts for large orders are available and willbe included in our price quotation, if applicable.

TermsTerms are Net 30 days for accounts with established

credit; until credit is established, we require prepayment, orwill ship C.O.D.

ShippingFor new orders, we normally ship UPS ground with ship-

ping charges prepaid and added to our invoice. If you are ina hurry, we will ship UPS Red, UPS Blue, FedEx, or the carrierof your choice, as you request.

Order Cancellation and ReturnsAll orders placed with Pentek are considered binding and

are subject to cancellation charges. Hardware products maybe returned within 30 days after receipt, subject to a restock-ing charge. Before returning a product, please call CustomerService to obtain a Return Material Authorization (RMA)number. Software purchases are final and we cannot allowreturns.

WarrantyPentek warrants its products to conform to published

specifications and to be free from defects in materials andworkmanship for a period of one year from the date of deliv-ery, when used under normal operating conditions andwithin the service conditions for which they were furnished.

The obligation of Pentek arising from a warranty claimshall be limited to repairing or, optionally, replacing withoutcharge any product which proves to be defective within theterm and scope of the warranty.

Pentek must be notified of the defect or nonconformitywithin the warranty period. The affected product must bereturned with shipping charges and insurance prepaid.Pentek will pay shipping charges for the return of product tobuyer, except for products returned from outside the USA.

Limitations of WarrantyThis warranty does not apply to products which have

been repaired or altered by anyone other than Pentek or itsauthorized representatives.

The warranty does not extend to products that have beendamaged by misuse, neglect, improper installation, unautho-rized modification, or extreme environmental conditions,that fall outside of the scope of the product’s environmentalspecifications.

Due to the normal, finite write-cycle limits of Solid StateDrives (SSDs), Pentek shall not be liable for warranty cover-age of SSDs caused by wear-related issues that arise as anSSD reaches its write-cycle limit.

Pentek specifically disclaims merchantability or fitness fora particular purpose. Pentek shall not be held liable for inci-dental or consequential damages arising from the sale, use,or installation of any Pentek product. Regardless of circum-stances, Pentek’s liability under this warranty shall not exceedthe purchase price of the product.

Extended WarrantyYou may purchase an extended warranty on our board-

level products for a fee of 1% of the list price per month ofcoverage, or 10% of the list price per year of coverage.

All Pentek software products (excluding 3rd-party prod-ucts) include free maintenance and free upgrades for oneyear. Extended software maintenance is available for one,two, and three years, starting after the first year.

Service and RepairYou must obtain a Return Material Authorization (RMA)

before returning any product to Pentek for service or repair.RMA requests must be submitted online at:

Return Material Authorization FormAfter the form is completed in its entirety and submitted,

Pentek shall email you a receipt and start processing yourrequest. Once your request has been approved, Pentek shalle-mail you an RMA number, shipping instructions, and aquotation if the product is out of warranty.

Carefully package the product in its original packaging, ifit is still available, and ship it to Pentek prepaid (if within theUS) or free domicile DDP (if outside the US). Pentek shall notbe responsible for loss or damage in shipment to Pentek, soyou are strongly encouraged to insure the shipment for itsfull replacement value.

When the work is completed, we will return the productto you along with a statement of work performed.

Customer Service phone: 201-818-5900 • fax: 201-818-5697• email: [email protected]

http://www.pentek.com/contact/RMA_Form.cfm

pentek analog & digital i/o catalog

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