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PEX 8619BA Base Board RDK Hardware Reference Manual

Version 1.0

April 2009

Website: www.plxtech.com

Technical Support: www.plxtech.com/support

Copyright © 2009 by PLX Technology, Inc. All Rights Reserved – Version 1.0 April 15, 2009

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PEX 8619BA Base Board RDK Hardware Reference Manual – Version 1.0 Copyright © 2009 by PLX Technology, Inc. All rights reserved 2

© 2009 PLX Technology, Inc. All rights reserved.

PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.

PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.

Other brands and names are the property of their respective owners.

Document Number: PEX8619BA-Base Board RDK-HRM-1.0

April 15, 2009

PEX 8619BA Base Board RDK Hardware Reference Manual – Version 1.0 Copyright © 2009 by PLX Technology, Inc. All rights reserved i

PREFACE

NOTICE This document contains PLX Confidential and Proprietary information. The contents of this document may not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.

PLX provides the information and data included in this document for your benefit, but it is not possible to entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this information. The information in this document is subject to change without notice. Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental, or consequential damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.

ABOUT THIS MANUAL This document describes the PLX PEX 8619BA-Base Board RDK, a Rapid Development Kit, from a hardware perspective. It contains a description of all major functional circuit blocks on the board and also is a reference for the creation of software for this product. This manual also includes complete schematics and bill of materials.

REVISION HISTORY

Date Version Comments

April 2009 1.0 Initial Release

PEX 8619BA Base Board RDK Hardware Reference Manual – Version 1.0 Copyright © 2009 by PLX Technology, Inc. All rights reserved ii

CONTENTS NOTICE ......................................................................................................................................................................... i ABOUT THIS MANUAL ..................................................................................................................................................... i

REVISION HISTORY .................................................................................................................................................... i 1. General Information ........................................................................................................................................... 1

1.1 PEX 8619 Features ................................................................................................................................... 1 1.2 PEX 8619BA-BB RDK Features ................................................................................................................ 3

2. System Architecture ........................................................................................................................................... 4 3. Hardware Architecture ....................................................................................................................................... 5

3.1 PEX 8619 ................................................................................................................................................... 5 3.2 PCI Express Interfaces .............................................................................................................................. 5

3.2.1 RDK Configuration Modules and Their Receptacles ......................................................................... 5 3.2.2 PCI Express Lane 0 to Lane 3 ........................................................................................................... 6 3.2.3 PCI Express Lane 4 to Lane 7 ........................................................................................................... 6 3.2.4 PCI Express Lane 8 to Lane 11 ......................................................................................................... 7 3.2.5 PCI Express lane 12 to lane 15 ......................................................................................................... 8

3.3 Reference Clock Circuits ........................................................................................................................... 8 3.4 Reset Circuits ............................................................................................................................................ 9 3.5 Serial Hot-Plug (SHP) Controller Circuits ................................................................................................ 10 3.6 Serial EEPROM ....................................................................................................................................... 11 3.7 I2C Interface ............................................................................................................................................. 11 3.8 Power Distribution Circuits ....................................................................................................................... 11 3.9 FPGA Interface ........................................................................................................................................ 12 3.10 LED and 7-Segment Displays ................................................................................................................. 13

3.10.1 LED Indicators ................................................................................................................................. 13 3.10.2 7-Segment Displays ......................................................................................................................... 14

3.11 GPIO Pins ................................................................................................................................................ 15 3.12 Reserved Pins ......................................................................................................................................... 15

4. On-Board Connectors, Switches, and Jumpers ............................................................................................... 16 4.1 DIP Switches ........................................................................................................................................... 16

4.1.1 Dip Switch Group 1 .......................................................................................................................... 16 4.1.2 Dip Switch Group 2 .......................................................................................................................... 17 4.1.3 Dip Switch Group 3 .......................................................................................................................... 19

4.2 Push-Button Switches .............................................................................................................................. 20 4.2.1 Manual Reset# (S1) ......................................................................................................................... 20 4.2.2 FPGA Manual Reset# (S2) .............................................................................................................. 20 4.2.3 Serial Hot-Plug Controller Attention Button (S3) ............................................................................. 21

4.3 Connectors and Headers ......................................................................................................................... 21 4.3.1 ATX Peripheral Power Connectors (J1-J4 & J7-J8) ........................................................................ 21 4.3.2 x4 PCI Express External Cable Connectors (J5 & J6) .................................................................... 21 4.3.3 ATX Main Power Connector (J9) ..................................................................................................... 22 4.3.4 ATX +12V Power Connector(J10) ................................................................................................... 22 4.3.5 Xilinx JTAG Connector (J12) ........................................................................................................... 22 4.3.6 Xilinx Mode Setting Header (J13) .................................................................................................... 23 4.3.7 PEX 8619 JTAG Header (JP3) ........................................................................................................ 23 4.3.8 SMBus Header (JP5) ....................................................................................................................... 23 4.3.9 PCI Express x8 Midbus Probe Footprint (JP6) ................................................................................ 23 4.3.10 PEX 8619 I2C Port (JP8) ................................................................................................................. 24 4.3.11 Debug Signal Header (JP9 & JP11) ................................................................................................ 24 4.3.12 Debug Input Header (JP10) ............................................................................................................. 26 4.3.13 Reference Clock Header (JP100) .................................................................................................... 26

5. RDK Port Configurations .................................................................................................................................. 27 6. Bill of Materials/ Schematics ............................................................................................................................ 33

PEX 8619BA Base Board RDK Hardware Reference Manual – Version 1.0 Copyright © 2009 by PLX Technology, Inc. All rights reserved iii

FIGURES Figure 1. PEX 8619BA Base Board RDK Front View ................................................................................................ 2 Figure 2. Connecting The RDK to a PC with x1 or x4 link ......................................................................................... 4 Figure 3. Connecting the RDK to a PC with x8 link ................................................................................................... 4 Figure 4. Lanes 0-3 Hardware Connections on the RDK .......................................................................................... 6 Figure 5. Lanes 4-7 Hardware Connections on the RDK .......................................................................................... 7 Figure 6. Lanes 8-11 Hardware Connections on the RDK ........................................................................................ 7 Figure 7. Lanes 12 – 15 Hardware Connections on the RDK ................................................................................... 8 Figure 8. RDK Reference Clock Circuits ................................................................................................................... 9 Figure 9. RDK Reset Circuits .................................................................................................................................... 9 Figure 10. SERIAL HOT-PLUG Circuits .................................................................................................................. 10 Figure 11. RDK ATX Power Connectors ................................................................................................................. 11 Figure 12. RDK Power Distribution Circuits ............................................................................................................ 12 Figure 13. FPGA Interface on RDK ......................................................................................................................... 13 Figure 14. RDK Dip Switch Groups ......................................................................................................................... 16 Figure 15. Group1 of Switches ................................................................................................................................ 16 Figure 16. Group 2 of Dipswitches .......................................................................................................................... 17 Figure 17. Group 3 of Dip Switches ......................................................................................................................... 19 Figure 18. x1 upstream and 15x1 downstream (PCFG=0000) ............................................................................... 27 Figure 19. x4 upstream 12x1 downstream (PCFG=0001) ...................................................................................... 28 Figure 20. x4 upstream, 1x4 and 8x1 downstream (PCFG=0010) .......................................................................... 29 Figure 21. x4 upstream, 2x4 and 4x1 downstream (PCFG=0011) .......................................................................... 30 Figure 22. x8 upstream, 8x1 downstream (PCFG=0101) ....................................................................................... 31 Figure 23. x8 upstream, 1x4 and 4x1 downstream (PCFG=0110) .......................................................................... 32

TABLES Table 1. Port Configurations Supported by the RDK ................................................................................................. 5 Table 2. RDK LED Indicator descriptions ................................................................................................................ 13 Table 3. RDK 7-Segment Display Functions ........................................................................................................... 14 Table 4. Strap_Reserved Pin Connections ............................................................................................................. 15 Table 5. Functional Description of Group 1 Dip Switches ....................................................................................... 17 Table 6. Functional Description of Group 2 Dip Switches ....................................................................................... 18 Table 7. Port Configurations use Dipswitch SW2 .................................................................................................... 19 Table 8. Functional Descriptions of SW3, SW6, SW13-SW14 ............................................................................... 20 Table 9. Signal Names of J1-J4 & J7-J8 ................................................................................................................. 21 Table 10. Signal Names of J5 and J6 ...................................................................................................................... 21 Table 11. Signal Names of J9 ................................................................................................................................. 22 Table 12. Signal Names of J10 ............................................................................................................................... 22 Table 13. Signal Names of J12 ............................................................................................................................... 22 Table 14. Signal Names of J13 ............................................................................................................................... 23 Table 15. Pin assignment of JP3 ............................................................................................................................. 23 Table 16. Signal Names of JP5 ............................................................................................................................... 23 Table 17. Signal Names of JP6 ............................................................................................................................... 23 Table 18. Pin assignment of JP8 ............................................................................................................................. 24 Table 19. Pin assignment of JP9 & JP11 ................................................................................................................ 24 Table 20. Pin assignment of JP10 ........................................................................................................................... 26 Table 21. Pin assignment of JP100 ......................................................................................................................... 26


1. General Information The PLX PEX 8619BA Base Board RDK is a Rapid Development Kit based on the PEX 8619, a 16-lane, 16-port PCI Express switch based in the PCI Express Specification rev 2.0 with SerDes capable of running at 5 GT/s. The PEX 8619BA Base Board RDK provides a complete hardware and software development platform that facilitates getting designs up and running quickly, lowering risk and reducing time-to-market. This RDK consists a base board containing three hardware configuration Modules, a PCI Express cable adapter board that plugs into the host system, and up to two x4 PCI Express cables that used to connect the RDK to the cable adapter. This manual primarily focuses on the PEX 8619BA Base Board RDK, and its use with other parts to demonstrate the various functions of PEX 8619 chip. Figure 1 provides a top view (component side) of the PEX 8619BA Base Board RDK.

1.1 PEX 8619 Features • 16-lane, 16-port PCI Express Gen 2 switch with integrated on-chip SerDes • 160 GT/s aggregate bandwidth (5.0 GT/s/Lane x 16 Lanes x 2 (full duplex)) • 19mm2 324-ball Plastic Ball Grid Array (PBGA) package • Typical Power – 2.2W • Cut-Thru packet latency of less than 160ns • Low power SerDes (under 90mW per lane) • Fully non-blocking switch architecture • Flexible port configuration

o 16 flexible and configurable ports (x1,x4 or x8), x2 is also supported • Flexible device configuration

o Configurable via serial EEPROM, I2C, hardware strapping, or by the host • Maximum packet payload size of 2,048 bytes • Designate any Port as the Upstream Port (Port 0 is recommended) • Dynamic Buffer Pool Architecture • Read Pacing (allows user to throttle Read requests from Downstream Ports to allow for more efficient

performance) • Dual-Casting (enhances performance by sending date from one ingress port to two egress ports) • Integrated Direct Memory Access (DMA) engine • Dynamic speed (2.5 GT/s or 5.0 GT/s) negotiation • Dynamic link-width negotiation (automatically negotiates down to optimal link-width based on traffic

density) • Lane and polarity reversal • Non-Transparent Bridging support

o Enables Dual-Host, Host-Failover applications • Conventional PCI-compatible Link Power Management states – L0, L0s, L1, L2/L3 Ready, and L3 (with

Vaux not supported) • Conventional PCI-compatible Device Power Management states – D0 and D3hot • Active State Power Management • Spread-Spectrum Clock Isolation (Dual-clock Domain) • Quality of Service (QoS)

o Two Virtual Channels (VC0 and VC1) and Eight Traffic classes (TC) o Weighted Round-Robin Port and Virtual Channel arbitration

• Reliability, Availability, Serviceability (RAS) features o All ports are Hot-Plug capable through I2C (Serial Hot-Plug Controller on every port) o Advanced Error Reporting capability o Performance Monitoring

Per-Port Payload and Header Counters Per-traffic type (write, Read, Completion) Counters

o JTAG AC/DC boundary scan o 16 Lane status balls (PEX_LANE_GOOD[15:0]#) o 32 GPIO balls (GPIO[31:0]

Figure 1. PEX 8619BA Base Board RDK Front View



• INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) ball support

• Compliant to the following specifications: o PCI Local Bus Specification, Revision 3.0 (PCI r3.0) o PCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2) o PCI to PCI Bridge Architecture Specification, Revision 1.2 (PCI-to-PCI Bridge r1.2) o PCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1) o PCI Express Base Specification, Revision 2.0 (PCI Express Base r2.0) o IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture,

1990 (IEEE Standard 1149.1-1990) o IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture o IEEE Standard 1149.1-1994, Specifications for Vendor-Specific Extensions o IEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan Architecture

Extensions (IEEE Standard 1149.6-2003) o The I2C-Bus Specification, Version 2.1 (I2C Bus v2.1)

1.2 PEX 8619BA-BB RDK Features • PLX PEX 8619 PCI Express switch in a 324-ball Plastic BGA package • Based on PCI Express Card Electromechanical (CEM) Specification 2.0 and PCI Express External

Cabling Specification 1.0 • Supports up to 6 different port configurations with x4 PCI Express cable connection(s) to the upstream

PC • Non-Transparent Bridging support • One x8 Gen 2 Midbus probe footprint for upper 8 lanes of PCI Express signal probing for the chip • PCI Express RefClk Circuits supports Spread-Spectrum Clock Isolation • Serial Hot-Plug circuits on one PCI Express card edge connector • In system programmable Serial EEPROM (2.5V) • A standard 2x2 header provides the I2C interface to an I2C master • DIP switches for port configuration, upstream port or NT port select and I2C address settings • Manual push-button PERST# capability • Up to sixteen dual color LEDs for visual inspection of link speed and status • 7-Segment displays for port numbers and link width • Up to 3-digit display for junction temperature of PEX 8619 • Voltage level monitoring circuit for 1.0V and 2.5V power to the PEX 8619

2. System Architecture The PEX 8619BA-Base Board RDK is a 21” x 10” bench top board for silicon evaluation and design reference for the PEX 8619 PCI Express Gen 2 switch. This RDK consists of three main hardware components: the base board, the PCI Express External Cable Adapter and PCI Express Cable assembly. Figure 1 represents the placement of major component blocks on the RDK base board. Figure 2 and Figure 3 provide diagrams of the RDK being used in a PC. The RDK provides up to 15 PCI Express slots for add-in cards and visual indicators for port, link status and speed information. The RDK is designed to be powered up with an ATX power supply.

Figure 2. Connecting The RDK to a PC with x1 or x4 link

Figure 3. Connecting the RDK to a PC with x8 link



3. Hardware Architecture The PEX 8619BA Base Board RDK is designed around the PEX 8619, a 16-port, 16-lane Gen 2 switch, and based on the PCI Express CEM 2.0 Specification. The RDK offers PCI Express interfaces to 15 PCI Express Edge Card Connectors, two x4 PCI Express External cable connectors, and three configuration modules. The RDK is designed to support 6 different port configurations (see Table 1 for details) and to connect to its upstream PC through its PCI Express Cable Connectors. The RDK relies on the PC connected to its PCI Express Cable Connector J5 to obtain it primary PCI Express reference clock and reset to support the RDK normal functions. Also, the RDK provides visual indications for power, link speed, port status, port number, and link width.

3.1 PEX 8619 The PEX 8619 is a 16-lane, 16-port PCI Express Gen 2 (5.0GT/s) switch. It is in 19mmx19mm package and it. It supports 9 different types of port configurations. Each with any port in the PEX 8619 can be designated as the upstream port or NT port. The PEX 8619 supports two clock domains which allows the support of Spread -Spectrum Clocking (SSC) isolation. The PEX 8519 also provides 16 lane status drivers and 32 GPIOs

3.2 PCI Express Interfaces The RDK provides 15 PCI Express connectors and two x4 PCI Express External Cable Connectors for PCI Express connections of PEX 8619. The RDK supports 6 different port configurations of PEX 8619. With the correct port configuration STRAP pin settings and the right Configuration Modules are installed, the RDK can demonstrate up to 16 ports and a up to x8 link upstream connection PCI Express Gen 2 switch. Table 1 shows all port configurations supported by the RDK while sections 3.2.1 to 3.2.5 describe the Configuration Modules and hardware configurations of grouped of each four PCI Express lanes in details.

Table 1. Port Configurations Supported by the RDK

Strap pin Settings STRAP_PORTCFG[3:0]

Port Configurations Configuration Modules Used *

0000 x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1 0108 at U74;0108 at U75; and 0108 at U76

0001 x4x1x1x1x1x1x1x1x1x1x1x1x1 0107 at U74;0108 at U75; and 0108 at U76

0010 x4x4x1x1x1x1x1x1x1x1 0107 at U74;0108 at U75; and 0107 at U76

0011 x4x4x41x1x1x1 0107 at U74;0107 at U75; and 0107 at U76

0101 x8x1x1x1x1x1x1x1x1 0107 at U74;0109 at U75; and 0108 at U76

0110 x8x41x1x1x1 0107 at U74;0109 at U75; and 0107 at U76

Note: * Three Configuration Modules may use for the RDK. They are “configuration Module 0107-0109”; U74, U75 and U76 are receptacles on the RDK for Configuration Modules to be installed

3.2.1 RDK Configuration Modules and Their Receptacles Each Configuration Module is a plug of a 200-pin board-to-board Mezzanine Connector assembled on a PCB. For the RDK, it is used to connect x4 link of PCI Express signals from PEX 8619 to one particular hardware connections. Only three Configuration Modules may be used on the PEX 8619BA base board RDK. These modules are labeled on their PCB silk screen as:

• Configuration Module 0107 • Configuration Module 0108 • Configuration Module 0109

On the RDK side, three receptacles of same Mezzanine Connectors are placed at U74, U75 and U76 where the Configuration Modules can be manually plugged in to complete the RDK PCI Express hardware configurations.

3.2.2 PCI Express Lane 0 to Lane 3 PCI Express lanes 0 - 3 of PEX 8619 are routed to the receptacle U74 as shown in Figure 4. When Configuration Module 0108 is plugged into U74 at Case (a), lanes 0-3 will be separately connected with a single line going to the following: PCI Express cable connector J5, PCI Express SLOT 1, PCI Express SLOT 2 and PCI Express SLOT 3. This results in x1 links to form port 0, 4, 6, and 8. When Configuration Module 0107 is plugged into U74 at Case (b), all four lanes will be connected to x4 PCI Express cable connector J5 to form a x4 link at port 0. Note that the PCIe signals to PCIe Cable Connector J5 can be an independent x4 port or the lower lanes of a x8 port.

x16

PCI E

xpre

ss C

onne

ctor

s

Port 0 x1link to upstream

SLT3 SL2 SLT1

4x PCIeCable

ConnectorJ5

Configuration Module0108

Lane 0Lane 1

Lane 2

Lane 3

Port 8 Port 6 Port 4

Lane 0-3

x16

PCI E

xpre

ss C

onne

ctor

s

Port 0 x4 link or lower 4 lanes of x8 link to upstream

SLT3 SL2 SLT1


Lane 0-3

Lane 0-3

4x PCIeCable

ConnectorJ5

U74U74

PEX 8619(U100)

Lane 3-0

Lane 8-11

Lane 4-7

Lane

12-

15

A1A1

PEX 8619(U100)

Lane 3-0

Lane 8-11

Lane 4-7

Lane

12-

15

(a) (b)

Figure 4. Lanes 0-3 Hardware Connections on the RDK

3.2.3 PCI Express Lane 4 to Lane 7 PCI Express lanes 4-7 of PEX 8619 are routed to the receptacle U75 as shown in Figure 5. When Configuration Module 0108 is plugged into U75 at Case (a), lanes 4-7 will be separately connected to PCI Express SLOT 4 to SLOT 7 with x1 link each to form ports 2, 10, 12, and 14. When Configuration Module 0107 is plugged into U75 at Case (b), four lanes will be connected to SLOT 4 to form a x4 link (port 4). When Configuration Module 0109 is plugged into U75 lane 4-7 will be connected to PCI Express cable connector J6 to form the upper four lanes of port 0 when port 0 is configured as a x8 port.



3.2.4 PCI Express Lane 8 to Lane 11 PCI Express lanes 8-11 of PEX 8619 are routed to the receptacle U76 as shown in Figure 6. When Configuration Module 0108 is plugged into U76 at Case (a), lanes 8-11 will be separately connected to PCI Express SLOT 8 to SLOT 11 with x1 link each to form ports 1, 5, 7, and 9. When Configuration Module 0107 is plugged into U76 at Case (b), four lanes will be connected to SLOT 8 to form a x4 link (port 1).

x16

PCI E

xpre

ss C

onne

ctor

s

x16

PCI E

xpre

ss C

onne

ctor

s

Lane 4-7

Lane

12-

15 Lane 4-7

Lane

12-

15



3.2.5 PCI Express lane 12 to lane 15 PCI Express lanes 12-15 of PEX 8619 are directly routed to PCI Express SLOT 12 to SLOT 15 with x1 link each to form ports 3, 11, 13 and 15, as shown in Figure 7, and a Configuration Module is not required.

Lane 15

Lane 13Lane 14


Lane 12

x16

PC

I Exp

ress

Con

nect

ors

SLT15 SLT14 SLT13

Port 15Port 13

Port 11

SLT12

A1

Lane 3-0

PEX 8619(U100)

Port 3

Lane 4-7

Lane

12-

15

Lane 8-11

Figure 7. Lanes 12 – 15 Hardware Connections on the RDK

3.3 Reference Clock Circuits The RDK reference clock circuits contain one crystal-to HCSL clock generator ( U108) from On Semiconductor (NB3N5573), two one-to-four differential clock fan out buffer (U28 and U61) from SpectraLinear (CY28400-2), two 1-to-10 differential clock drivers (U113-U114) from On Semiconductor (MC100LVEP111), AC coupling capacitors, and resistors for source terminations and voltage dividers. The clock circuits are designed to perform two major clock functions: reference clock fan out and Spread-Spectrum Clock Isolation. Refer to Figure 8, the PCI Express clock (CREFCLKp and CREFCLKn) from x4 PCI Express External Cable Connector J5 feeds into 1-to-4 fan out buffer U28. The outputs from U28 support the primary REFCLK of the PEX 8619 and connect to the inputs of clock drivers U113 and U114. The Constant frequency output from the clock generator (U108) is connected to a 1-to-4 fan out buffer U61. The outputs from U61 support the input to CFC_REFCK on the PEX 8619 as well as inputs to U113 and U114. When Spread Spectrum Clocking Crossing is enabled, the PEX 8619 can be made part of two clock domains. Port 0 is part of the SSC domain while all on-board PCI Express SLOT 1 to SLOT 15 are part of the constant frequency domain. Add-in cards connected to SLOT1 – SLOT15 will operate in a constant frequency clock. The SSC isolation feature can be enabled with a pull-down resistor on STRAP_SSC_ISO_ENABLE# pin. On the RDK, this can be done in Dipswitch SW6 position 1 set to ‘ON’. This feature is disabled on the RDK by default.

MC100LVEP111Pair 0

Pair 1

Pair 2

Pair 3

Pair 4

Pair 5

CY28400-2 Pair 1

Pair 2

Pair 5

NB3N55732

U108

U61

Pair 1

Pair 2

Pair 5

Source Termination

Source Termination

Source Termination

U28

CY28400-2

From 4x PCI Express Cable

Connector J5

PEX 8619

C

CFC_REFCK

REFCK

C

C

C

C

U113

Pair 6

Pair 7

Pair 8

Pair 9

MC100LVEP111Pair 0

Pair 1

Pair 2

Pair 3

Pair 4

Pair 5

U114

Pair 6

Pair 7

Pair 8

Pair 9

Source Termination

Source Termination

Source Termination

Voltage Devider

Voltage Devider

Pos1/SW6

0

1

SEL

Voltage Devider

Voltage Devider

0

1

SEL

Source Termination

Source Termination

Source Termination

Source Termination

Source Termination

Source Termination

Source Termination

Source Termination

Source Termination

Source Termination

Source Termination

Source Termination

Source Termination

Source Termination

Source Termination

Source Termination

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

Voltage Devider

Voltage Devider

Voltage Devider

Voltage DeviderVoltage Devider

Voltage Devider

SLOT 1

SLOT 2

SLOT 3

SLOT 4

SLOT 5

Voltage Devider

Voltage Devider


Voltage Devider

SLOT 6

SLOT 7

SLOT 8

SLOT 9

SLOT 10

Voltage Devider

Voltage Devider


Voltage Devider

SLOT 11

SLOT 12

SLOT 13

SLOT 14

SLOT 15

JP100 Refclk header for Midbus probe

SSC_ISO_EN_n

Figure 8. RDK Reference Clock Circuits

3.4 Reset Circuits Refer to Figure 9, the RDK reset circuits include two National NC7S08 2-input AND gate (U17&U21), two Maxim MAX6420 reset controllers (U18 and U20), one Xilinx FPGA (U115), a Serial Hot-Plug controller, momentary switches (S1 and S3), resistors and capacitors.

Figure 9. RDK Reset Circuits


The Reset Circuits contains two independent circuits: (a) the circuits reset the FPGA; (b) the circuits reset PEX 8619 and sends resets to 15 PCI Express connectors. The first one detect the power good signal, PS_PWR_GOOD, from the ATX 24-pin Main Power Connector and reset from momentary switch S3 to generate reset, FPGA_RESET, to the FPGA U115. The second detect the reset input, CPERST_n from the PCI Express Cable Connector J5 and the reset from momentary switch S1 input them to the FPGA that fans out the resets, PERST_n_SL[15:9, 7:1] , to 14 PCI Express slots, PEX_PERST_n to reset the PEX 8619, and PERST_n_SL8 to reset the PIC Express SLOT 8 through the Serial Hot-Plug Controller (see Figure 9 an Figure 10 for details)

3.5 Serial Hot-Plug (SHP) Controller Circuits With external IO expenders and Hot-Plug controllers, PEX 8619 supports up to 16 PCI Express Serial Hot-Plug ports/ SLOTs. The RDK implements a serial Hot-Plug controller circuitry to PCI Express SLOT 8 for the SHP function demonstration. By default, the serial Hot-Plug circuit is enabled.

PEX 8619I2C_SDA1

I2C_SCL1

SHPC_INT#

16 IO expenderMAX7311

(U71)

Interlock

Sltid[3:0]

GPIO

AD[2:0]

I2Cport1

PCI ExpressSLOT 8

VCC

System power supply

12V, 3.3V

VCC

VCCHot plug controller

FETs

Clken#

Atnled#

Pwrled#

Pwren

Perst#

Button#

Pwrflt#

Mrl#Prsnt#

Pwrgood

4

3

IO 13IO 1

IO 0

IO 2IO 3

IO 14

IO 4

IO 5

IO 6

IO[10:7]

IO 11IO 12

IO 15

VCC

VCC

(U100)

TP1

VCCVCC

SW10

RN54

D32

S2

VCC

D31

D28

VCC

TPS2311(U70)

P1/SW11

4 2-to-1 Mux

(U72)

SN74LVC157

Pwren

Perst#

Refclk From refclk buffer

Refclk

VCC

P2/SW11HP_SL8_CTL

SHPC_INT#

VCC

Figure 10. SERIAL HOT-PLUG Circuits

Refer to Figure 10 above, the serial Hot-Plug controller consists of MAX7311 I/O expander (U71), a TI TPS2311 dual hot–swap power controller (U70), a quad TI SN74LVC157 2-to-1 multiplexer (U72), two power MOSFET IRF7470 (Q1 and Q2), LEDs, manual switch, dipswitches and resistors. The PEX 8619 master I2C interface is designed for the specific control use of the serial Hot-Plug controller. The master I2C interface connected to the I/O expander and the interrupt output from the I/O expander connects to the SHP_INT# of the PEX 8619. When power is applied to the PEX 8619, the master I2C interface will scan the bus and attempts to detect the presence of the I/O expander. If an I/O expander is detected, the I2C master will program it as a “remote parallel Hot-Plug controller” and assign an available serial Hot-Plug port to the I/O expander. The IO expender then generates PWREN, CLKEN#, and PERST# outputs to control the power enable, clock enable# and reset# of the SHP SLOT8 and drives the LEDs at PWRLED#, ATNLED# and INTERLOCK# outputs. Also, it accepts BUTTON#, PWRFLT#, PWRGOOD, PRSNT# and MRL# inputs and generates interrupts to PEX 8619 for SHP status changes.

The RDK also provides dip switch (SW10) for setting the SLOTID [3:0]for the SLOT 8, and another dipswitch (SW11) to control the Serial Hot-Plug controller functions (enable/disable it), a test point for access the GPIO pin, and three pull-down resistors to set ADD [2:0] of the I/O expander U71. The LEDs D29 and D32 are 12V and 3.3V power indicators when power reaches PCI Express connector SLOT 82.


3.6 Serial EEPROM The PEX 8619BA Base Board RDK contains a blank surface mount Atmel AT25256A 32-Kbit serial EEPROM (U19) which is directly interfaced to the PEX 8619. When programmed correctly, the serial EEPROM can be used to change the default configuration and internal register values of the PEX 8619. A blank EEPROM results in the default register values set in the PEX 8619. Refer to the Software Development Kit (SDK) documentation for more information of how to program the serial EEPROM.

3.7 I2C Interface The PEX 8619 implements an I2C slave interface (I2C port 0), which allows an external I2C master to read and write device registers through an out-of-band mechanism. The PEX 8619 I2C interface is accessible via a 7-bit address, at data rates from 100 Kbps up to 3.4 Mbps. The RDK provides a 2x2, 0.1” pitch header (JP8), which interface to the PEX 8619’s I2C port. This allows using standard ribbon cable, and/or connecting to an I2C master such as Total Phase Aardvark I2C controller. (See 4.3.10 for pin assignment of JP8.)

3.8 Power Distribution Circuits To support the power of the RDK and the power of the PCI Express add-in cards plug into up to 15 PCI Express Edge Card connectors, an external ATX power supply is required. Refer to Figure 11, the RDK has 8 different ATX power connectors for power connections. These include one 24-pin ATX Main Power Connector J9, six 4-pin Peripheral Power Connectors J1- J4 & J7 - J8, and one 8-pin +12 V Power Connector.

SLO

T15

Figure 11. RDK ATX Power Connectors

The 24-pin ATX Power Connector should be connected to J9 and two or three 4-pin ATX Peripheral Power Connectors should be connected to either J1-J4 or J7-J8 depending on the power consumption requirements of the PCI Express add-in cards plugging into the PCI Express slots of the RDK. Note Some 600 watt power supplies in the market such as the NSpire model PSH600V-D 600 Watt power supply requires a minimum power consumption at +12V output to stabilize its +5V outputs. Without 0.8A loading at +12V outputs, the NSpire 600 watt power supply will drop its +5V output to near 3.9V-4.2V levels. The RDK only uses +5V output from the ATX power supply to generated lower DC voltages to support the PEX 8619 chip and the on board FPGA and other circuits. This particular power supply does not operate correctly unless there is enough loading on the +12V supply. An Nvidia Geforce 8800GT high power graphic card can be plugged into one of PCI Express slots on the RDK in order to provide enough loading on the +12V supply.


4-Pin ATX Peripheral Power

Connector J1-J4, J7-J8

U25V to 1V

adj. DC/DC converter

on/off#

U35V to 1V

adj. DC/DC converter

on/off#

U45V to

3.3VCC DC/DC

converter

On board3.3V Circuits

Dipswitch SW15 is used to select on

board power source or external power inputs

to the Sirius chips

BJ4 BJ3

BJ5 BJ6

BJ8

1.0VCC

2.5VCC

GND

GND

24-Pin ATX Main Power Connector

J9

15 PCI Express Connectors

BJ10 BJ9

1.0VCC_A

SLOT 1

5V

2.5V_A

PEX 8619

12V

12V_A

5V_A

12V_A3

3.3VCC1

U55V to 2.5V adj. DC/DC converter

R

on/off#

0

5V_A

3.3V

CC

3.3VCC

GND

GND

GND

12V_A1 0

GND

8-Pin ATX +12V Power Connector

J10

12V_A2 0

SLOT 2

SLOT 3

SLOT 4

SLOT 9

SLOT 10

SLOT 11

SLOT 12

SLOT 5

SLOT 6

SLOT 7

SLOT 8

SLOT 13

SLOT 14

SLOT 15

MOSFET

MOSFET

Serial HP Controller

U117Dual output step down regulator

1.2V

2.5V

Figure 12. RDK Power Distribution Circuits Refer to Figure 12, 15 PCI Express slots including the Serial Hot-Plug controlled SLOT 8 get 3.3 volt and 12 volt power from 24-pin ATX Main Power Connector, 4-pin ATX Peripheral Power Connectors and the +12V Power Connector. The RDK on board circuits and the PEX 8619 get their power from the +5V input from the ATX power supply. DC/DC converter U4 uses 5V input generates 3.3VCC1 to the on board circuit. The 3.3VCC1 further steps down by voltage regulator U117 to generate 2.5V and 1.2V for Xilinx FPGA (U115). Three dc/dc converters U2, U3 and U5 use 5V input to generate 1.0VCC, 1.0VCC_A and 2.5VCC for PEX 8619. Dip switch SW15 can be set to turn off these dc/dc converters for external power margin tests for PLX use only.

3.9 FPGA Interface The RDK contains a Xilinx Spartan-3 FPGA which is used to perform 6 major functions (see Figure 13 for details):

• Connects to GPIOs, lane and chip status and spare pins of PEX 8619 ( for PLX use only) • Controls the 7-segment displays for port numbers and link width for PCI Express Cable Connectors J5

and J6 and PCI Express connectors SLOT 1 to SLOT15 • Decodes lane status and converts them to link speed and status LED display • Communicates with the thermal sensor and displays the junction temperature of PEX 8619 in 4 digits • Connects to users defined Dipswitches • Fans out reset signals to PEX 8619 and PCI Express slots


M

14 PCIe Connectors

PEX 8619(U100)

8 Dipswitches SW13-14

Xilinx Spartan 3 FPGA

XC3S200-4FTG256C(U115)

connectes to GPIOs, Lane and chip status,

and spare Pins of PEX8618

Mictor Connectors (JP9 & 11)

Communicates with the thermal sensor and displays the junction temperature of PEX

8618

36 7-seg. displays

Temperature in 4 digits

MAX6658

2

Users’ defined Dipswitches

RESET and PERST circuits

14

From PCIe cable connector J5 or on board

momentary switch S12

Decodes lane status and converts to link speed and status

displays

5Gbps 2.5Gbps

Thermal DiodeControls the 7-segment

displays of Port# and link width of PCIe slots and cable

connectors of PEX 8618

Figure 13. FPGA Interface on RDK

3.10 LED and 7-Segment Displays The RDK provides 31 LEDs and forty 7-segment displays for power indicators, Hot-Plug output indicators, link speed/status, port numbers and link width of each port.

3.10.1 LED Indicators All LED indicators and their associated functions are described in the Table 2 below.

Table 2. RDK LED Indicator descriptions

Indicator Type Locations LED Functions

Power LEDs/green color

D1 On: 12V_A is applied to the RDK from the ATX power supply

D2 On: 5V_A is applied to the RDK from the ATX power supply

D3 On: 3.3VCC is applied to the RDK from the ATX power supply

D9 On: 3.3VCC1 from dc/dc converter U4

D4 On: 2.5VCC_A is applied to PEX 8619

D5 On: 2.5VCC is applied to PEX 8619

D6 Power LED for 1.0VCC_A (did not work)

D7 Power LED for 1.0VCC (did not work)



Indicator Type Locations LED Functions

Power LEDs/dual color: green and red

D8 Green LED on: 2.5VCC to PEX 8619 is within 10% range Red LED on: 2.5VCC to PEX 8619 is out of 10% range

D10 Green LED on: 1.0VCC to PEX 8619 is within 10% range Red LED on: 1.0VCC to PEX 8619 is out of 10% range

SERIAL HOT-PLUG (SHP) LEDs/green color

D28 On: SHP power LED output active at SLOT 8

D29 On: 12V is applied to PCI Express SLOT 8

D30 On: 3.3V is applied to PCI Express SLOT 8

D31 On: SHP Attention LED output active at SLOT 8

D32 On: SHP Interlock LED output active at SLOT 8

Port Link Status and Speed LEDs / Dual color: green and

yellow

D12 Green LED on: port 0 link up with GEN 2 speed (5Gbps) at connector J5 Yellow LED on: port 0 link up with GEN 1 speed (2.5Gbps) at connector J5 Both LED off: port 0 link down or no connected or no configured

D16 Same function as D12 for port 4 at SLOT1















3.10.2 7-Segment Displays The RDK has forty 7-segment displays. Thrity-four of them are used for port number and link width indicators of each PCI Express SLOTs, two are user defined 7-segment displays, and four of them are used for junction temperature display. (See Table 3 for details).

Table 3. RDK 7-Segment Display Functions

Location of Display 7-Segment Display Functions DS37 For port 0 at cable connector J5, When enabled, LED display is 0 DS39 Link Width of port0, LED display is 1, 4 or 8 depending on the port configuration DS33 Copy DS37 if cable connector J6 is used. Otherwise it would be off DS35 Copy DS39 if cable connector J6 is used. Otherwise it would be off DS2 For port 4 at SLOT1, When enabled, LED display is 4 DS6 Link Width of port 4, When enabled, LED display is 1 DS9 For port 6 at SLOT2, When enabled, LED display is 6

DS13 Link Width of port 6, When enabled, LED display is 1 DS1 For port 8 at SLOT3, When enabled, LED display is 8 DS5 Link Width of port 8, When enabled, LED display is 1


Location of Display 7-Segment Display Functions DS12 For port 2 at SLOT4, When enabled, LED display is 2 DS16 Link Width of port 2, LED display is 1 or 4 depending on the port configuration DS4 For port 10 at SLOT5, When enabled, LED display is A DS8 Link Width of port 10, When enabled, LED display is 1

DS11 For port 12 at SLOT6, When enabled, LED display is C DS15 Link Width of port 12, When enabled, LED display is 1 DS3 For port 14 at SLOT7, When enabled, LED display is E DS7 Link Width of port 14, When enabled, LED display is 1

DS26 For port 1 at SLOT8, When enabled, LED display is 1 DS30 Link Width of port 1, LED display is 1 or 4 depending on the port configuration DS18 For port 5 at SLOT9, When enabled, LED display is 5 DS22 Link Width of port 5, When enabled, LED display is 1 DS25 For port 7 at SLOT10, When enabled, LED display is 7 DS29 Link Width of port 7, When enabled, LED display is 1 DS17 For port 9 at SLOT11, When enabled, LED display is 9 DS21 Link Width of port 9, When enabled, LED display is 1 DS28 For port 3 at SLOT12, When enabled, LED display is 3 DS32 Link Width of port 3, When enabled, LED display is 1 DS20 For port 6 at SLOT13, When enabled, LED display is 6 DS24 Link Width of port 6, When enabled, LED display is 1 DS27 For port 13 at SLOT14, When enabled, LED display is 13 DS31 Link Width of port 13, When enabled, LED display is 1 DS19 For port 15 at SLOT15, When enabled, LED display is F DS23 Link Width of port 15, When enabled, LED display is 1

DS10 and DS14 Users’ defined 7-segment displays DS34, DS36, DS38,

DS40 Used to display junction temperature of PEX 8619BA in degree C

3.11 GPIO Pins The PEX 8619 has thirty-two GPIO pins. Depends on the TEST MODE pin settings, 16 of them, GPIO[15:0], can be configured to perform Serial Hot-Plug reset output functions (PERSTx#).

3.12 Reserved Pins The PEX 8619 has 2 STRAP_RESERVED pins. They are factory use only and should be set to know logic states. Table 4 shows the list of these reserved pins and their connections in the RDK.

Table 4. Strap_Reserved Pin Connections

Name Pin Location Connections on PEX 8619BA Base Board RDK STRAP_RESERVED16 D14 Pull-down with a 1K ohm resistor

STRAP_RESERVED17# F1 Pull-up with a 4.7K ohm resistor

4. On-Board Connectors, Switches, and Jumpers

4.1 DIP Switches The PEX 8619BA Base Board RDK contains eleven DIP switches for various functions. Refer to Figure 14; they can be divided into three groups. The Group1 contains three dip switches and is located at the lower left corner of the RDK, Group2 contains three dip switches and is located at the middle of right edge, and the last group contains five dip switches and is located at the lower right hand corner of the RDK

Figure 14. RDK Dip Switch Groups

4.1.1 Dip Switch Group 1 This group includes three dipswitches, SW10, SW11 and SW15. Figure 15 shows the default settings of these dipswitches and Table 5 describes the functions of each dipswitches

4. D

ebug

_Nor

mal

#3.

PLX

use

onl

y2.

PLX

use

onl

y1.

PLX

use

onl

y

2. H

P_S

L8_C

TL1.

MR

LI#_

S

4. S

LOT3

3. S

LOT2

2. S

LOT1

1. S

LOT0

Figure 15. Group1 of Switches


Table 5. Functional Description of Group 1 Dip Switches

Name Function Settings

SW10 Slot number of Serial Hot-Plug port PCIe connectro SPLT8

Default: on, on, on, on (0000)

4: SLOT 3 3: SLOT 2 2: SLOT 1 1: SLOT 0

SW11 Serial Hot-Plug Port input and control

2. HP_SL8_CTL : on: enable Serial Hot-Plug (SHP) control outputs—PWREN_S, PERST#_S and CLKEN#_S; off: bypass above SHP control ouputs

1. MRLI#_S: on: enable SHP MRL# input; off: disable it

Default: on,on (enable SHP functions at SLOT 8)

SW15 Debug function and dc/dc converter controls

4: Debug_normal_#: on : for normal operation; off: for debug us 3-1: for PLX use only

Default: on, off,off,off

4.1.2 Dip Switch Group 2 This group includes three dipswitches, SW4, SW5 and SW7. Figure 16 shows the default settings of these dipswitches and Table 6 describes the functions of each dipswitches

SW7

ON

SW5

ON

SW4

ON

1. TESTMODE32. TESTMODE23: TESTMODE14: TESTMODE0

1. NT_ENABLE_n2. DEBUG_SEL03: PROBE_MODE_n4: SERDES_MODE_EN_n

1. NT_UPSTR_PSEL32. NT_UPSTR_PSEL23: NT_UPSTR_PSEL14: NT_UPSTR_PSEL0

Figure 16. Group 2 of Dipswitches



Table 6. Functional Description of Group 2 Dip Switches


SW4 NT Upstream Port Selects NT_UPSTR_PSEL[3:0] Port # on,on,on,on 0 on,on,on,off 1 on,on,off,on 2 on,on,off,off 3 on,off,on,on 4 on,off,on,off 5 on,off,off,on 6 on,off,off,off 7 off,on,on,on 8 off,on,on,off 9 off,on,off,on 10 off,on,off,off 11 off,off,on,on 12 off,off,on,off 13 off,off,off,on 14 off,off,off,off 15

SW5 NT port and debug mode enables 1. NT_ENABLE_n : on: enable NT mode, off: disable NT mode, default disable NT mode 2. DEBUG_SEL0: for PLX use only 3: PROBE_MODE_n: for PLX use only 4. SERDES_MODE_EN_n: for PLX use only

Default: 1-4: off,off,off,off

SW7 Test Mode selects 1. TESTMODE3: for PLX use only 2: TESTMODE2: for PLX use only 3. TESTMODE1: for PLX use only 4: TESTMODE0: for PLX use only


4.1.3 Dip Switch Group 3 This group includes five dipswitches, SW2, SW3, SW6, SW13 and SW14. Figure 17 shows the default settings of these dipswitches. Table 7 and Table 8 describe the functions of them.

SW2

SW14

SW13

SW3

SW6

SW2

SW14

SW13

SW3

SW6

1. UPSTR_PSEL32. UPSTR_PSEL23: UPSTR_PSEL14: UPSTR_PSEL0

1. SSC_ISO_EN_n2. PP_PYPASS_n3: GEN1_n4: FAST_BRINGUP_n

1. PORT_CFG32. PORT_CFG23: PORT_CFG14: PORT_CFG0

1. UMODE72. UMODE63: UMODE54: UMODE4

1. UMODE32. UMODE23: UMODE14: UMODE0

Figure 17. Group 3 of Dip Switches

Table 7. Port Configurations use Dipswitch SW2

Dipswitch Settings for STRAP_PORTCFG[3:0]

Port Configurations

ON,ON,ON,ON (0000) x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1x1 ON,ON,ON,OFF (0001) x41x1x1x1x1x1x1x1x1x1x1x1 ON,ON,OFF,ON (0010) x4x41x1x1x1x1x1x1x1 ON,ON,OFF,OFF (0011) x4x4x41x1x1x1 ON, OFF,ON,OFF (0101) x8x1x1x1x1x1x1x1x1 ON,OFF,OFF,ON (0110) x8xx41x1x1x1



Table 8. Functional Descriptions of SW3, SW6, SW13-SW14


SW3 Upstream Port Selects UPSTR_PSEL[3:0] Port # on,on,on,on 0 on,on,on,off 1 on,on,off,on 2 on,on,off,off 3 on,off,on,on 4 on,off,on,off 5 on,off,off,on 6 on,off,off,off 7 off,on,on,on 8 off,on,on,off 9 off,on,off,on 10 off,on,off,off 11 off,off,on,on 12 off,off,on,off 13 off,off,off,on 14 off,off,off,off 15

SW6 Other Mode Selects 1. SSC_ISO_EN_n : on: enable the Spread Spectrum Clocking (SSC) crossing, off: disable it, default is disable SSC crossing function 2. PP_PYPASS_n: for PLX use only 3: GEN 1_N: for PLX use only 4. FAST_BRINGUP_n: for PLX use only


SW13 Users Define Mode Switches 1. UMODE3 2: UMODE2 3. UMODE1 4: UMODE0


SW14 Users Define Mode Switches 1. UMODE7 2: UMODE6 3. UMODE5 4: UMODE4


4.2 Push-Button Switches

4.2.1 Manual Reset# (S1) The RDK provides a manual switch (S1) for manual PERST# capability. Note that manual PERST# will only apply warm reset to the PEX 8619 as well as PCI Express SLOT 1 to SLOT 15.

4.2.2 FPGA Manual Reset# (S2) This momentary switch (S2) provides manual reset to the FPGA (U115) on the RDK.


4.2.3 Serial Hot-Plug Controller Attention Button (S3) The RDK provides a manual switch (S3) for attention button to the Serial Hot-Plug circuit. When pushed and released, the switch generates an active low pulse to the Attention Button Input to the IO Expender U71 which will generate interrupt signal, INT#, to the PEX 8619 for attention (see section 3.5 for details).

4.3 Connectors and Headers

4.3.1 ATX Peripheral Power Connectors (J1-J4 & J7-J8) The RDK has six ATX Peripheral Power Connectors.

Table 9. Signal Names of J1-J4 & J7-J8 Pin # Signal Name

1 12V 2 GND 3 GND 4 5V

4.3.2 x4 PCI Express External Cable Connectors (J5 & J6) The RDK has two x4 PCI Express External Cable Connectors.

Table 10. Signal Names of J5 and J6

Pin # Signal Name Pin # Signal Name A1 GND B1 GND

A2 PETp0 B2 PERp0

A3 PETn0 B3 PERn0

A4 GND B4 GND

A5 GND B5 PERp1

A6 PETp1 B6 PERn1

A7 PETn1 B7 GND

A8 GND B8 PERp2

A9 PETp2 B9 PERn2

A10 PETn2 B10 GND

A11 GND B11 PERp3

A12 PETp3 B12 PERn3

A13 PETn3 B13 GND

A14 GND B14 PWR

A15 CREFCLKp B15 PWR

A16 CREFCLKn B16 PWR_RTN

A17 GND B17 PWR_RTN

A18 SB_RTN B18 CWAKE#

A19 CPWRON B19 CPERST#


4.3.3 ATX Main Power Connector (J9) Table 11. Signal Names of J9

Pin # Signal Name Pin # Signal Name 1 +3.3VDC 13 +3.3VDC

2 +3.3VDC 14 -12VDC

3 COM 15 COM

4 +5VDC 16 PS_ON#

5 COM 17 COM

6 +5VDC 18 COM

7 COM 19 COM

8 PWR_OK 20 -5VDC

9 +5VSB 21 +5VDC

10 +12VDC 22 +5VDC

11 +12VDC 23 +5VDC

12 +3.3VDC 24 COM

4.3.4 ATX +12V Power Connector(J10) Table 12. Signal Names of J10

Pin # Signal Name Pin # Signal Name 1 COM 13 +12VDC

2 COM 14 +12VDC

3 COM 15 +12VDC

4 COM 16 +12VDC

4.3.5 Xilinx JTAG Connector (J12) Table 13. Signal Names of J12

Pin # Signal Name Pin # Signal Name 1 VREF to 2.5V 2 GND

3 SS_PROG_TMS 4 GND

5 SCLK_CCLK_TCK 6 GND

7 MISO_DONE_TDO 8 GND

9 MOSI_DIN_TDI 10 GND

11 NC 12 GND

13 NC_INIT_NC 14 DNG


4.3.6 Xilinx Mode Setting Header (J13) Table 14. Signal Names of J13

Pin # Signal Name Pin # Signal Name 1 GND 2 M0

3 GND 4 M1

5 GND 6 M2

4.3.7 PEX 8619 JTAG Header (JP3) The 2x5 header JP3 provides a direct connection to the PEX 8619 JTAG interface. The 10-pin connector is designed to allow a direct interface to 3rd party JTAG controllers, such as the Corelis USB-1149.1/E controller. The pin assignment for the JTAG header (JP3) is listed at Table 15.

Table 15. Pin assignment of JP3

Pin # Signal Name Pin # Signal Name 1 JTAG_TRST 2 GND

3 JTAG_TDI 4 GND

5 JTAG_TDO 6 GND

7 JTAG_TMS 8 GND

9 JTAG_TCK 10 GND

4.3.8 SMBus Header (JP5) This header is for PLX use only

Table 16. Signal Names of JP5

Pin # Signal Name Pin # Signal Name 1 SMBCLK 2 GND

3 SMBDATA 4 NC

4.3.9 PCI Express x8 Midbus Probe Footprint (JP6) Table 17. Signal Names of JP6

Pin # Signal Name Pin # Signal Name G1 GND

2 GND 1 C0p-Upstream

4 C0p-Downstream 3 C0n-Upstream

6 C0n-Downstream 5 GND







Pin # Signal Name Pin # Signal Name 18 C2n-Downstream 17 GND















48 C7n-Downstream 47

G2 GND

4.3.10 PEX 8619 I2C Port (JP8) Table 18. Pin assignment of JP8

Pin Number Signal Name 1 I2C_SCL0 2 GND 3 I2C_SDA0 4 NC

4.3.11 Debug Signal Header (JP9 & JP11) This is for PLX use only.

Table 19. Pin assignment of JP9 & JP11

Pin # Signal Name at JP9 Signal Name at JP11 1 - -

3 GND GND

5 - NC

7 GPIO16 DEBUG_SEL0

9 GPIO17 STRAP_UPCFG_TIMER_EN#

11 GPIO18 STRAP_SMBUS_EN#

13 GPIO19 STRAP_SPARE0#

15 GPIO20 UPSTRM_PSEL3

17 GPIO21 GPIO29

19 GPIO22 GPIO30


Pin # Signal Name at JP9 Signal Name at JP11 21 GPIO23 I2C_ADDR2

23 GPIO24 STRAP_SPARE5#

25 GPIO25 GPIO6

27 GND GPIO7

29 - GPIO8

31 - GPIO26

33 - GPIO27

35 - STRAP_NT_P2P_EN#

37 - GND

39 GND GND

40 GND GND

41 GND GND

42 GND GND

43 GND GND

2 - -

4 - -

6 - -

8 LN_GOOD_00_n GPIO0






20 LN_GOOD_06_n I2C_ADDR0

22 LN_GOOD_07_n I2C_ADDR1

24 LN_GOOD_08_n STRAP_SPARE1#









4.3.12 Debug Input Header (JP10) This is for PLX use only.

Table 20. Pin assignment of JP10

Pin # Signal Name Pin # Signal Name 1 GND 2 STRAP_SPARE1#

3 I2C_ADDR2 4 I2C_ADDR1

5 GPIO30 6 I2C_ADDR0

7 GPIO29 8 GND

9 UPSTRM_PSEL3 10 GPIO5

11 STRAP_SPARE0# 12 GPIO4

13 GND 14 GPIO3

15 STRAP_SMBUS_EN# 16 GPIO2

17 STRAP_UPCFG_TIMER_EN# 18 GPIO1

19 DEBUG_SEL0 20 GPIO0

4.3.13 Reference Clock Header (JP100) Table 21. Pin assignment of JP100

Pin Number Signal Name 1 LAI_Refclk_p 2 GND 3 LAI_Refclk_n

5. RDK Port Configurations

1.0VCC

2.5VCC

J9SLOT15

SLOT14

SLOT13

SLOT12

SLOT11

SLOT10

SLOT9

SLOT8

SLOT7

SLOT6

SLOT5

SLOT4

SLOT3

SLOT2

SLOT1

J1 J7J3 J8 J4J2

1

24

J5

4x P

CIE

ca

ble

conn

ecto

r

J6

4x P

CIE

ca

ble

conn

ecto

r

U10

0

PEX

8619

Xilin

x FP

GA

U11

5

Con

figur

atio

n M

odul

e


0108


SW15

SW11

S2SW

10O

NO

NO

N

JP9

JP10

S2

J13

JP5

1234

1

J12

1

SW

7

ON

SW5

ON

SW

4

ON

SW

2

ON

SW

14

ON

SW

13

ON

SW3

ON

SW

6

ON

JP8

1234

JP10

11JP

3

D1

12V

_AD

2 5

V_A

D29

12V

_SLT

_8_H

PD

30 3

.3V

CC

_SLT

_8_H

PD

32 In

terlo

ck_S

D31

ATN

LED

#_S

D28

PW

RLE

D#_

SD

3 3.

3VC

CD

9 3.

3VC

C1

JP6

GN

D

BJ9

BJ1

0

GN

D

BJ6

BJ5

BJ4 BJ3

GN

D

Mid

bus

Prob

e Fo

otpr

int

Mic

tor

Con

nect

ors

Deb

ug In

put

Hea

der

I2C

Por

t

JTA

G P

ort

2.5V

CC

1.0V

CC

_A

1.0V

CC

Port

#Po

rt #

Port

#

Link

Wid

th

Port

#

S1FP

GA

JTA

G

Port

Man

ual R

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D7

D5

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D12

D16

D20

D24

D13

D17

D21

D25

D14

D18

D22

D26

D15

D27

D23

D19

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Figure 18. x1 upstream and 15x1 downstream (PCFG=0000)

Figure 19. x4 upstream 12x1 downstream (PCFG=0001)


Figure 20. x4 upstream, 1x4 and 8x1 downstream (PCFG=0010)



Figure 22. x8 upstream, 8x1 downstream (PCFG=0101)


6. Bill of Materials/ Schematics

Item # Qty Man. Man. Part # Description Package Type Component Designator(s)

SURFACE MOUNT COMPONENTS

1 1 PLX PEX8619-BA50BC G

IC, 16 lane 16 port PCIe gen2 switch with DMA,

19x19mm

BGA, 324-pin, full matrix, 1mm

ball pitch U100

2 4 BEL S7AH-08E1A0 .

Non-iso DC/DC converter, 5Vin/0.9-3.3Vout @8A SMT, 7-pin U2, U3, U4, U5

3 1 Intersil ISL6132IR IC, multiple voltage monitor SMT, QFN-24 U16 4 2 National NC7S08M5X IC, 2-input AND gate SMT, SOT23-5 U17, U21

5 2 MAXIM MAX6420UK16-T

IC, Reset controller, Adj. reset timeout SMT, SOT23-5 U18, U20

6 1 ATMEL AT25256AN-10SU-2.7 IC, SPI Serial EEPROM SMT, SO-8 U19

7 2 SpectralLinear/Cypress CY28400OXC-2 IC, 100MHz Differential

Clock Buffer SMT, SSOP-28 U28, U61

8 44 Fairchild MM74HC164MX IC, 8-bit serial in/parallel-out shift register SMT, SO14

U29, U30, U31, U32, U33, U34, U35, U36, U37, U38, U39, U40, U41, U42, U43, U44, U45, U46, U47, U48, U49, U50, U51, U52, U53, U54, U55, U56, U57, U58, U59, U60, U62, U63, U64, U65, U66, U67, U68, U69, U83, U84,

U88, U89

9 1 MAXIM MAX7311AUG IC, 2-wire-interface 16-bit

I/O Port Expander with Interrupt

SMT, TSSOP-24 U71

10 1 Texas TPS2311IPW IC, dual hot-swap power controller SMT, TSSOP-20 U70

11 1 Texas SN74LVC157APW

IC, Quad 2-to-1 data selector/multiplexer SMT, TSSOP-16 U72

12 1 MAXIM MAX6658MSA IC, SMBus-compatible temperature sensor SMT, SO-8 U78

13 5 NXP SEMI SN74LVC04AD IC, hex inverter SMT, SO-14 U80, U85, U87, U91, U92

14 1 On Semiconductor NB3N5573DTG IC, crystal to HCSL clock

generator, 3.3V SMT TSSOP-16 U108

15 2 On Semiconductor

MC100LVEP111FAG

IC, 1:10 differential ECL/PECL/HSTL clock

driver, 2.5/3.3V SMT, QFP-32 U113, U114

16 1 Xilinx XC3S200-4FTG256C

IC, Spartan-3 FPGA, 4ns, 173 I/Os, 256-pin, 1mm

pitch,

SMT, 256-pin BGA U115

17 1 Xilinx XCF01SVOG20C

IC, 1Mbit platform flash PROM SMT, TSSOP-20 U116

18 1 Maxim MAX8833ETJ+ IC, dual 3A step-down regulator SMT, QFN-32 U117

19 2 International Rectifier IRF7470PBF IC, N-channel MOSFET,

40V/10A 13mohm SMT, SO-8 Q1, Q2

20 11 Lumex SML-LXT0805GW-TR LED, green color SMT, 0805 D1, D2, D3, D4, D5, D9, D28,

D29, D30, D31, D32

21 2 CML Innovative Technologies 7016X1/5 LED, dual color, green/red SMT, 4-pin D8, D10

22 16 CML Innovative Technologies 7016X5/7 LED, dual color,

genn/yelow SMT, 4-pin D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23,

D24, D25, D26, D27

23 1 Citizen HCM49 25.000MABJ-UT

CRYSTAL, 25.000 MHz, 18pF load capacitor SMT Y2

24 1 ECS Inc ECS-3953M-1000-AU

OSC, 100.000 MHZ 3.3V SMD SMT Y4

25 2 Panasonic ELL-6SH1R0M Inductor, 1.0UH 20% 3.4A, SMT L2, L3 26

27 3 FCI 84517-101LF Connector, 10x20, Receptacle SMT U74, U75, U76

28 2 Molex 75586-0011

Connector, receptacle, right angle receptacle,

0.8mm pitch for PCIE 4x cable,

SMT 38-pin connector J5, J6



30 15 CTS 742C083472JTR Resistor Network, 4.7K ohm 4R isolated SMT, 8-pin

RN1, RN4, RN5, RN6, RN7, RN8, RN9, RN10, RN11, RN13, RN54,

RN55, RN58, RN59, RN60

31 40 Panasonic EXB-2HV221JV Resistor Network, 220 ohm 8R isolated SMT, 16-pin

RN14, RN15, RN16, RN17, RN18, RN19, RN20, RN21, RN22, RN23, RN24, RN25, RN26, RN27, RN28, RN29, RN30, RN31, RN32, RN33, RN34, RN35, RN36, RN37, RN38, RN39, RN40, RN41, RN42, RN43, RN44, RN45, RN46, RN47, RN48, RN49, RN50, RN51, RN52, RN53

32 1 CTS 742C083103JTR Resistor Network 10K ohm 4R isolated SMT, 8-pin RN56

33 1 CTS 742C083102JTR Resistor Network, 1K ohm 4R isolated SMT, 8-pin RN3

34 5 ROHM MCR10EZHJ000 RES. 0.0 OHM 5% SMT, 0805 R10, R59, R61, R62, R269

35 2 Panasonic ERJ-6ENF2001V RES. 2.00K OHM 1% SMT, 0805 R262, R263

36 1 Panasonic ERJ-6ENF2002V RES. 20.0K OHM 1% SMT, 0805 R251

37 3 Yageo RC0805FR-07374RL RES. 374 OHM 1% SMT, 0805 R29, R30, R34

38 1 Panasonic ERJ-6ENF4701V RES. 4.70K OHM 1% SMT, 0805 R268

39 12 Panosonic ERJ-3GEY0R00V RES. ZERO OHM 5% SMT, 0603

R277, R285, R286, R287, R311, R314, R315, R339, R340, R344,

R407, R408

40 40 Panasonic ERJ-3GEYJ102V RES. 1K OHM 5% SMT, 0603

R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R505, R506, R507, R508, R509, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528, R529, R510

42 40 Panasonic ERJ-3GEYJ121V RES. 120 OHM 5% SMT, 0805

R530, R531, R532, R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, R569

43 2 Panasonic ERJ-3GEYJ4R7V RES. 4.7 OHM 5% SMT, 0603 R293, R320

44 12 Panasonic ERJ-3GEYJ512V RES. 5.1K OHM 5% SMT, 0603

R307, R308, R309, R310, R312, R313, R334, R335, R336, R337,

R338, R374

45 48 Panasonic ERJ-3GEYJ103V RES 10K OHM 1% SMT, 0603

R449, R454, R455, R456, R457, R458, R459, R460, R465, R466, R467, R468, R469, R470, R471, R472, R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, R497, R498, R499, R500, R501,

R502, R503, R504 46 4 Panasonic ERJ-3EKF1431V RES 1.43K OHM 1% SMT, 0603 R281, R282, R283, R284 47 1 Panasonic ERJ-3EKF2000V RES 200 OHM 1% SMT, 0603 R278 48 2 Panasonic ERJ-3EKF2261V RES 2.26K OHM 1% SMT, 0603 R42, R44 49 3 Panasonic ERJ-3EKF4750V RES 475 OHM 1% SMT, 0603 R79, R292, R319 50 1 Panasonic ERJ-3EKF4990V RES 499 OHM 1% SMT, 0603 R28

51 9 Yageo RC0603FR-075K1L RES 5.10K OHM 1% SMT, 0603 R60, R64, R70, R71, R72, R77,

R78, R80, R81



52 8 Panasonic ERJ-3EKF7321V RES 7.32K OHM 1% SMT, 0603 R450, R451, R452, R453, R461, R462, R463, R464

53 36 Panasonic ERJ-S02F3900X RES 390 OHM 5% SMT, 0402

R49, R50, R53, R54, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246,

R247

54 27 Panasonic ERJ-2GEJ472X RES 4.7K OHM 5% SMT, 0402

R9, R33, R35, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R259, R260, R265, R266, R270, R271, R272,

R273, R274

55 3 Panasonic ERJ-2RKF1001X RES 1.00K OHM 1% SMT, 0402 R254, R257, R258

56 1 Yageo RM04F1001CTLF RES 1K 1% SMT, 0402 R350


58 3 Yageo RM04F1002CTLF RES 10K 1% SMT, 0402 R348, R349, R359

59 1 Panasonic ERJ-2RKF1003X RES 100K OHM 1% SMT, 0402 R248

60 1 Yageo RM04F10R0CTLF RES 10.0 OHM 1% SMT, 0402 R346

61 1 Panasonic ERJ-2RKF1181X RES 1.18K OHM 1% SMT, 0402 R41




65 3 Panasonic ERJ-2RKF1500X RES 150 OHM 1% SMT, 0402 R253, R255, R256

66 1 Yageo RM04F2000CTLF RES 200 OHM 1% SMT, 0402 R347

67 1 Yageo RM04F2001CTLF RES 2K OHM 1% SMT, 0402 R14

68 4 Yageo RM04F2002CTLF RES 20K 1% SMT, 0402 R352, R355, R356, R357




72 21 Yageo RC0402FR-0733RL RES 33.0 OHM 1% SMT, 0402

R63, R65, R289, R291, R297, R299, R300, R301, R302, R306, R316, R318, R324, R326, R327, R328, R329, R333, R341, R342,

R353

73 1 Yageo RT0402FRE07360RL RES 360 OHM 1% SMT, 0402 R2

74 2 Panasonic ERJ-2RKF3652X RES 36.5K OHM 1% SMT, 0402 R7, R11

75 1 Panasonic ERJ-2RKF4640X RES 464 OHM 1% SMT, 0402 R43

76 1 Yageo ERJ-2RKF4991X RES 4.99K 1% SMT, 0402 R354

77 18 Panasonic ERJ-2RKF49R9X RES 49.9 OHM 1% SMT, 0402

R73, R74, R290, R294, R295, R296, R298, R303, R304, R305, R317, R321, R322, R323, R325,

R330, R331, R332


Item # Qty Man. Man. Part # Description Package Type Component Designator(s) 78 2 Panasonic ERJ-2GEJ513X RES 51K OHM 1% SMT, 0402 R57, R66

79 1 Yageo RT0402FRE0751RL RES 51.1 OHM 1% SMT, 0402 R267


81 1 Panasonic ERJ-2RKF7321X RES 7.32K OHM 1% SMT, 0402 R38,

82 2 Panasonic ERJ-M1WSF20MU RES 0.02 OHM 1W 1% SMT, 2512 R261, R264

83 1 Yageo 9C06031A7321FKHFT

Res. 7.32K ohm, 1/10W 1% SMT, 0603 R343

84 1 Yageo 9C06031A1001FKHFT Res. 1.0K ohm 1/10W 1% SMT, 0603 R345

85 2 Panasonic ERJ-2GEJ203X Res. 20K ohm 1/16W 5% SMT, 0402 R360-R361

90 11 Panasonic ECJ3YB1C106M CAP 10uF 16V 20% X5R SMT, 1206 C42, C45, C47, C64, C67, C315, C319, C320, C326, C336, C339

91 1 CALCHIP ECJ-2VC1H151J CAP 150pf 50V 5% NPO SMT, 0805 C160 92 1 CALCHIP ECJ-2VC1H331J CAP 330pf 50V 5% NPO SMT, 0805 C80

93 2 Panasonic ECJ-2VB1H102K CAP 1000pf 50V 10% X7R SMT, 0805 C79, C82

94 8 Kemet GMC21X7R104K50NT CAP 0.1 uf 50V 10% X7R SMT, 0805 C72, C73, C74, C76, C78, C83,

C86, C157

95 32 CALCHIP GMC21X7R105K16NT-LF CAP 1UF10% 16V X5R SMT, 0805

C1, C2, C6, C8, C10, C12, C13, C16, C19, C20, C21, C24, C25, C26, C27, C28, C44, C46, C48,

C63, C65, C71, C161, C257, C296, C298, C301, C302, C305,

C306, C308, C310

96 2 Kemet GMC21X5R106M6R3NT CAP 10uf 6.3V 20% X5R SMT, 0805 C75, C84

97 1 CALCHIP 08055C223KAT2A

CAP 0.022uf 50V 10% X7R SMT, 0805 C163

98 1 CALCHIP GMC21X5R226M6R3NT CAP 22uf 6.3V 20% X5R SMT, 0805 C156

99 1 AVX 06033A180GAT2A CAP 18PF 25V NP0 SMT, 0603 C327

100 1 AVX 0603YA220JAT2A CAP 22PF 16V NP0 SMT, 0603 C328

101 24 Kemet C0603C105K8PACTU CAP 1.0UF 10V 10% X5R SMT, 0603

C89, C90, C91, C92, C93, C94, C95, C98, C121, C122, C123,

C124, C125, C126, C127, C128, C389, C391, C392, C393, C395,

C396, C412, C423

102 47 AVX 04026C102KAT2A CAP 1000PF 50V X7R SMT, 0402

C88, C153, C105, C108, C109, C110, C116, C117, C118, C120, C141, C145, C146, C148, C151, C259, C260, C334, C378, C379, C380, C381, C382, C383, C394, C397, C398, C399, C400, C401, C402, C403, C404, C405, C406, C407, C408, C409, C410, C415, C416, C417, C418, C419, C420,

C421, C422

103 72 Panasonic ECJ-0EB1C103K CAP 0.01uf 16V 10% X7R SMT, 0402

C101, C102, C106, C107, C133, C137, C158, C159, C316, C317, C318, C321, C324, C325, C337, C338, C340, C341, C211, C212, C213, C214, C215, C216, C217, C218, C219, C220, C221, C222, C223, C224, C225, C226, C227, C228, C229, C230, C231, C232, C233, C234, C235, C236, C237, C238, C239, C240, C241, C242, C243, C244, C245, C246, C247, C248, C249, C250, C311, C312, C313, C314, C384, C385, C386, C387, C388, C390, C411, C413,

C414, C424



104 97 Kemet C0402C104K8PACTU CAP 0.1UF 10V X5R SMT, 0402

C85, C87, C154, C251, C252, C255, C256, C258, C261, C263, C264, C265, C266, C267, C268, C269, C270, C271, C272, C273, C274, C275, C276, C277, C278, C279, C280, C281, C282, C283, C284, C285, C286, C287, C288, C289, C290, C291, C292, C293, C294, C444, C445, C446, C447, C448, C449, C450, C451, C452, C453, C454, C455, C456, C457, C458, C459, C460, C461, C462, C463, C464, C465, C466, C467, C468, C469, C470, C471, C472, C473, C474, C475, C476, C477, C478, C479, C480, C481, C482, C483, C484, C485, C486, C487, C488, C489, C490, C491, C492, C493, C494, C495, C496, C497,

C498, C499

105 1 AVX 04023C222JAT2A CAP 2200PF 25V X7R SMT, 0402 C262

106 54 AVX TAJC226K020R CAP 22UF 20V 10% Tantalum SMT, C Case

C3, C4, C5, C7, C9, C11, C14, C15, C17, C18, C22, C23, C29,

C30, C31, C32, C181, C182, C183, C184, C185, C186, C187, C188, C189, C190, C191, C192, C193, C194, C195, C196, C197, C198, C199, C200, C201, C202, C203, C204, C205, C206, C207, C208, C209, C210, C295, C297, C299, C300, C303, C304, C307,

C309

107 10 AVX 0201ZD103KAT2A

CAP 0.01UF 10% 10V X5R SMT, 0201 C96, C97, C99, C100, C129,

C130, C134, C135, C136, C138

108 20 Panasonic ECJ-ZEB1E102K CAP 1000PF 25V X7R SMT, 0201

C103, C104, C111, C112, C113, C114, C115, C119, C131, C132, C139, C140, C142, C143, C144, C147, C149, C150, C152, C155

109 3 Vishay 594D187X0016R2T

CAP, 180UF 16V 20% Tantalum SMT, D Case C34, C35, C36

THROUGH-HOLE COMPONENTS

200 40 Lumex LDS-A516RI 7-SEGMENT display, red,

common anode, 0.75"x0.48"

10-pin DIP

DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, DS10, DS11,

DS12, DS13, DS14, DS15, DS16, DS17, DS18, DS19, DS20, DS21, DS22, DS23, DS24, DS25, DS26, DS27, DS28, DS29, DS30, DS31, DS32, DS33, DS34, DS35, DS36,

DS37, DS38, DS39, DS40

201 10 CK-Components BD04 Switch, dipswitch, 4-POS Top Slide 8-pin TH

SW2, SW3, SW4, SW5, SW6, SW7, SW10, SW13, SW14,

SW15

202 1 CK-Components BD02 Switch, dipswitch, 2-POS Top Slide 4-pin TH SW11

203 3 E Switch TL1105F100Q Switch, momentary E-switch, 6mm SQ, 4-pin TH S1, S2, S3

204 1 Samtec TMS-103-02-S-S micro therninal strip, 1x3, Centerline:.050" 1x3 TH JP100

205 6 Molex 15-24-4449 Connector, 4-pos straight

ATX peripherial power connector

4-pin TH J1, J2, J3, J4, J7, J8

206 2 Molex 74540-0400 Guide house, for 4x link

PCIe external cable connector

TH CAGE1 and CAGE2 for J5, J6

207 1 SULLINS PBC05DAAN HEADER, 5X2, 100mil TH, 10-pin JP3 208 2 SULLINS PBC02DAAN HEADER, 2X2, 100mil TH, 4-pin JP5, JP8 209 1 Sullins PBC10DAAN HEADER, 2X10, 100mil TH, 20-pin JP10 210 1 Sullins PBC03DAAN HEADER, 2X3, 100mil TH, 6-pin J13



211 1 Molex 39-28-1083 CONN, 2 X 4 straight

locking 12V ATX power connector

TH, 8-pin J10

212 1 Molex 44206-0001 Conn, ATX 24-pin Mainboard Power

Connector TH, 24-pin J9

213 1 Molex 87831-1420 CONN, 2 X 7 straight shrouded, 2mm pitch TH, 14-pin J12

214 15 FCI 10018783-10003TLF

Conn. X16 PCIe card edge connector Vertical , 164-

pin 1mm pitch TH, 164-pin

SLOT1, SLOT2, SLOT3, SLOT4, SLOT5, SLOT6, SLOT7, SLOT8,

SLOT9, SLOT10, SLOT11, SLOT12, SLOT13, SLOT14,

SLOT15 MANUALLY INSERTED COMPONENTS 300 3 Amp/Tyco 382811-6 Jumpers JP13 (1-2,3-4,5-6)

MISCELLANEOUS COMPONENTS 400 8 Olander .2C5PPMS Screw, M2 X 5MM PHIL

PAN SST XCAGE1, XCAGE2

401 12 3M SJ5009(BLACK) RUBBER BUMPER, .40 X .88 BLACK Install at the bottom side of each

board

402 1 PLX Technology 90-0104-000A PCB, PEX8619 Base Board RDK

PART THAT SHOULD NOT BE ASSEMBLED 500 0 Concord

Electronics 09-9127-1-0210 CONN, banana jack, black color TH BJ3, BJ6, BJ9

501 0 Concord Electronics 09-9127-1-0212 CONN, banana jack, red

color TH BJ4, BJ5, BJ10

502 0 Agilent E5387-68701 Midbus LAI 48-pin header shroud TH JP6

503 0 TBD TBD RES. SMT, 2512

R15, R18, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R36, R39, R40, R46, R48, R51,

R52, R55

504 0 Maxium DS4100H+ IC, HCSL, OSC, 100MHz SMT, 10-pin LCCC U98

505 0 TBD TBD RES. SMT, 0805 R4, R5, R13, R16 506 0 TBD TBD CAP. SMT 0603 C253, C254 507 0 TBD TBD RES. SMT, 0402 R75, R76

20 0 Lumex SML-LXT0805GW-TR LED, green color SMT, 0805 D6, D7

65 0 Panasonic ERJ-2RKF1500X RES 150 OHM 1% SMT, 0402 R31, R32

26 0 AMP 767054-1 Connector, 38-pin Mictor connector, vertical SMT, vertical JP9, JP11

NOTES A. R277, R314, R315, R407and R408 are placed at pad 1 and 3 B. Header JP13 jump 1-2,3-4 and 5-6 C. 2"x1/4" labes with two different wordings depends the Kit to order 1."PEX8619BA-BB8U1D RDK" 2."PEX8619BA-BB4U1D RDK" D. The label should be placed at upper right hand corner in the box E. R343, R345, R360 and R361 are used for rework the board (see assembly instructions for details)

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

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PLX TECHNOLOGY, INC.870 W Maude Ave, Sunnyvale, CA 94085

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8619 Base Board RDKTitle


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8619 Base Board RDK

x1

SLOT1

x1x1

SLOT2SLOT3

x1x1

SLOT5SLOT6

x1

SLOT7

x1

SLOT4

x1x1

SLOT9SLOT10

x1

SLOT11

x1

SLOT8

x1x1

SLOT13SLOT14

x1

SLOT15

x1

SLOT12

CONFIG RECEPTACLE

EPROM

PORT ID

POER WIDTH

MidBus Connector

PCIe[3:0]

CONFIG RECEPTACLE CONFIG RECEPTACLE

8619

JTAG

I2C

XC3S200

PORT ID

POER WIDTH

PORT ID

POER WIDTH

PCIe[7:4]

TEMPERATURE

USER STATUS

5

5

4

4

3

3

2

2

1

1

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C C

B B

A A

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8619 Base Board RDK

RELEASE NOTES:

Initial Release: Apr 18, 2008

Release 0.1: May 15, 2008

- changed the RefClock Fanout Buffer to MC100LVEP111

- Chnaged the Xilinx FPGA part from XCS40XL to XC3S200 and the associated prom

- Added the Multioutput Voltage regulator for the new Xilin FPGA

- Updated the JTAG interface to USB to conform to latest Xilinx Tools

Release 0.2: March 9, 2009

- changed the R510 from 120 ohm to 1K ohm on page 6

5

5

4

4

3

3

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www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

RELEASE NOTES:

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAN_PST_S3

RST_8

SRT_8

PERST#_9

PWRGD_2p5

PWRGD_1p0

12V_A

5V_A

12V_A

5V_A

12V_A

5V_A

12V_A

5V_A

5V_A

12V_A

12V_A

5V_A

12V_A

5V_A

1.0VCC1.0VCC_A3.3VCC 2.5VCC2.5VCC_A

12V_SLT_112V_SLT_2

12V_SLT_312V_SLT_4

12V_SLT_512V_SLT_6

12V_SLT_712V_SLT_8

12V_SLT_912V_SLT_10

12V_SLT_1112V_SLT_12

12V_SLT_1312V_SLT_14

12V_SLT_15

3.3VCC_SLT_83.3VCC_SLT_1

3.3VCC_SLT_2_3

3.3VCC

3.3VCC_SLT_12_13

3.3VCC_SLT_14_15

3.3VCC_SLT_9

3.3VCC_SLT_10_113.3VCC_SLT_4_5

3.3VCC_SLT_6_7

12V_A

3.3VCC 12V_A35V_A

3.3VCC

3.3VCC

3.3VCC

1.0VCC_A

3.3VCC

2.5VCC

2.5VCC_A

1.0VCC

5V_A1.0VCC

5V_A1.0VCC_A

5V_A3.3VCC1

3.3VCC1

2.5VCC5V_A

2.5VCC_A2.5VCC

2.5VCC

1.0VCC

1.0VCC_A

3.3VCC

3.3VCC

3.3VCC

3.3VCC

1.0VCC 2.5VCC

3.3VCC

12V_A212V_A1

12V_A312V_A2

12V_A1

PS_Pwr_good [23,26]

PS_ON_n[26]

FPGA_PEX_PERST_n [26]

CPERST_n[16]

DEBUG_NORMAL_n[26]

Title


Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


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8619 Base Board RDK

ATX HD POWER CONNECTORS

8A

4A

8A

4A

8A

4A

8A

4A

POWER INDICATOR LEDSPlace these next to appropriate Connectors

8A

4A

8A

4A

POWER INDICATORLEDS Place these nextto appropriate voltagesource. Silkscreenshould lable these

C37 IS USED TO SET THE RESET TIMEOUT PERIODFOR U18. A VALUE OF 0.001UF RESULTS ISAPPROXIMATELY 3MS. SEE MANUFACTURERDATASHEET FOR DETAILS.

RESET CIRCUIT

Place the shunt in position 1 and 3

2 hotplug

2 hotplug

1.0v +F8A

Trim up

5V-TO-1.0V DC/DC CONVERTER

1.0v +F

8A

Trim up

5V-TO-1.0V_A DC/DC CONVERTER

8A

Trim up

5V-TO-3.3V DC/DC CONVERTER

5V-TO-2.5V DC/DC CONVERTER2.5v -F

2.5V_A LDO

1.0v +F

1.0v -F1.0v +F

SW1 SETTINGS:1: OFF2: ON

The Circuit on Board is Designed toprovides Enough Load for all RAILS.These Resistor are there Just in Casethe Power Supply Continues to TripBecause of Min Load Requirement

PEX8619 VOLTAGE MONITOR CIRCUIT

D7 is green: 2.5VCCis withinthe 10%rangeD7 is red: 2.5VCC is out ofrange

D8 is green: 1.0VCC iswithinthe 10% rangeD8 is red: 1.0VCC isout of range

8A

Trim up

U17

NC7S08

U17

NC7S08

VCC5

GND 3

A1

B2

Y 4

TV5

Prototyping Pad

TV5

Prototyping Pad

R52

NL

R52

NL

D6GREEN

D6GREEN

2 1

C301

1uF

C301

1uF

TV51

Prototyping Pad

TV51

Prototyping Pad

BJ6blackBJ6black

1

C87

0.1uF

C87

0.1uF

C13

1uF

C13

1uF

TV43

Prototyping Pad

TV43

Prototyping Pad

TV11

Prototyping Pad

TV11

Prototyping Pad

BJ9blackBJ9black

1

SW15 SW DIP-4SW15 SW DIP-4

1234

8765

R18NLR18NL

R50390R50390

TV2

Prototyping Pad

TV2

Prototyping Pad

R32 150R32 150

C306

1uF

C306

1uF

C44

1uF

C44

1uF

C47

10uF

C47

10uF

TV10

Prototyping Pad

TV10

Prototyping Pad

R55

NL

R55

NL

R455.76K 1% R455.76K 1%

TV52

Prototyping Pad

TV52

Prototyping Pad

R23

NL

R23

NL

TV50

Prototyping Pad

TV50

Prototyping Pad

R28 499 1%R28 499 1%

J1

15244449

J1

15244449

+12VDC 1

COM0 2

COM1 3

+5VDC 4

TV44

Prototyping Pad

TV44

Prototyping Pad

+C30

22uF

+C30

22uF

C6

1uF

C6

1uF

TV16

Prototyping Pad

TV16

Prototyping Pad

R60

5.1K

R60

5.1K

R142K 1%

R142K 1%

RN1

4.7K

RN1

4.7K

12345

678

R736.5K 1%

R736.5K 1%

D7GREEN

D7GREEN

2 1

+C7

22uF

+C7

22uFC302

1uF

C302

1uF

TV53

Prototyping Pad

TV53

Prototyping Pad

TV15

Prototyping Pad

TV15

Prototyping Pad

R57

51K

R57

51K

R38

7.32K 1%

R38

7.32K 1%

TV3

Prototyping Pad

TV3

Prototyping Pad

+C18

22uF

+C18

22uF

C45

10uF

C45

10uF

C2

1uF

C2

1uF

TV25

Prototyping Pad

TV25

Prototyping Pad

C26

1uF

C26

1uF

TV45

Prototyping Pad

TV45

Prototyping Pad

C48

1uF

C48

1uF

J4

15244449

J4

15244449

+12VDC 1

COM0 2

COM1 3

+5VDC 4

R49390R49390

TV8

Prototyping Pad

TV8

Prototyping Pad

TV18

Prototyping Pad

TV18

Prototyping Pad

C8

1uF

C8

1uF

U2

V7AH-08E1A0

U2

V7AH-08E1A0

Vin2 Vout 4

On/Off#1

Gnd

3

Trim 5

NC

06

NC

17

BJ10redBJ10red

1

C19

1uF

C19

1uF

+C4

22uF

+C4

22uF

J10

ATX 4plus4 Proc 12V Conn

J10

ATX 4plus4 Proc 12V Conn

GND1 1GND2 2GND3 3GND4 412V1_15 12V1_26 12V2_17 12V2_28

D2GREEN

D2GREEN

2 1

D3GREEN

D3GREEN

2 1

TV12

Prototyping Pad

TV12

Prototyping Pad

+C36

180uF

+C36

180uF

TV19

Prototyping Pad

TV19

Prototyping Pad

TV46

Prototyping Pad

TV46

Prototyping Pad

U5

V7AH-08E1A0

U5

V7AH-08E1A0

Vin2 Vout 4

On/Off#1

Gnd

3

Trim 5

NC

06

NC

17

C46

1uF

C46

1uF

+C11

22uF

+C11

22uF

TV28

Prototyping Pad

TV28

Prototyping Pad

S1

SW PUSHBUTTON

S1

SW PUSHBUTTON

1 342

+C22

22uF

+C22

22uF

R47

2.32K 1%

R47

2.32K 1%

TV13

Prototyping Pad

TV13

Prototyping Pad

U3

V7AH-08E1A0

U3

V7AH-08E1A0

Vin2 Vout 4

On/Off#1

Gnd

3

Trim 5

NC

06

NC

17

TV21

Prototyping Pad

TV21

Prototyping Pad

+C15

22uF

+C15

22uF

C1

1uF

C1

1uF

+C35

180uF

+C35

180uF

R21

NL

R21

NL

TV56

Prototyping Pad

TV56

Prototyping Pad

R16 NLR16 NL

C12

1uF

C12

1uF

+C3

22uF

+C3

22uF

TV6

Prototyping Pad

TV6

Prototyping Pad

C65

1uF

C65

1uF

D5GREEN

D5GREEN

2 1

R121.21K 1%

R121.21K 1%

C16

1uF

C16

1uF

TV24

Prototyping Pad

TV24

Prototyping Pad

+C31

22uF

+C31

22uF

GR

D8

GREEN_RED_LED

GR

D8

GREEN_RED_LED

21

43

J9

ATX-400P24

J9

ATX-400P24

+3.3V_11+3.3V_22COM_13+5V_14COM_25+5V_26COM_37PG8+5VSB9+12V_110+12V_211+3.3V_312

+3.3V_4 13

COM_4 15PS-ON 16COM_5 17COM_6 18COM_7 19

-5V 20+5V_3 21+5V_4 22+5V_5 23

COM_8 24

-12V 14

C85

0.1uF

C85

0.1uF

TV22

Prototyping Pad

TV22

Prototyping Pad

C25

1uF

C25

1uF

+C307

22uF

+C307

22uF

R2 360R2 360

BJ3blackBJ3black

1

R58

10K

R58

10K

+C295

22uF

+C295

22uF

R1136.5K 1%

R1136.5K 1%

TV26

Prototyping Pad

TV26

Prototyping Pad

TV20

Prototyping Pad

TV20

Prototyping Pad

R19

NL

R19

NL

R43

464 1%

R43

464 1%

R15NLR15NL

R30 374 1%R30 374 1%

+C9

22uF

+C9

22uF

U16

ISL6132

U16

ISL6132

VD

D23

GN

D10

EN11EN211

UVMON_120OVMON_112UVMON_217OVMON_214

UVSTATUS_1 2OVSTATUS_1 5UVSTATUS_2 6OVSTATUS_2 7

PGOOD 24PGOOD2 9

NC

113

NC

215

NC

316

NC

418

NC

519

NC

621

NC

722

NC93NC84 N

C0

8

+C23

22uF

+C23

22uF

R34 374 1%R34 374 1%

C63

1uF

C63

1uF

J3

15244449

J3

15244449

+12VDC 1

COM0 2

COM1 3

+5VDC 4

GR

D10

GREEN_RED_LED

GR

D10

GREEN_RED_LED

21

43

BJ4redBJ4red

1

C296

1uF

C296

1uF

R4 NLR4 NL

J2

15244449

J2

15244449

+12VDC 1

COM0 2

COM1 3

+5VDC 4

J8

15244449

J8

15244449

+12VDC 1

COM0 2

COM1 3

+5VDC 4

C308

1uF

C308

1uF

R37

3.09K 1%

R37

3.09K 1%

C24

1uF

C24

1uF

R36

NL

R36

NL

C20

1uF

C20

1uF

TV54

Prototyping Pad

TV54

Prototyping PadR29 374 1%R29 374 1%

J7

15244449

J7

15244449

+12VDC 1

COM0 2

COM1 3

+5VDC 4

C27

1uF

C27

1uF

TV23

Prototyping Pad

TV23

Prototyping Pad

TV9

Prototyping Pad

TV9

Prototyping Pad

C88

0.001uF

C88

0.001uF

D9GREEN

D9GREEN

2 1

TV33

Prototyping Pad

TV33

Prototyping Pad

TV57

Prototyping Pad

TV57

Prototyping Pad

R39

NL

R39

NL

TV55

Prototyping Pad

TV55

Prototyping Pad

R33 4.7KR33 4.7KU4

V7AH-08E1A0

U4

V7AH-08E1A0

Vin2 Vout 4

On/Off#1

Gnd

3

Trim 5

NC

06

NC

17

R1 1.2KR1 1.2K

+C303

22uF

+C303

22uF

TV14

Prototyping Pad

TV14

Prototyping Pad

+C5

22uF

+C5

22uF+C299

22uF

+C299

22uF

R10

0.0 Ohm

R10

0.0 OhmR24

NL

R24

NL

TV34

Prototyping Pad

TV34

Prototyping Pad

R9

4.7K

R9

4.7K

C21

1uF

C21

1uF

R40

NL

R40

NL

R54390R54390

D4GREEN

D4GREEN

2 1

+C304

22uF

+C304

22uF

TV27

Prototyping Pad

TV27

Prototyping Pad

+C14

22uF

+C14

22uF+C309

22uF

+C309

22uF

+C32

22uF

+C32

22uF

R35 4.7KR35 4.7K

R59 0R59 0

R25

NL

R25

NL

+C17

22uF

+C17

22uF

TV48

Prototyping Pad

TV48

Prototyping Pad

+C297

22uF

+C297

22uF

+C300

22uF

+C300

22uF

R46

NL

R46

NL

D1GREEN

D1GREEN

2 1

U18

MAX6420

U18

MAX6420

RST IN3 VCC 5

SRT4 GND 2

RESET# 1

R48

NL

R48

NL

R22

NL

R22

NL

R31 150R31 150

C42

10uF

C42

10uF

R20

NL

R20

NL

TV7

Prototyping Pad

TV7

Prototyping Pad

R13 NLR13 NL

C310

1uF

C310

1uF

C28

1uF

C28

1uF

TV49

Prototyping Pad

TV49

Prototyping Pad

R26

NL

R26

NL

R411.18K 1% R411.18K 1%

TV17

Prototyping Pad

TV17

Prototyping Pad

C71

1uF

C71

1uF

R61 0R61 0

R277

0 Shunt

R277

0 Shunt

123

TV4

Prototyping Pad

TV4

Prototyping Pad

R51

NL

R51

NL

R53390R53390

+C34

180uF

+C34

180uF

BJ5redBJ5red

1

TV1

Prototyping Pad

TV1

Prototyping Pad

R5 NLR5 NL

C10

1uF

C10

1uF

C298

1uF

C298

1uF

R27

NL

R27

NL

C67

10uF

C67

10uF

+C29

22uF

+C29

22uFC305

1uF

C305

1uF

C64

10uF

C64

10uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CFC_Clk_pCFC_Clk_n

3.3VCC

3.3VCC

3.3VCC

3.3VCC

3.3VCC

3.3VCC3.3VCC

3.3VCC

CREFCLKRECEPT0_p[16]

RCKp_PEX8619 [7]RCKn_PEX8619 [7]

CREFCLKRECEPT0_n[16]SSC_CK1p [6]SSC_CK1n [6]

SSC_CK2p [6]SSC_CK2n [6]

CFC_CK1p [6]CFC_CK1n [6]

CFC_RCKp_PEX8618 [7]CFC_RCKn_PEX8618 [7]

CFC_CK2p [6]CFC_CK2n [6]

Title


Date: Sheet of

91-0131-000-A 0


C


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Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

Place these CAPS as closeto the destination aspossible

REFCLK CLOCK BUFFER CIRCUITS

No Load Components.

Place these CAPS as closeto the destination aspossible

U108

NB3N5573

U108

NB3N5573

S01S12NC03X1/CLK4X25OE6GND07NC18 IREF 9CLK1# 10CLK1 11VDD0 12GND1 13CLK0# 14CLK0 15VDD1 16

C315

10uF

C315

10uF

TPV27 Prototyping PadTPV27 Prototyping Pad

R306 33R306 33

R311

0 Shunt

R311

0 Shunt

123

R326 33R326 33R374 5.1KR374 5.1K

R297 33R297 33

R334 5.1KR334 5.1K

C320

10uF

C320

10uF

R298

49.9

R298

49.9

C445

0.1uF

C445

0.1uF

C468

0.1uF

C468

0.1uF

C319

10uF

C319

10uF

R408

0 Shunt

R408

0 Shunt

123

R303

49.9

R303

49.9

R327 33R327 33

C328

22pF

C328

22pF

R307 5.1KR307 5.1K

R299 33R299 33R313 5.1KR313 5.1K

R335 5.1KR335 5.1K

R6533

R6533

R304

49.9

R304

49.9

R328 33R328 33

C4500.1uFC4500.1uF


C447

0.1uF

C447

0.1uF

Y2 25MHzY2 25MHz12

R305

49.9

R305

49.9

R319

475 1%

R319

475 1%

R300 33R300 33

C465

0.1uF

C465

0.1uF

R292

475 1%

R292

475 1%

R360

20K

R360

20K

R308 5.1KR308 5.1K

R329 33R329 33

R336 5.1KR336 5.1K

R314

0 Shunt

R314

0 Shunt

123

R301 33R301 33

R316 33R316 33

U98

NL

U98

NL

NC

07

NC

18

NC

29

NC

310

OE1RREF2GND3

VCC 6

OUTN 5OUTP 4

RN55

4R 4.7K

RN55

4R 4.7K

1 2 3 45678

R289 33R289 33

U61

CY28400-2

U61

CY28400-2

VD

D0

1V

DD

15

VD

D2

11V

DD

318

VD

D4

24

VS

S4

OE_INV25

VD

D_A

28

VS

S_A

27

SRC_IN2SRC_IN#3

OE_18OE_621

HIGH_BW#17SRC_STP16PWRDWN15

SCLK13SDATA14

IREF 26

PLL/BYPASS#12

DIFT1 6DIFC1 7

DIFT2 9DIFC2 10

DIFT5 20DIFC5 19

DIFT6 23DIFC6 22

C321

0.01uF

C321

0.01uF

C463

0.1uF

C463

0.1uF

R315

0 Shunt

R315

0 Shunt

123

C316

0.01uF

C316

0.01uF

C467

0.1uF

C467

0.1uF

R330

49.9

R330

49.9

R309 5.1KR309 5.1K

R302 33R302 33

R63 33R63 33

C462

0.1uF

C462

0.1uF

R317

49.9

R317

49.9

R331

49.9

R331

49.9

R79475 1%R79475 1%

R337 5.1KR337 5.1K

C449

0.1uF

C449

0.1uF

C325

0.01uF

C325

0.01uF

R73

49.9

R73

49.9

U28

CY28400-2

U28

CY28400-2

VD

D0

1V

DD

15

VD

D2

11V

DD

318

VD

D4

24

VS

S4

OE_INV25

VD

D_A

28

VS

S_A

27

SRC_IN2SRC_IN#3

OE_18OE_621

HIGH_BW#17SRC_STP16PWRDWN15

SCLK13SDATA14

IREF 26

PLL/BYPASS#12

DIFT1 6DIFC1 7

DIFT2 9DIFC2 10

DIFT5 20DIFC5 19

DIFT6 23DIFC6 22


C317

0.01uF

C317

0.01uF

R310 5.1KR310 5.1K

R338 5.1KR338 5.1K

C158

0.01uF

C158

0.01uF

C324

0.01uF

C324

0.01uF

R323

49.9

R323

49.9

C446

0.1uF

C446

0.1uF

R332

49.9

R332

49.9

C469

0.1uF

C469

0.1uF

R290

49.9

R290

49.9

C159

0.01uF

C159

0.01uF

R322

49.9

R322

49.9

R291 33R291 33

R318 33R318 33

C464

0.1uF

C464

0.1uF

R75 NLR75 NL

R3437.32K 1%

R3437.32K 1%

TPV25Prototyping Pad


R320 4.7R320 4.7

R294

49.9

R294

49.9

R312 5.1KR312 5.1K

C318

0.01uF

C318

0.01uF

R74

49.9

R74

49.9

R344

0 Shunt

R344

0 Shunt

123

R324 33R324 33

C444

0.1uF

C444

0.1uF

R333 33R333 33

C466

0.1uF

C466

0.1uF

R296

49.9

R296

49.9

R321

49.9

R321

49.9

R325

49.9

R325

49.9

C448

0.1uF

C448

0.1uF

R407

0 Shunt

R407

0 Shunt

123

R3451.0K 1%

R3451.0K 1%

C4510.1uFC4510.1uF

R293 4.7R293 4.7

R76 NLR76 NL

R361

20K

R361

20K

R295

49.9

R295

49.9

C327

18pF

C327

18pF

C326

10uF

C326

10uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RCKn_SL9

RCKn_SL12RCKp_SL12

RCKp_SL4RCKn_SL4

RCKp_SL1RCKn_SL1

RCKp_SL5RCKn_SL5

RCKp_SL2RCKn_SL2

RCKp_SL3RCKn_SL3

RCKp_SL8

RCKp_SL11

RCKp_SL7RCKn_SL7

RCKp_SL6RCKn_SL6

RCKn_SL14RCKp_SL14

RCKp_SL10RCKn_SL10

RCKn_SL13RCKp_SL13

RCKn_SL8

RCKp_SL9

RCKn_SL11

RCKp_SL15RCKn_SL15

3.3VCC

3.3VCC

3.3VCC

3.3VCC

3.3VCC

3.3VCC

LAI_RefClk_p [7]LAI_RefClk_n [7]

RCKp_SL9 [13]RCKn_SL9 [13]




RCKp_SL5 [11]


RCKn_SL5 [11]










SSC_ISO_EN_n[8]

SSC_CK1p[5]SSC_CK1n[5]

SSC_CK2p[5]SSC_CK2n[5]

CFC_CK1p[5]CFC_CK1n[5]

CFC_CK2p[5]CFC_CK2n[5]

Title


Date: Sheet of

91-0131-000-A 0


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Date: Sheet of

91-0131-000-A 0


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Date: Sheet of

91-0131-000-A 0


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8619 Base Board RDK

A LOW on SEL selects CLK0

R536120R536120

R47310K

R47310K

R552120R552120

C459

0.1uF

C459

0.1uF

R48210K

R48210K

R5221KR5221K

R564120R564120

R49310K

R49310K



R560120R560120

R531120R531120

C497

0.1uF

C497

0.1uF

C490

0.1uF

C490

0.1uF

R549120R549120

R5091KR5091K

R4421KR4421K

C339

10uF

C339

10uF

R48010K

R48010K

C473

0.1uF

C473

0.1uF

R5201KR5201K

R4341KR4341K

R49110K

R49110K

C480

0.1uF

C480

0.1uF

R4361KR4361K

R48910K

R48910K

R4637.32K

R4637.32K

C471

0.1uF

C471

0.1uF

R46610K

R46610K

C341

0.01uF

C341

0.01uF

R5071KR5071K

C338

0.01uF

C338

0.01uF

R544120R544120

R557120R557120

R4401KR4401K

C499

0.1uF

C499

0.1uF

R47810K

R47810K

R5181KR5181K

R4527.32K

R4527.32K

C482

0.1uF

C482

0.1uF

R48710K

R48710K

R45610K

R45610K

R4617.32K

R4617.32K


R551120R551120

R5051KR5051K

R538120R538120

R563120R563120

R50410K

R50410K

R47610K

R47610K

R5161KR5161KR533

120R533120

R5141KR5141K

R567120R567120

R48510K

R48510K

C456

0.1uF

C456

0.1uF

R50210K

R50210K

R50010K

R50010K

R5121KR5121K

R47210K

R47210K

R546120R546120

R556120R556120

R4481KR4481K

R5291KR5291K

R4461KR4461K

R5271KR5271K

C488

0.1uF

C488

0.1uF

C477

0.1uF

C477

0.1uF

R49810K

R49810K

C493

0.1uF

C493

0.1uF

R46910K

R46910K

R540120R540120

R510

1K

R510

1K

R4517.32K

R4517.32K

C476

0.1uF

C476

0.1uF

C494

0.1uF

C494

0.1uF

R541120R541120

R550120R550120

R4351KR4351K

R46010K

R46010K

R530120R530120

R4441KR4441K

R5251KR5251K

R46810K

R46810K

R45810K

R45810K

R49610K

R49610K

R535120R535120

R4647.32K

R4647.32K

R45510K

R45510K

C336

10uF

C336

10uF

C492

0.1uF

C492

0.1uF

R548120R548120

R46510K

R46510K

R48310K

R48310K

R5231KR5231K

R49410K

R49410K

U114

MC100LVEP111

U114

MC100LVEP111

VC

C_1

1V

CC

_29

VC

C_3

16V

CC

_425

Q0 31

Q1 29

Q2 27

Q3 24

Q4 22

Q5 20

Q6 18

Q7 15

Q8 13

Q9 11

Q0 30

Q1 28

Q2 26

Q3 23

Q4 21

Q5 19

Q6 17

Q7 14

Q8 12

Q9 10

CLK03

CLK16

CLK04

CLK17

SEL2

VBB 5

VEE8

VC

C_5

32

C478

0.1uF

C478

0.1uF

C495

0.1uF

C495

0.1uF


R555120R555120

C475

0.1uF

C475

0.1uF

R4381KR4381K

C489

0.1uF

C489

0.1uF

R569120R569120

C453

0.1uF

C453

0.1uF

C452

0.1uF

C452

0.1uF

R543120R543120

R4431KR4431K

C481

0.1uF

C481

0.1uF

R48110K

R48110K

C498

0.1uF

C498

0.1uF

R5211KR5211K


R49210K

R49210K

C472

0.1uF

C472

0.1uF

R47110K

R47110K

R537120R537120

R4507.32K

R4507.32K

C485

0.1uF

C485

0.1uF

R5081KR5081K

R4411KR4411K

R47910K

R47910K

R5191KR5191K

R49010K

R49010K

C460

0.1uF

C460

0.1uF

C454

0.1uF

C454

0.1uF

R554120R554120

R48810K

R48810K


R4627.32K

R4627.32K

C458

0.1uF

C458

0.1uF

R566120R566120

C340

0.01uF

C340

0.01uF

R45410K

R45410K

R5061KR5061K

R532120R532120

R4391KR4391K

C461

0.1uF

C461

0.1uF

R47710K

R47710K

C486

0.1uF

C486

0.1uF

R5171KR5171K

C484

0.1uF

C484

0.1uF

R545120R545120

R5151KR5151K

R48610K

R48610K

R47410K

R47410K

C474

0.1uF

C474

0.1uF

C479

0.1uF

C479

0.1uF

C457

0.1uF

C457

0.1uF

C496

0.1uF

C496

0.1uF

C491

0.1uF

C491

0.1uF

R562120R562120

R50310K

R50310K

R47510K

R47510K

R50110K

R50110K

R539120R539120

R5131KR5131K

R46710K

R46710K

R44910K

R44910K

R559120R559120



R4371KR4371K

R5281KR5281K

R568120R568120

R553120R553120

R49910K

R49910K

C487

0.1uF

C487

0.1uF

U113

MC100LVEP111

U113

MC100LVEP111

VC

C_1

1V

CC

_29

VC

C_3

16V

CC

_425

Q0 31

Q1 29

Q2 27

Q3 24

Q4 22

Q5 20

Q6 18

Q7 15

Q8 13

Q9 11

Q0 30

Q1 28

Q2 26

Q3 23

Q4 21

Q5 19

Q6 17

Q7 14

Q8 12

Q9 10

CLK03

CLK16

CLK04

CLK17

SEL2

VBB 5

VEE8

VC

C_5

32

R534120R534120

R5111KR5111K

C483

0.1uF

C483

0.1uF

C470

0.1uF

C470

0.1uF

R565120R565120

R4471KR4471K

R561120R561120

R4451KR4451K

R5261KR5261K

R4537.32K

R4537.32K

R47010K

R47010K

R45910K

R45910K

R49710K

R49710K

R547120R547120

C337

0.01uF

C337

0.01uF



C455

0.1uF

C455

0.1uF

R48410K

R48410K

R5241KR5241K

R45710K

R45710K

R558120R558120

R49510K

R49510K



R542120R542120

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PET_p0PET_n0

PET_p1PET_n1PER_p1PER_n1



PET_p4PET_n4




PET_p8PET_n8

PET_p9PET_n9

PET_p10PET_n10

PET_p11PET_n11

PET_p12PET_n12

PET_p13PET_n13

PET_p14PET_n14

PET_p15PET_n15

PER_n0

PER_n10

PER_p8

PER_p12

PER_p10

PER_p0

PER_n9PER_p9

PER_n15

PER_n12

PER_p4

PER_n8

PER_p13

PER_n14

PER_n4

PER_p15

PER_p14

PER_n13

PER_p11PER_n11

RCKp_PEX8619[5]RCKn_PEX8619[5]

CFC_RCKp_PEX8618[5]CFC_RCKn_PEX8618[5]

TX0n_SL15 [16]TX0p_SL15 [16]

TX0n_SL14 [15]TX0p_SL14 [15]

TX0n_SL13 [15]TX0p_SL13 [15]

TX0n_SL12 [14]TX0p_SL12 [14]

RX0p_SL15 [16]RX0n_SL15 [16]

RX0p_SL14 [15]RX0n_SL14 [15]

RX0p_SL13 [15]RX0n_SL13 [15]

RX0p_SL12 [14]RX0n_SL12 [14]

TX3n_RECEPT3 [22]TX3p_RECEPT3 [22]












RX3p_RECEPT3 [22]RX3n_RECEPT3 [22]












LAI_RefClk_p[6]

LAI_RefClk_n[6]

Title


Date: Sheet of

91-0131-000-A 0


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Date: Sheet of

91-0131-000-A 0


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Date: Sheet of

91-0131-000-A 0


C


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8619 Base Board RDK

MIDBUS PROBE IS PUT ON Lane[15:8] Only

The TWO Mechanical Pins on the MidBusProbe should betied to digital Ground

TV39

Prototyping Pad

TV39

Prototyping Pad

R2811.43K1%

R2811.43K1%

C2770.1uF C2770.1uF

TV38

Prototyping Pad

TV38

Prototyping Pad

C2780.1uF C2780.1uF

R2821.43K1%

R2821.43K1%

C2670.1uF C2670.1uF

C2850.1uF C2850.1uF

C2730.1uF C2730.1uF

C2680.1uF C2680.1uF

TV35

Prototyping Pad

TV35

Prototyping Pad

C2860.1uF C2860.1uF

C2740.1uF C2740.1uF

JP100

TMS-103-02-S-S

JP100

TMS-103-02-S-S

REFCLK+1

REFCLK-3 GND 2

C2640.1uF C2640.1uF

TV37

Prototyping Pad

TV37

Prototyping Pad

R2831.43K1%

R2831.43K1%

C2830.1uF C2830.1uF

C2710.1uF C2710.1uF

TV42

Prototyping Pad

TV42

Prototyping Pad

PEX 8619

U100A

PEX 8619

PEX 8619

U100A

PEX 8619

PEX_PETp0 U8

PEX_PETp1 U9

PEX_PETp2 U11

PEX_PETp3 U12

PEX_PETp4 L18

PEX_PETp5 K18

PEX_PETp6 H18

PEX_PETp7 G18

PEX_PETp8 B11

PEX_PETp9 B10

PEX_PETp10 B8

PEX_PETp11 B7

PEX_PETp12 H1

PEX_PETp13 J1

PEX_PETp14 L1

PEX_PETp15 M1

PEX_PETn0 V8

PEX_PETn1 V9

PEX_PETn2 V11

PEX_PETn3 V12

PEX_PETn4 L17

PEX_PETn5 K17

PEX_PETn6 H17

PEX_PETn7 G17

PEX_PETn8 A11

PEX_PETn9 A10

PEX_PETn10 A8

PEX_PETn11 A7

PEX_PETn12 H2

PEX_PETn13 J2

PEX_PETn14 L2

PEX_PETn15 M2

PEX_PERp0 P8

PEX_PERp1 P9

PEX_PERp2 P11

PEX_PERp3 P12

PEX_PERp4 L15

PEX_PERp5 K15

PEX_PERp6 H15

PEX_PERp7 G15

PEX_PERp8 E11

PEX_PERp9 E10

PEX_PERp10 E8

PEX_PERp11 E7

PEX_PERp12 H4

PEX_PERp13 J4

PEX_PERp14 L4

PEX_PERp15 M4

PEX_PERn0 R8

PEX_PERn1 R9

PEX_PERn2 R11

PEX_PERn3 R12

PEX_PERn4 L14

PEX_PERn5 K14

PEX_PERn6 H14

PEX_PERn7 G14

PEX_PERn8 D11

PEX_PERn9 D10

PEX_PERn10 D8

PEX_PERn11 D7

PEX_PERn12 H5

PEX_PERn13 J5

PEX_PERn14 L5

PEX_PERn15 M5

PEX_REFCLKpU10PEX_REFCLKnV10

REXT_A0R10

REXT_B0N11

REXT_A1J15

REXT_B1H13

NC0J17NC1J18

PEX_REFCLK_CFCnA9 PEX_REFCLK_CFCpB9

REXT_A2D9

REXT_B2F8

NC2K1NC3K2

REXT_A3K4

REXT_B3L6

NC4P10

NC5J14

NC6E9

NC7K5

C2660.1uF C2660.1uF

C2720.1uF C2720.1uF

C2840.1uF C2840.1uF

TV36

Prototyping Pad

TV36

Prototyping Pad

TV41

Prototyping Pad

TV41

Prototyping Pad

C2690.1uF C2690.1uF

C2930.1uF C2930.1uF

R2841.43K1%

R2841.43K1%

C2810.1uF C2810.1uF

C2630.1uF C2630.1uF

JP6

Midbus LAI

JP6

Midbus LAI

TX0+1TX0-3 RX0+ 4

RX0- 6

GND8 2

GND9 8RX1+ 10RX1- 12

GND10 14RX2+ 16RX2- 18

GND11 20RX3+ 22RX3- 24

GND12 26RX4+ 28RX4- 30

GND13 32RX5+ 34RX5- 36

GND14 38RX6+ 40RX6- 42

GND15 44RX7+ 46RX7- 48

GND05TX1+7TX1-9GND111TX2+13TX2-15GND217TX3+19TX3-21GND323TX4+25TX4-27GND429TX5+31TX5-33GND535TX6+37TX6-39GND641TX7+43TX7-45GND747DGND1G1 DGND2 G2

C2940.1uF C2940.1uF

C2820.1uF C2820.1uF

C2700.1uF C2700.1uF

C2750.1uF C2750.1uF

C2890.1uF C2890.1uF

C2870.1uF C2870.1uF

TV40

Prototyping Pad

TV40

Prototyping Pad

C2650.1uF C2650.1uF

C2760.1uF C2760.1uF

C2880.1uF C2880.1uF

C2900.1uF C2900.1uF

C2910.1uF C2910.1uF

C2790.1uF C2790.1uF

C2920.1uF C2920.1uF

C2800.1uF C2800.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GPIO04GPIO05GPIO06GPIO07GPIO08GPIO09GPIO10GPIO11GPIO12GPIO13GPIO14GPIO15

GPIO20GPIO21GPIO22GPIO23GPIO24GPIO25GPIO26GPIO27GPIO28GPIO29GPIO30GPIO31

GPIO16GPIO17GPIO18GPIO19

GPIO00GPIO01GPIO02GPIO03

TESTMODE0TESTMODE1TESTMODE2

PORT_CFG3PORT_CFG2PORT_CFG1PORT_CFG0

UPSTR_PSEL0

SSC_ISO_EN_nPP_BYPASS_nGEN1_n

UPSTR_PSEL1UPSTR_PSEL2

FAST_BRINGUP_n

UPSTR_PSEL3

PEX_JTAG_TMSPEX_JTAG_TCKPEX_JTAG_TRST_n

PEX_JTAG_TDIPEX_JTAG_TDO

NT_ENABLE_n

NT_UPSTR_PSEL2NT_UPSTR_PSEL3

NT_UPSTR_PSEL1NT_UPSTR_PSEL0

DEBUG_SEL0

PEX_EE_CK

PEX_EE_DIPEX_EE_DO

PEX_EE_CS_n

TESTMODE3

SERDES_MODE__EN_nPROBE_MODE_n

3.3VCC1

2.5VCC_A3.3VCC

3.3VCC3.3VCC

1.0VCC_A

1.0VCC

2.5VCC

3.3VCC3.3VCC

PEX_PERST_n[17,18,19,21,26]

GPIO00 [25,26]GPIO01 [25,26]GPIO02 [25,26]GPIO03 [25,26]GPIO04 [25,26]GPIO05 [25,26]GPIO06 [25,26]GPIO07 [25,26]GPIO08 [25,26]GPIO09 [25,26]GPIO10 [25,26]GPIO11 [25,26]GPIO12 [25,26]GPIO13 [25,26]GPIO14 [25,26]GPIO15 [25,26]GPIO16 [25,26]GPIO17 [25,26]GPIO18 [25,26]GPIO19 [25,26]GPIO20 [25,26]GPIO21 [25,26]GPIO22 [25,26]GPIO23 [25,26]GPIO24 [25,26]GPIO25 [25,26]GPIO26 [25,26]GPIO27 [25,26]GPIO28 [26]GPIO29 [25,26]GPIO30 [25,26]GPIO31 [26]

LN_GOOD_00_n [25,26]LN_GOOD_01_n [25,26]LN_GOOD_02_n [25,26]LN_GOOD_03_n [25,26]LN_GOOD_04_n [25,26]LN_GOOD_05_n [25,26]LN_GOOD_06_n [25,26]LN_GOOD_07_n [25,26]LN_GOOD_08_n [25,26]LN_GOOD_09_n [25,26]LN_GOOD_10_n [25,26]LN_GOOD_11_n [25,26]LN_GOOD_12_n [25,26]LN_GOOD_13_n [25,26]LN_GOOD_14_n [25,26]LN_GOOD_15_n [25,26]

NVM_VDDQ [23]PROCMON [25,26]PEX_INTA_n [26]FATAL_ERR_n [26]

TDIODE_p [23]TDIODE_n [23]SHPC_INT_n [21,26]

SPARE0 [25,26]SPARE1 [25,26]STRAP_NT_P2PEN# [25,26]STRAP_SMBUSEN# [25,26]

STRAP_UPCFG_TR_EN# [25,26]SPARE5 [25,26]

I2C_SCL0[26]I2C_SDA0[26]

I2C_SDA1[21]I2C_SCL1[21]

PROBE_MODE_n

I2C_ADDR0[25]I2C_ADDR1[25]I2C_ADDR2[25]

DEBUG_SEL0 [25]UPSTRM_PSEL3 [25]SSC_ISO_EN_n [6]

Title


Date: Sheet of

91-0131-000-A 0


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Date: Sheet of

91-0131-000-A 0


C


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Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

EEPROM

PEX8619 JTAG PORT

Place 1000pf close to the pins.Sprinkle 0.01uf around the chip.Sprinkle 1uf around the chip

I2C HEADERS

C105

1000pF

C105

1000pF

RN94R 4.7KRN94R 4.7K

12345 6 7 8

C152

1000pF

C152

1000pF

C106

0.01uF

C106

0.01uF

C119

1000pF

C119

1000pF

JP3

HDR 5X2

JP3

HDR 5X2

11 2 233 4 455 6 677 8 899 10 10

C136

0.01uF

C136

0.01uF

C129

0.01uF

C129

0.01uF


12345 6 7 8

C111

1000pF

C111

1000pF

R285

0 Shunt

R285

0 Shunt

123

C115

1000pF

C115

1000pF

C123

1uF

C123

1uF

C124

1uF

C124

1uFC130

0.01uF

C130

0.01uF

C104

1000pF

C104

1000pF

C107

0.01uF

C107

0.01uF

C120

1000pF

C120

1000pF

C98

1uF

C98

1uF


1234

8765

C127

1uF

C127

1uF

C147

1000pF

C147

1000pF

R286

0 Shunt

R286

0 Shunt

123


12345 6 7 8

TV47Prototyping PadTV47Prototyping Pad

RN3

4R 1K

RN3

4R 1K

1234 5

678

C91

1uF

C91

1uF

C145

1000pF

C145

1000pF

C150

1000pF

C150

1000pF

C112

1000pF

C112

1000pF

C116

1000pF

C116

1000pF

C143

1000pF

C143

1000pF

C108

1000pF

C108

1000pF

C134

0.01uF

C134

0.01uF

R287

0 Shunt

R287

0 Shunt

123

C121

1uF

C121

1uF

C100

0.01uF

C100

0.01uF

PEX 8619

U100B

PEX 8619

PEX 8619

U100B

PEX 8619

VS

S60

L3V

SS

59K

16V

SS

58K

13V

SS

57K

12V

SS

56K

11V

SS

55K

10V

SS

54K

9V

SS

53K

8V

SS

52K

7V

SS

51J1

2V

SS

50J1

1V

SS

49J1

0V

SS

48J9

VS

S47

J8V

SS

46J7

VS

S45

J6V

SS

44J3

VS

S42

H12

VS

S41

H11

VS

S43

H16

VS

S40

H10

VS

S39

H9

VS

S38

H8

VS

S37

H7

VS

S36

G12

VS

S35

G11

VS

S34

G10

VS

S33

G9

VS

S32

G8

VS

S31

G7

VS

S30

G5

VS

S29

G4

VS

S28

G3

VS

S27

G2

VS

S26

G1

VS

S25

F18

VS

S24

F17

VS

S23

F16

VS

S22

F15

VS

S21

F14

VS

S20

F10

VS

S19

F5V

SS

18E

12V

SS

17E

6V

SS

16D

12V

SS

15D

6V

SS

14C

12

VS

S11

C6

VS

S61

L7

VS

S63

L9

VS

S65

L11

VS

S67

M7

VS

S68

M8

VS

S70

M10

VS

S71

M11

VS

S62

L8

VS

S64

L10

VS

S66

L12

VS

S69

M9

VS

S72

M12

VS

S73

M14

VS

S74

M15

VS

S75

M16

VS

S76

M17

VS

S77

M18

VS

S78

N1

VS

S79

N2

VS

S80

N3

VS

S81

N4

VS

S82

N5

VS

S83

N9

VS

S84

N14

VS

S85

P7

VS

S86

P13

VS

S87

R7

VS

S88

R13

VS

S89

T7V

SS

90T9

VS

S91

T11

VS

S92

T13

VS

S93

U1

VD

D25

0F6

VD

D25

1F1

3V

DD

252

N6

VD

D25

3N

13

VD

D25

A0

F9V

DD

25A

1J1

3V

DD

25A

2K

6V

DD

25A

3N

10

VD

D10

_0F7

VD

D10

_1F1

1V

DD

10_2

F12

VD

D10

_3G

6V

DD

10_4

G13

VD

D10

_5H

6V

DD

10_6

L13

VD

D10

_7M

6V

DD

10_8

M13

VD

D10

_9N

7V

DD

10_1

0N

8V

DD

10_1

1N

12

VD

D10

A_0

C7

VD

D10

A_1

C9

VD

D10

A_2

C11

VD

D10

A_3

G16

PEX_PERST#P17PEX_NT_RESET#P16

STRAP_NT_UPSTRM_PORTSEL2R1STRAP_NT_UPSTRM_PORTSEL3P6

STRAP_NT_UPSTRM_PORTSEL1P2 STRAP_NT_UPSTRM_PORTSEL0P1 STRAP_NT_ENABLE#N18

STRAP_TESTMODE0V14

STRAP_FAST_BRINGUP#C2

STRAP_SERDES_MODE_EN#C4

STRAP_RESERVED17#F1

STRAP_DEBUG_SEL0N17

STRAP_PLL_BYPASS#R15

STRAP_PROBE_MODE#T17

STRAP_SSC_ISO_ENABLE#U3

STRAP_TESTMODE3U17

VD

D10

A_4

H3

VD

D10

A_5

J16

VD

D10

A_6

K3

VD

D10

A_7

L16

VD

D10

A_8

M3

VD

D10

A_9

T8V

DD

10A

_10

T10

VD

D10

A_1

1T1

2

VS

S0

A1

VS

S1

A2

VS

S2

A3

VS

S3

A6

VS

S4

A12

VS

S5

A18

VS

S6

B1

VS

S7

B6

VS

S8

B12

VS

S9

B18

VS

S10

C1

VS

S94

U7

VS

S95

U13

VS

S96

U18

VS

S97

V1

VS

S98

V2

VS

S99

V3

VS

S10

0V

7V

SS

101

V13

VS

S10

2V

17V

SS

103

V18

JTAG_TRST#D15JTAG_TCKB15JTAG_TMSC14JTAG_TDIE14JTAG_TDOC15

EE_SKR18EE_CSR17EE_DIN15EE_DON16

STRAP_PORTCFG1A4 STRAP_PORTCFG0A5

STRAP_PORTCFG3C13 STRAP_PORTCFG2B2

STRAP_UPSTRM_PORTSEL3E1

STRAP_UPSTRM_PORTSEL0E2

STRAP_UPSTRM_PORTSEL2F2 STRAP_UPSTRM_PORTSEL1F3

STRAP_TESTMODE1V15STRAP_TESTMODE2V16

I2C_ADDR2E18 I2C_ADDR1E17 I2C_ADDR0C18

I2C_SCL0C17

I2C_SDA1C16 I2C_SCL1B16

I2C_SDA0A17

PEX_LANE_GOOD8# B3

PEX_LANE_GOOD4# B17

PEX_LANE_GOOD6# D17PEX_LANE_GOOD5# D18

PEX_LANE_GOOD11# E5PEX_LANE_GOOD10# E13

PEX_LANE_GOOD7# E16

PEX_LANE_GOOD13# P3PEX_LANE_GOOD12# R2

PEX_LANE_GOOD14# T1PEX_LANE_GOOD15# T2

PEX_LANE_GOOD1# T14

GPIO13 V4

PEX_LANE_GOOD3# U15PEX_LANE_GOOD2# U16

PEX_LANE_GOOD9# A13

GPIO29 B4GPIO28 B5

GPIO25 B14GPIO26 C3GPIO27 C5

GPIO4 D1GPIO3 D2

GPIO1 D3

GPIO31 D4GPIO30 D5

GPIO23 D16

GPIO2 E3

GPIO0 E4

GPIO24 E15

GPIO5 F4

GPIO8 P4GPIO9 P5

GPIO16 P14

GPIO21 P15

GPIO7 R3

GPIO12 R6

GPIO19 R14GPIO20 R16

GPIO6 T3

GPIO18 T15GPIO17 T16

GPIO22 T18

GPIO10 U2GPIO11 U6

PEX_LANE_GOOD0# U14

GPIO14 V5GPIO15 V6

SPARE0 R4SPARE1 T4

STRAP_NT_P2P_EN# R5STRAP_SMBUS_EN# U4

STRAP_UPCFG_TIMER_EN# U5SPARE5 T5

PEX_INTA# P18N/C T6

FATAL_ERR# B13

THERMAL_DIODEp A14THERMAL_DIODEn A15

SHPC_INT# A16

STRAP_RESERVED16 D14

VS

S10

4D

13

VS

S12

C8

VS

S13

C10

C137

0.01uF

C137

0.01uF

C92

1uF

C92

1uF

C109

1000pF

C109

1000pF

C131

1000pF

C131

1000pF

C122

1uF

C122

1uF

C125

1uF

C125

1uF

R422.26K1%

R422.26K1%

C96

0.01uF

C96

0.01uF


12345 6 7 8

C139

1000pF

C139

1000pF

C133

0.01uF

C133

0.01uF

C117

1000pF

C117

1000pF

C128

1uF

C128

1uF

C148

1000pF

C148

1000pF

R442.26K1%

R442.26K1%

C93

1uF

C93

1uF


1234

8765

C101

0.01uF

C101

0.01uF

C132

1000pF

C132

1000pF

C151

1000pF

C151

1000pF

C113

1000pF

C113

1000pF

C97

0.01uF

C97

0.01uF


1234

8765

C144

1000pF

C144

1000pF

RN104R 4.7KRN104R 4.7K

12345 6 7 8


1234

8765

C135

0.01uF

C135

0.01uF

U19

AT25256A

U19

AT25256ASCLK 6

CS# 1SI 5

SO 2HOLD#7 VCC8

WP#3GND4

C102

0.01uF

C102

0.01uF

C94

1uF

C94

1uF


1234

8765

C138

0.01uF

C138

0.01uF

C118

1000pF

C118

1000pF

C140

1000pF

C140

1000pF

C89

1uF

C89

1uF

C110

1000pF

C110

1000pF

C126

1uF

C126

1uF

C146

1000pF

C146

1000pF


12345 6 7 8

C114

1000pF

C114

1000pF

C99

0.01uF

C99

0.01uF


1234

8765

C103

1000pF

C103

1000pF

C149

1000pF

C149

1000pF


1 2 3 45678

JP8

HEADER 2X2

JP8

HEADER 2X2

SCL 1GND2SDA 3NC4

C90

1uF

C90

1uF

C95

1uF

C95

1uF

C142

1000pF

C142

1000pF

C141

1000pF

C141

1000pF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PRSNT_n_SL2RCKp_SL2RCKn_SL2

PERST_n_SL2

RX0p_SL2RX0n_SL2

TX0p_SL2TX0n_SL2


PERST_n_SL1

RX0p_SL1RX0n_SL1

TX0p_SL1TX0n_SL1

3.3VCC

12V_SLT_2

3.3VCC_SLT_2_3 3.3VCC_SLT_2_3

3.3VCC

12V_SLT_1

3.3VCC_SLT_1 3.3VCC_SLT_1

PRSNT_n_SL2[26]

PERST_n_SL2 [26]


RX0p_SL2 [22]

TX0p_SL2[22]

RX0n_SL2 [22]

TX0n_SL2[22]

PRSNT_n_SL1[26]

PERST_n_SL1 [26]


RX0p_SL1 [22]

TX0p_SL1[22]

RX0n_SL1 [22]

TX0n_SL1[22]

Wake_n[10,11,12,13,14,15,16,26] Wake_n[10,11,12,13,14,15,16,26]

Title


Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

SLOT 02 SLOT 01

+C18222uF

+C18222uF

R202

4.7K

R202

4.7K

R201

4.7K

R201

4.7K

SLOT1

x16 PCI Express Contr

SLOT1


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11

+12V_0B1+12V_1B2+12V_2B3GND0B4SMCLKB5SMDATB6GND1B7+3.3V_0B8TRST#B93.3VAUXB10WAKE#B11

RSVD0B12

PETp0B14PETn0B15GND3B16PRSNT2#_0B17GND4B18PETp1B19PETn1B20GND5B21GND6B22PETp2B23PETn2B24GND7B25GND8B26PETp3B27PETn3B28GND9B29RSVD1B30

GND35 A12REFCLK+ A13REFCLK- A14

GND36 A15PERp0 A16PERn0 A17GND37 A18RSVD3 A19GND38 A20PERp1 A21PERn1 A22GND39 A23GND40 A24PERp2 A25PERn2 A26GND41 A27GND42 A28PERp3 A29PERn3 A30

GND2B13

GND43 A31RSVD4 A32RSVD5 A33GND44 A34PERp4 A35PERn4 A36GND45 A37GND46 A38PERp5 A39PERn5 A40GND47 A41GND48 A42PERp6 A43PERn6 A44GND49 A45GND50 A46PERp7 A47PERn7 A48GND51 A49RSVD6 A50GND52 A51PERp8 A52PERn8 A53GND53 A54GND54 A55PERp9 A56PERn9 A57GND55 A58GND56 A59

PERp10 A60

PRSNT2#_1B31GND10B32PETp4B33PETn4B34GND11B35GND12B36PETp5B37PETn5B38GND13B39GND14B40PETp6B41PETn6B42GND15B43GND16B44PETp7B45PETn7B46GND17B47PRSNT2#_2B48GND18B49PETp8B50PETn8B51GND19B52GND20B53PETp9B54PETn9B55GND21B56GND22B57PETp10B58PETn10B59GND23B60

PERn10 A61GND57 A62GND58 A63

PERp11 A64PERn11 A65GND59 A66GND60 A67




PERp15 A80PERn15 A81GND67 A82

GND24B61PETp11B62PETn11B63GND25B64GND26B65PETp12B66PETn12B67GND27B68GND28B69PETp13B70PETn13B71GND29B72GND30B73PETp14B74PETn14B75GND31B76GND32B77PETp15B78PETn15B79GND33B80PRSNT2#_4B81RSVD2B82

SLOT2


SLOT2


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









+ C184

22uF

+ C184

22uF

+ C183

22uF

+ C183

22uF

+C18122uF

+C18122uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


PERST_n_SL4

RX0p_SL4RX0n_SL4

TX0p_SL4TX0n_SL4


PERST_n_SL3

RX0p_SL3RX0n_SL3

TX0p_SL3TX0n_SL3

TX1p_SL4TX1n_SL4

TX2p_SL4TX2n_SL4

TX3p_SL4TX3n_SL4

RX1p_SL4RX1n_SL4

RX2p_SL4RX2n_SL4

RX3p_SL4RX3n_SL4

3.3VCC

12V_SLT_4


3.3VCC

12V_SLT_3


PRSNT_n_SL4[26]

PERST_n_SL4 [26]


RX0p_SL4 [22]

TX0p_SL4[22]

RX0n_SL4 [22]

TX0n_SL4[22]

PRSNT_n_SL3[26]

PERST_n_SL3 [26]


RX0p_SL3 [22]

TX0p_SL3[22]

RX0n_SL3 [22]

TX0n_SL3[22]

TX3p_SL4[22]TX3n_SL4[22]



RX3n_SL4 [22]

RX1p_SL4 [22]RX1n_SL4 [22]

RX2p_SL4 [22]RX2n_SL4 [22]

RX3p_SL4 [22]

Wake_n[9,11,12,13,14,15,16,26] Wake_n[9,11,12,13,14,15,16,26]

Title


Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

SLOT 04 Pin1&2 of J2 should be placedon the refclk traces and closeto SLOT2 without stubs


SLOT3


SLOT3


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









SLOT4


SLOT4


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









+ C188

22uF

+ C188

22uF

+ C187

22uF

+ C187

22uF

+C18522uF

+C18522uF

+C18622uF

+C18622uF

R203

4.7K

R203

4.7K

R204

4.7K

R204

4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


PERST_n_SL6

RX0p_SL6RX0n_SL6

TX0p_SL6TX0n_SL6


PERST_n_SL5

RX0p_SL5RX0n_SL5

TX0p_SL5TX0n_SL5

3.3VCC

12V_SLT_6


3.3VCC

12V_SLT_5


PRSNT_n_SL6[26]

PERST_n_SL6 [26]


RX0p_SL6 [22]

TX0p_SL6[22]

RX0n_SL6 [22]

TX0n_SL6[22]

PRSNT_n_SL5[26]

PERST_n_SL5 [26]


RX0p_SL5 [22]

TX0p_SL5[22]

RX0n_SL5 [22]

TX0n_SL5[22]

Wake_n[9,10,12,13,14,15,16,26] Wake_n[9,10,12,13,14,15,16,26]

Title


Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK



+ C192

22uF

+ C192

22uF

+ C191

22uF

+ C191

22uF

+C18922uF

+C18922uF

+C19022uF

+C19022uF

R206

4.7K

R206

4.7K

R205

4.7K

R205

4.7K

SLOT5


SLOT5


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









SLOT6


SLOT6


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TX1p_SL8TX1n_SL8

TX2p_SL8TX2n_SL8

TX3p_SL8TX3n_SL8


PERST_n_SL8

RX1p_SL8RX1n_SL8

RX2p_SL8RX2n_SL8

RX3p_SL8RX3n_SL8

RX0p_SL8RX0n_SL8

TX0p_SL8TX0n_SL8


PERST_n_SL7

RX0p_SL7RX0n_SL7

TX0p_SL7TX0n_SL7

3.3VCC

12V_SLT_8_HP

3.3VCC_SLT_8_HP 3.3VCC_SLT_8_HP

3.3VCC

12V_SLT_7


TX3p_SL8[22]

RX3n_SL8 [22]

PRSNT_n_SL8[21,26]

TX3n_SL8[22]

PERST_n_SL8 [21]


RX0p_SL8 [22]

TX0p_SL8[22]

RX0n_SL8 [22]

TX0n_SL8[22]

RX1p_SL8 [22]

TX1p_SL8[22]

RX1n_SL8 [22]

TX1n_SL8[22]

RX2p_SL8 [22]

TX2p_SL8[22]

RX2n_SL8 [22]

TX2n_SL8[22]

RX3p_SL8 [22]

PRSNT_n_SL7[26]

PERST_n_SL7 [26]


RX0p_SL7 [22]

TX0p_SL7[22]

RX0n_SL7 [22]

TX0n_SL7[22]

Wake_n[9,10,11,13,14,15,16,26]

Wake_n[9,10,11,13,14,15,16,26]

Title


Date: Sheet of

91-0131-000-A 0


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Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

SLOT 08 SLOT 07

SLOT7


SLOT7


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









SLOT8


SLOT8


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









+ C196

22uF

+ C196

22uF

+ C195

22uF

+ C195

22uF

+C19322uF

+C19322uF

+C19422uF

+C19422uF

R207

4.7K

R207

4.7K

R208

4.7K

R208

4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


PERST_n_SL10

RX0p_SL10RX0n_SL10

TX0p_SL10TX0n_SL10


PERST_n_SL9

RX0p_SL9RX0n_SL9

TX0p_SL9TX0n_SL9

3.3VCC

12V_SLT_10

3.3VCC_SLT_10_11 3.3VCC_SLT_10_11

3.3VCC

12V_SLT_9

3.3VCC_SLT_9 3.3VCC_SLT_9

PRSNT_n_SL10[26]

PERST_n_SL10 [26]


RX0p_SL10 [22]

TX0p_SL10[22]

RX0n_SL10 [22]

TX0n_SL10[22]

PRSNT_n_SL9[26]

PERST_n_SL9 [26]


RX0p_SL9 [22]

TX0p_SL9[22]

RX0n_SL9 [22]

TX0n_SL9[22]

Wake_n[9,10,11,12,14,15,16,26] Wake_n[9,10,11,12,14,15,16,26]

Title


Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

SLOT 10 SLOT 09

SLOT9


SLOT9


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









SLOT10


SLOT10


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









+ C200

22uF

+ C200

22uF

+ C199

22uF

+ C199

22uF

+C19722uF

+C19722uF

+C19822uF

+C19822uF

R210

4.7K

R210

4.7K

R209

4.7K

R209

4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


PERST_n_SL12

RX0p_SL12RX0n_SL12

TX0p_SL12TX0n_SL12


PERST_n_SL11

RX0p_SL11RX0n_SL11

TX0p_SL11TX0n_SL11

3.3VCC

12V_SLT_12

3.3VCC_SLT_12_13 3.3VCC_SLT_12_13

3.3VCC

12V_SLT_11

3.3VCC_SLT_10_11 3.3VCC_SLT_10_11

PRSNT_n_SL12[26]

PERST_n_SL12 [26]


RX0p_SL12 [7]

TX0p_SL12[7]

RX0n_SL12 [7]

TX0n_SL12[7]

PRSNT_n_SL11[26]

PERST_n_SL11 [26]


RX0p_SL11 [22]

TX0p_SL11[22]

RX0n_SL11 [22]

TX0n_SL11[22]

Wake_n[9,10,11,12,13,15,16,26] Wake_n[9,10,11,12,13,15,16,26]

Title


Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

SLOT 12 SLOT 11

SLOT11


SLOT11


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









SLOT12


SLOT12


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









+ C204

22uF

+ C204

22uF

+ C203

22uF

+ C203

22uF

+C20122uF

+C20122uF

+C20222uF

+C20222uF

R211

4.7K

R211

4.7K

R212

4.7K

R212

4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


PERST_n_SL14

RX0p_SL14RX0n_SL14

TX0p_SL14TX0n_SL14


PERST_n_SL13

RX0p_SL13RX0n_SL13

TX0p_SL13TX0n_SL13

3.3VCC

12V_SLT_14

3.3VCC_SLT_14_15 3.3VCC_SLT_14_15

3.3VCC

12V_SLT_13

3.3VCC_SLT_12_13 3.3VCC_SLT_12_13

PRSNT_n_SL14[26]

PERST_n_SL14 [26]


RX0p_SL14 [7]

TX0p_SL14[7]

RX0n_SL14 [7]

TX0n_SL14[7]

PRSNT_n_SL13[26]

PERST_n_SL13 [26]


RX0p_SL13 [7]

TX0p_SL13[7]

RX0n_SL13 [7]

TX0n_SL13[7]

Wake_n[9,10,11,12,13,14,16,26] Wake_n[9,10,11,12,13,14,16,26]

Title


Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

SLOT 14 SLOT 13

+C20522uF

+C20522uF

+C20622uF

+C20622uF

R214

4.7K

R214

4.7K

R213

4.7K

R213

4.7K

SLOT13


SLOT13


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









SLOT14


SLOT14


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









+ C208

22uF

+ C208

22uF

+ C207

22uF

+ C207

22uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


PERST_n_SL15

RX0p_SL15RX0n_SL15

TX0p_SL15TX0n_SL15

3.3VCC

12V_SLT_15

3.3VCC_SLT_14_15 3.3VCC_SLT_14_15

PRSNT_n_SL15[26]

PERST_n_SL15 [26]


RX0p_SL15 [7]

TX0p_SL15[7]

RX0n_SL15 [7]

TX0n_SL15[7]

CREFCLKRECEPT0_n[5]CREFCLKRECEPT0_p[5]

CPWRON[26]CPRSNTN[26]

TX3n_PCIe_Cable[22]TX3p_PCIe_Cable[22]








RX3n_PCIe_Cable [22]RX3p_PCIe_Cable [22]

RX2p_PCIe_Cable [22]RX2n_PCIe_Cable [22]







CPERST_n [4]

Wake_n[9,10,11,12,13,14,15,26]

Title


Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

SLOT 15

J6

PCIex4_Cab-Con

J6

PCIex4_Cab-Con

GND7 B1GND6A1 PERp0 B2PERn0 B3GND8 B4PERp1 B5PERn1 B6GND9 B7PERp2 B8PERn2 B9GND10 B10PERp3 B11PERn3 B12GND11 B13PWR0 B14PWR1 B15PWR_RTN0 B16PWR_RTN1 B17CWAKE# B18CPERST# B19

PETp0A2 PETn0A3 GND5A4 PETp1A5 PETn1A6 GND4A7 PETp2A8 PETn2A9 GND3A10 PETp3A11 PETn3A12 GND1A13 CREFCLKpA14 CREFCLKnA15 GND0A16 SB_RTNA17 CPRSNT#A18 CPWRONA19 TPV4

Prototyping Pad

TPV4

Prototyping Pad

+ C210

22uF

+ C210

22uF

TPV2

Prototyping Pad

TPV2

Prototyping Pad

CAGE1

cage

CAGE1

cage

112233445566778899

CAGE2

cage

CAGE2

cage

112233445566778899

TV30

Prototyping Pad

TV30

Prototyping Pad

+C20922uF

+C20922uF

TV32

Prototyping Pad

TV32

Prototyping Pad

J5

PCIex4_Cab-Con

J5

PCIex4_Cab-Con

GND7 B1GND6A1 PERp0 B2PERn0 B3GND8 B4PERp1 B5PERn1 B6GND9 B7PERp2 B8PERn2 B9GND10 B10PERp3 B11PERn3 B12GND11 B13PWR0 B14PWR1 B15PWR_RTN0 B16PWR_RTN1 B17CWAKE# B18CPERST# B19

PETp0A2 PETn0A3 GND5A4 PETp1A5 PETn1A6 GND4A7 PETp2A8 PETn2A9 GND3A10 PETp3A11 PETn3A12 GND1A13 CREFCLKpA14 CREFCLKnA15 GND0A16 SB_RTNA17 CPRSNT#A18 CPWRONA19

TV31

Prototyping Pad

TV31

Prototyping Pad

R215

4.7K

R215

4.7K

TPV3

Prototyping Pad

TPV3

Prototyping Pad


SLOT15


SLOT15


PRSNT1# A1+12V_3 A2+12V_4 A3GND34 A4

TCLK A5TDI A6

TDO A7TMS A8

+3.3V_2 A9+3.3V_1 A10PERST# A11


RSVD0B12




GND2B13


PERp10 A60









TV29

Prototyping Pad

TV29

Prototyping Pad

TPV1

Prototyping Pad

TPV1

Prototyping Pad

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC13.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1 3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

PEX_PERST_n[8,18,19,21,26]

LEDSET1_DATA[26]

LEDSET1_CLK[26]

LEDSET0_DATA[26]

LEDSET0_CLK[26]

LEDSET7_CLK[26]

LEDSET7_DATA[26]

Title


Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

LEDSET1LEDSET1LEDSET0 LEDSET0

Port ID3

Port ID2

Port ID1

USERDEBUG1 Port ID6 Port ID4

Port ID7 Port ID5

Port STS3

Port STS2 USERDEBUG0

Port STS1Port STS7

Port STS6 Port STS4

Port STS5

Place USERDEBUG0 and USERDEBUG1 atthe top right of the Board.USERDEBUG0 is Unit Digit andUSERDEBUG1 is tens digit. Place itclose to the ATX24 power connector

Place the USERDEBUG[1:0] relatedcomponents close to the ATXpower connector

subpart F not used

U92E74LVC04/SOU92E74LVC04/SO

11 10

RN28

220

RN28

220

123456789

10111213141516

RN29

220

RN29

220

123456789

10111213141516

U80B74LVC04/SOU80B74LVC04/SO

3 4

C215

0.01uF

C215

0.01uF

C224

0.01uF

C224

0.01uF

DS15RedDS15Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18U42

MM74HC164

U42

MM74HC164

GN

D7

CLK8

CLR9

VC

C14

QA 3QB 4QC 5QD 6QE 10QF 11QG 12QH 13

A1B2

DS3RedDS3Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

U80A

74LVC04/SO

U80A

74LVC04/SO

1 2

147

U34

MM74HC164

U34

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

C218

0.01uF

C218

0.01uF

C225

0.01uF

C225

0.01uF

U33

MM74HC164

U33

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

RN14

220

RN14

220

123456789

10111213141516

RN18

220

RN18

220

123456789

10111213141516

DS12RedDS12Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

U30

MM74HC164

U30

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

C220

0.01uF

C220

0.01uF

U40

MM74HC164

U40

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS1RedDS1Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

C212

0.01uF

C212

0.01uF

DS10RedDS10Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

C223

0.01uF

C223

0.01uF

U36

MM74HC164

U36

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

C213

0.01uF

C213

0.01uF

C221

0.01uF

C221

0.01uF


11 10

DS5RedDS5Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

U37

MM74HC164

U37

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

U80D74LVC04/SOU80D74LVC04/SO

9 8

C214

0.01uF

C214

0.01uF

DS14RedDS14Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

C219

0.01uF

C219

0.01uF

C226

0.01uF

C226

0.01uF

DS16RedDS16Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

DS6RedDS6Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

C211

0.01uF

C211

0.01uF

C222

0.01uF

C222

0.01uF

RN26

220

RN26

220

123456789

10111213141516

RN20

220

RN20

220

123456789

10111213141516

RN23

220

RN23

220

123456789

10111213141516

DS9RedDS9Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

RN19

220

RN19

220

123456789

10111213141516

RN27

220

RN27

220

123456789

10111213141516

RN16

220

RN16

220

123456789

10111213141516

U29

MM74HC164

U29

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS7RedDS7Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

RN22

220

RN22

220

123456789

10111213141516

U32

MM74HC164

U32

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

U43

MM74HC164

U43

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS2RedDS2Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

DS11RedDS11Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

DS13RedDS13Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

U35

MM74HC164

U35

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS4RedDS4Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

U41

MM74HC164

U41

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

RN15

220

RN15

220

123456789

10111213141516

U39

MM74HC164

U39

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

C216

0.01uF

C216

0.01uF

RN17

220

RN17

220

123456789

10111213141516

RN24

220

RN24

220

123456789

10111213141516

U44

MM74HC164

U44

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

RN21

220

RN21

220

123456789

10111213141516

U80C74LVC04/SOU80C74LVC04/SO

5 6

RN25

220

RN25

220

123456789

10111213141516

U38

MM74HC164

U38

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

U31

MM74HC164

U31

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

C217

0.01uF

C217

0.01uF

DS8RedDS8Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3.3VCC13.3VCC13.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC13.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1 3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

PEX_PERST_n[8,17,19,21,26]

LEDSET3_DATA[26]

LEDSET3_CLK[26]

LEDSET2_DATA[26]

LEDSET2_CLK[26]

Title


Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

Port ID11

Port ID10

Port ID9

Port ID8

Port ID15

Port ID14

Port ID13

Port ID12

Port STS11

Port STS10

Port STS9

Port STS8

Port STS15

Port STS14 Port STS12

Port STS13

LEDSET3LEDSET3

LEDSET2 LEDSET2

subpart F not used

C235

0.01uF

C235

0.01uF

C240

0.01uF

C240

0.01uF

RN42

220

RN42

220

123456789

10111213141516

C227

0.01uF

C227

0.01uF

C242

0.01uF

C242

0.01uF

U50

MM74HC164

U50

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS29RedDS29Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

RN38

220

RN38

220

123456789

10111213141516

U58

MM74HC164

U58

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS27RedDS27Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18RN39

220

RN39

220

123456789

10111213141516

U85A74LVC04/SO

U85A74LVC04/SO

1 2

147

C241

0.01uF

C241

0.01uF

U45

MM74HC164

U45

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

U85B74LVC04/SOU85B74LVC04/SO

3 4


9 8

RN35

220

RN35

220

123456789

10111213141516

C239

0.01uF

C239

0.01uF

RN32

220

RN32

220

123456789

10111213141516

U53

MM74HC164

U53

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

RN44

220

RN44

220

123456789

10111213141516

U46

MM74HC164

U46

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

C230

0.01uF

C230

0.01uF

U59

MM74HC164

U59

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

RN40

220

RN40

220

123456789

10111213141516

RN31

220

RN31

220

123456789

10111213141516

RN37

220

RN37

220

123456789

10111213141516

U56

MM74HC164

U56

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS31RedDS31Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

U48

MM74HC164

U48

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS22RedDS22Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

C234

0.01uF

C234

0.01uF

U47

MM74HC164

U47

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS18RedDS18Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

U60

MM74HC164

U60

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

RN45

220

RN45

220

123456789

10111213141516

C238

0.01uF

C238

0.01uF

U54

MM74HC164

U54

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

U85C74LVC04/SO

U85C74LVC04/SO

5 6

DS26RedDS26Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

U49

MM74HC164

U49

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

RN34

220

RN34

220

123456789

10111213141516

DS23RedDS23Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

DS28RedDS28Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

U51

MM74HC164

U51

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

RN36

220

RN36

220

123456789

10111213141516

U57

MM74HC164

U57

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS30RedDS30Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

RN30

220

RN30

220

123456789

10111213141516

DS20RedDS20Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

C232

0.01uF

C232

0.01uF

RN43

220

RN43

220

123456789

10111213141516

C236

0.01uF

C236

0.01uF

DS19RedDS19Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

C233

0.01uF

C233

0.01uF

DS32RedDS32Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

DS17RedDS17Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

DS25RedDS25Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18


11 10

RN33

220

RN33

220

123456789

10111213141516

DS24RedDS24Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18U52

MM74HC164

U52

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

C228

0.01uF

C228

0.01uF

C231

0.01uF

C231

0.01uF

RN41

220

RN41

220

123456789

10111213141516

C237

0.01uF

C237

0.01uF

DS21RedDS21Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

C229

0.01uF

C229

0.01uF

U55

MM74HC164

U55

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC13.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

PEX_LN2_2p5G [20]PEX_LN2_5p0G [20]


PEX_LN12_2p5G [20]PEX_LN12_5p0G [20]



PEX_LN13_2p5G [20]PEX_LN13_5p0G [20]

PEX_LN0_2p5G [20]


PEX_LN14_2p5G [20]PEX_LN14_5p0G [20]


LEDSET6_CLK[26]

PEX_LN0_5p0G [20]


PEX_LN15_2p5G [20]PEX_LN15_5p0G [20]

PEX_LN10_2p5G [20]

PEX_PERST_n[8,17,18,21,26]

PEX_LN10_5p0G [20]

LEDSET5_DATA[26]

LEDSET5_CLK[26]

LEDSET4_DATA[26]

LEDSET4_CLK[26]



PEX_LN11_2p5G [20]PEX_LN11_5p0G [20]

LEDSET6_DATA[26]

Title


Date: Sheet of

91-0131-000-A 0


C


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Date: Sheet of

91-0131-000-A 0


C


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Date: Sheet of

91-0131-000-A 0


C


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8619 Base Board RDK

LEDSET4Port RCPT1 ID

Port RCPT0 ID

Port RCPT1 STS

Port RCPT0 STS

TEMPERATURE100

TEMPERATURE10

TEMPERATURE1

TEMPERATURE0.1

LEDSET6LEDSET5

The above FOUR 7Segs should Be placed inaccordance with their Name.TEMPERATURE.01 is the LSD andTEMPERATURE100 is the MSD.

U69

MM74HC164

U69

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

U91C74LVC04/SO

U91C74LVC04/SO

5 6

RN49

220

RN49

220

123456789

10111213141516


9 8

U62

MM74HC164

U62

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

C246

0.01uF

C246

0.01uF

RN48

220

RN48

220

123456789

10111213141516

RN53

220

RN53

220

123456789

10111213141516

DS33RedDS33Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

U83

MM74HC164

U83

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

C248

0.01uF

C248

0.01uF

DS38RedDS38Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

C311

0.01uF

C311

0.01uF

U64

MM74HC164

U64

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

C249

0.01uF

C249

0.01uF

U92A

74LVC04/SO

U92A

74LVC04/SO

1 2

147

RN47

220

RN47

220

123456789

10111213141516

U84

MM74HC164

U84

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS40RedDS40Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

RN51

220

RN51

220

123456789

10111213141516

C247

0.01uF

C247

0.01uF

C244

0.01uF

C244

0.01uF

U63

MM74HC164

U63

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2


9 8

C245

0.01uF

C245

0.01uF

U92F74LVC04/SOU92F74LVC04/SO

13 12

U66

MM74HC164

U66

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS35RedDS35Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

U67

MM74HC164

U67

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

U87A74LVC04/SO

U87A74LVC04/SO

1 2

147

DS37RedDS37Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

C312

0.01uF

C312

0.01uF

U88

MM74HC164

U88

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

C243

0.01uF

C243

0.01uF

U92B

74LVC04/SO

U92B

74LVC04/SO

3 4

C313

0.01uF

C313

0.01uF

RN50

220

RN50

220

123456789

10111213141516

DS34RedDS34Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

U68

MM74HC164

U68

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

RN46

220

RN46

220

123456789

10111213141516

C314

0.01uF

C314

0.01uF

U89

MM74HC164

U89

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

DS39RedDS39Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

DS36RedDS36Red

A7B6C4D2E1F9G10DP5

AN

OD

E0

3A

NO

DE

18

C250

0.01uF

C250

0.01uF

U65

MM74HC164

U65

MM74HC164

GN

D7

CLK8

CLR9

VC

C14


A1B2

RN52

220

RN52

220

123456789

10111213141516

U91A74LVC04/SO

U91A74LVC04/SO

1 2

147

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

PEX_LN6_2p5G[19]

PEX_LN6_5p0G[19]

PEX_LN7_2p5G[19]

PEX_LN7_5p0G[19]

PEX_LN4_2p5G[19]

PEX_LN4_5p0G[19]

PEX_LN5_2p5G[19]

PEX_LN5_5p0G[19]

PEX_LN10_2p5G[19]

PEX_LN10_5p0G[19]

PEX_LN11_2p5G[19]

PEX_LN11_5p0G[19]

PEX_LN8_2p5G[19]

PEX_LN8_5p0G[19]

PEX_LN9_2p5G[19]

PEX_LN9_5p0G[19]

PEX_LN14_2p5G[19]

PEX_LN14_5p0G[19]

PEX_LN15_2p5G[19]

PEX_LN15_5p0G[19]

PEX_LN12_2p5G[19]

PEX_LN12_5p0G[19]

PEX_LN13_2p5G[19]

PEX_LN13_5p0G[19]

PEX_LN2_2p5G[19]

PEX_LN2_5p0G[19]

PEX_LN3_2p5G[19]

PEX_LN3_5p0G[19]

PEX_LN0_2p5G[19]

PEX_LN0_5p0G[19]

PEX_LN1_2p5G[19]

PEX_LN1_5p0G[19]

Title


Date: Sheet of

91-0131-000-A 0


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Date: Sheet of

91-0131-000-A 0


C


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Date: Sheet of

91-0131-000-A 0


C


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8619 Base Board RDK

Except for PEX_LN0_xpxG LED all ofthe LEDs on this page are associatedto slots. Place them accordingly withthe Port IDx(x) and Port STSx(x). ThePEX_LN0_XpxG should be placed withthe close to Port ID/Port STS LEDfor the PCIe Receptacle

R230390R230390

GY

D19

GREEN_AMBER_LED

GY

D19

GREEN_AMBER_LED

21

43

R241390R241390

R235390R235390

R225390R225390

R247390R247390

R217390R217390

GR

D12

GREEN_AMBER_LED

GR

D12

GREEN_AMBER_LED

21

43

R240390R240390

R224390R224390

GY

D20

GREEN_AMBER_LED

GY

D20

GREEN_AMBER_LED

21

43

GY

D25

GREEN_AMBER_LED

GY

D25

GREEN_AMBER_LED

21

43

R234390R234390

R245390R245390

R216390R216390

R227390R227390

R221390R221390

GY

D26

GREEN_AMBER_LED

GY

D26

GREEN_AMBER_LED

21

43

R246390R246390

R244390R244390

GY

D22

GREEN_AMBER_LED

GY

D22

GREEN_AMBER_LED

21

43

R226390R226390

GY

D13

GREEN_AMBER_LED

GY

D13

GREEN_AMBER_LED

21

43

GY

D27

GREEN_AMBER_LED

GY

D27

GREEN_AMBER_LED

21

43

R220390R220390

R223390R223390

R243390R243390

GY

D21

GREEN_AMBER_LED

GY

D21

GREEN_AMBER_LED

21

43

GY

D23

GREEN_AMBER_LED

GY

D23

GREEN_AMBER_LED

21

43

GY

D14

GREEN_AMBER_LED

GY

D14

GREEN_AMBER_LED

21

43

GY

D24

GREEN_AMBER_LED

GY

D24

GREEN_AMBER_LED

21

43

R222390R222390

GY

D15

GREEN_AMBER_LED

GY

D15

GREEN_AMBER_LED

21

43

R233390R233390

R242390R242390

R229390R229390

GY

D16

GREEN_AMBER_LED

GY

D16

GREEN_AMBER_LED

21

43

R239390R239390

R232390R232390

GY

D17

GREEN_AMBER_LED

GY

D17

GREEN_AMBER_LED

21

43

R237390R237390

R219390R219390

R228390R228390

R238390R238390

R231390R231390

GY

D18

GREEN_AMBER_LED

GY

D18

GREEN_AMBER_LED

21

43

R236390R236390

R218390R218390

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

D3_2

INTERLOCK_SD4_2

V_4

PERST#_S

T_4

PEX_PERST_nCLKEN#_S

12VG_4

AD0_3

MRLI#_S

GPIO_S

PWREN_5

FAULT#_4

AD1_3

VS2_

4

CLKEN_n_SL8

PWRGOOD_S

PERST_n_SL8

AD2_3

PWRFLT#_S

12VSENSE_4

IS1_4

3VSENSE_4

IS_4

I2C_SCL1I2C_SDA1

HP_SL8_CTL

I2C_SCL1

PWRLED#_SATNLED#_SPWREN_SCLKEN#_SPERST#_S

SLOT0_3SLOT1_3SLOT2_3

VS1_

4

SLOT3_3PRSNT_n_SL8MRLI#_SBUTTONI#_SPWRFLT#_SPWRGOOD_S

PWREN_S

SHPC_INT_n

D5_1

3VG_4

D2_

2

D1_

2

3.3VCC

3.3VCC

3.3VCC

3.3VCC

12V_A

12V_SLT_8_HP

3.3VCC_SLT_8

3.3VCC_SLT_8_HP

3.3VCC

3.3VCC

3.3VCC

3.3VCC

3.3VCC

3.3VCC

3.3VCC_SLT_8_HP12V_SLT_8_HP

PEX_PERST_n[8,17,18,19,26] PERST_n_SL8 [12]

I2C_SCL1[8]I2C_SDA1[8]

PRSNT_n_SL8 [12,26]SHPC_INT_n[8,26]

CLKEN_SL8 [26]

Title


Date: Sheet of

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Date: Sheet of

91-0131-000-A 0


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Date: Sheet of

91-0131-000-A 0


C


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8619 Base Board RDK

To demonstrate the serial hot plug function of PEX 8618 requires the chip to boot with EEPROM and sets both pos. 1 and 2 of SW3 to "on" position.

SW2Default Settings1: off (disable MRL#_S)2: off (disable Serial HP)

SERIAL HOT PLUG CIRCUIT FOR SLOT 8

R267

51

R267

51

R250

13.7K 1%

R250

13.7K 1%

D29

GREEN

D29

GREEN

21

R264 0.02 1%R264 0.02 1%

D30

GREEN

D30

GREEN

21

Q2

IRF7470PBF

Q2

IRF7470PBF

D0 5D1 6D2 7D3 8

S01S12S23

G4

D31 GREEND31 GREEN21

R253

150

R253

150

R262 2KR262 2K R263 2KR263 2K

C2550.1uF

C2550.1uF

R269 0R269 0

R274

4.7K

R274

4.7K

U71

MAX7311AUG

U71

MAX7311AUG

SCL22

AD23

AD021AD12

SDA23

V+24

INT#1

GND12

IO0 4IO1 5IO2 6IO3 7IO4 8IO5 9IO6 10IO7 11IO8 13IO9 14

IO10 15IO11 16IO12 17IO13 18IO14 19IO15 20

TP1

Prototyping Pad

TP1

Prototyping Pad

R266 4.7KR266 4.7K

R273

4.7K

R273

4.7K

SW10

SW DIP-4

SW10

SW DIP-4

1234

8765

R248

100K 1%

R248

100K 1%

D32

GREEN

D32

GREEN

2 1

R256

150

R256

150

R259 4.7KR259 4.7K

ON

SW11

SW DIP-2

ON

SW11

SW DIP-2

12

43

U70

TPS2311PW

U70

TPS2311PW

GATE11 GATE2 2

DGND3 TIMER 4

AGND8

DISCH120 DISCH2 19

ENABLE18

FAULT# 16

IN111 IN2 12

ISENSE110 ISENSE2 9

ISET115 ISET2 14

PWRGD1# 17

PWRGD2# 13

VREG5

VSENSE17 VSENSE2 6

U72

SN74LVC157APW

U72

SN74LVC157APW

2A5 VC

C16

1A21B3

4B13

GN

D8

4A14 3B10

2B63A11

1Y 42Y 73Y 94Y 12

A#/B1 G# 15

R251

20K 1%

R251

20K 1%

R255

150

R255

150

R271 4.7KR271 4.7K

C256

0.1uF

C256

0.1uF

R265 4.7KR265 4.7K

U92C74LVC04/SO

U92C74LVC04/SO

5 6

R254 1KR254 1K

R272 4.7KR272 4.7K

R261 0.02 1%R261 0.02 1%

R260 4.7KR260 4.7K

S2

SW PUSHBUTTON

S2

SW PUSHBUTTON

134 2

C252 0.1uFC252 0.1uF

C253 NLC253 NL

R249

12.4K 1%

R249

12.4K 1%

C251 0.1uFC251 0.1uF

R268 4.7KR268 4.7K

D28 GREEND28 GREEN21

R258 1KR258 1K

Q1

IRF7470PBF

Q1

IRF7470PBF

D05D16D27D38

S0 1S1 2S2 3

G 4

R252

1.2K

R252

1.2K

R257 1KR257 1K

C254 NLC254 NL

C258

0.1uF

C258

0.1uF

R270

4.7K

R270

4.7K

RN54

4R 4.7K

RN54

4R 4.7K

12345

678

C257

1uF

C257

1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3.3VCC13.3VCC13.3VCC1

RECP0_CFGID1[26]RECP0_CFGID0[26]RECP0_PRES_n[26]



TX0p_RECEPT1[7]

TX0n_RECEPT1[7]

TX1p_RECEPT1[7]

TX1n_RECEPT1[7]

TX2p_RECEPT1[7]

TX2n_RECEPT1[7]

TX3p_RECEPT1[7]

TX3n_RECEPT1[7]

TX0p_RECEPT3[7]

TX0n_RECEPT3[7]

TX1p_RECEPT3[7]

TX1n_RECEPT3[7]

TX2p_RECEPT3[7]

TX2n_RECEPT3[7]

TX3p_RECEPT3[7]

TX3n_RECEPT3[7]

TX0p_RECEPT2[7]

TX0n_RECEPT2[7]

TX1p_RECEPT2[7]

TX1n_RECEPT2[7]

TX2p_RECEPT2[7]

TX2n_RECEPT2[7]

TX3p_RECEPT2[7]

TX3n_RECEPT2[7]

RX0p_RECEPT1 [7]

RX0n_RECEPT1 [7]

RX1p_RECEPT1 [7]

RX1n_RECEPT1 [7]

RX2p_RECEPT1 [7]

RX2n_RECEPT1 [7]

RX3p_RECEPT1 [7]

RX3n_RECEPT1 [7]

RX1p_RECEPT2 [7]

RX1n_RECEPT2 [7]

RX2p_RECEPT2 [7]

RX2n_RECEPT2 [7]

RX3p_RECEPT2 [7]

RX3n_RECEPT2 [7]

RX0p_RECEPT2 [7]

RX0n_RECEPT2 [7]

RX1p_RECEPT3 [7]

RX1n_RECEPT3 [7]

RX2p_RECEPT3 [7]

RX2n_RECEPT3 [7]

RX3p_RECEPT3 [7]

RX3n_RECEPT3 [7]

RX0p_RECEPT3 [7]

RX0n_RECEPT3 [7]

RX0p_PCIe_Cable[16]

RX0n_PCIe_Cable[16]

RX1n_PCIe_Cable[16]

RX1p_PCIe_Cable[16]

RX2p_PCIe_Cable[16]

RX2n_PCIe_Cable[16]

RX3n_PCIe_Cable[16]

RX3p_PCIe_Cable[16]

RX0p_SL8[12]

RX0n_SL8[12]

RX1p_SL8[12]

RX1n_SL8[12]

RX2p_SL8[12]

RX2n_SL8[12]

RX3p_SL8[12]

RX3n_SL8[12]

TX0p_PCIe_Cable [16]

TX0n_PCIe_Cable [16]







TX0p_SL8 [12]

TX0n_SL8 [12]

TX1p_SL8 [12]

TX1n_SL8 [12]

TX2p_SL8 [12]

TX2n_SL8 [12]

TX3p_SL8 [12]

TX3n_SL8 [12]TX0n_SL3 [10]

TX0p_SL3 [10]

TX0p_SL2 [9]



TX0n_SL2 [9]

TX0p_SL1 [9]

TX0n_SL1 [9]

RX0p_PCIe_Cable[16]

RX0n_PCIe_Cable[16]

RX0p_SL1[9]

RX0n_SL1[9]

RX0p_SL2[9]

RX0p_SL3[10]

RX0n_SL2[9]

RX0n_SL3[10]









RX4p_PCIe_Cable[16]

RX4n_PCIe_Cable[16]

RX5n_PCIe_Cable[16]

RX5p_PCIe_Cable[16]

RX6p_PCIe_Cable[16]

RX6n_PCIe_Cable[16]

RX7n_PCIe_Cable[16]

RX7p_PCIe_Cable[16]

TX0p_SL4 [10]

TX0n_SL4 [10]

TX1p_SL4 [10]

TX1n_SL4 [10]

TX2p_SL4 [10]

TX2n_SL4 [10]

TX3p_SL4 [10]

TX3n_SL4 [10]

TX0p_SL4 [10]

TX0n_SL4 [10]

TX0p_SL5 [11]

TX0p_SL6 [11]

TX0p_SL7 [12]

TX0n_SL5 [11]

TX0n_SL6 [11]

TX0n_SL7 [12]

RX0p_SL4[10]

RX0n_SL4[10]

RX2p_SL4[10]

RX3p_SL4[10]

RX1n_SL4[10]

RX2n_SL4[10]

RX3n_SL4[10]

RX1p_SL4[10]

RX0p_SL4[10]

RX0n_SL4[10]

RX0p_SL5[11]

RX0n_SL5[11]

RX0p_SL6[11]

RX0p_SL7[12]

RX0n_SL6[11]

RX0n_SL7[12]

TX0p_SL8 [12]

TX0n_SL8 [12]

TX0p_SL9 [13]

TX0p_SL10 [13]

TX0p_SL11 [14]

TX0n_SL9 [13]

TX0n_SL10 [13]

TX0n_SL11 [14]

RX0p_SL8[12]

RX0p_SL9[13]

RX0p_SL10[13]

RX0p_SL11[14]

RX0n_SL8[12]

RX0n_SL9[13]

RX0n_SL10[13]

RX0n_SL11[14]

Title


Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


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Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

TXRX

U75A

Receptacle 10 x 20

TXRX

U75A

Receptacle 10 x 20

TX0_S_pA3 TX0_D0_p B3TX0_D1_p A2TX0_D2_p B2

TX0_D0_n D3TX0_D1_n C2TX0_D2_n D2

TX0_S_nC3

TX1_S_pA7

TX1_S_nC7

TX1_D0_p B7TX1_D1_p A6TX1_D2_p B6








RX4_S2_nJ18 RX4_S1_nI18 RX4_S0_nJ19

RX4_S2_pH18 RX4_S1_pG18 RX4_S0_pH19

TX2_S_pA11

TX2_S_nC11

TX3_S_pA15

TX3_S_nC15

TX4_S_pA19

TX4_S_nC19









PRESENTF1CFGID0E1CFGID1E2

RX0_D_p G3

RX0_D_n I3

RX1_D_p G7

RX1_D_n I7

RX2_D_p G11

RX2_D_n I11

RX3_D_p G15

RX3_D_n I15

RX4_D_p G19

RX4_D_n I19

RN604R 4.7KRN604R 4.7K

1 2 3 45678

TXRX

U76A

Receptacle 10 x 20

TXRX

U76A

Receptacle 10 x 20



TX0_S_nC3

TX1_S_pA7

TX1_S_nC7











TX2_S_pA11

TX2_S_nC11

TX3_S_pA15

TX3_S_nC15

TX4_S_pA19

TX4_S_nC19










RX0_D_p G3

RX0_D_n I3

RX1_D_p G7

RX1_D_n I7

RX2_D_p G11

RX2_D_n I11

RX3_D_p G15

RX3_D_n I15

RX4_D_p G19

RX4_D_n I19

RN584R 4.7KRN584R 4.7K

1 2 3 45678

TXRX

U74A

Receptacle 10 x 20

TXRX

U74A

Receptacle 10 x 20



TX0_S_nC3

TX1_S_pA7

TX1_S_nC7











TX2_S_pA11

TX2_S_nC11

TX3_S_pA15

TX3_S_nC15

TX4_S_pA19

TX4_S_nC19










RX0_D_p G3

RX0_D_n I3

RX1_D_p G7

RX1_D_n I7

RX2_D_p G11

RX2_D_n I11

RX3_D_p G15

RX3_D_n I15

RX4_D_p G19

RX4_D_n I19

RN594R 4.7KRN594R 4.7K

1 2 3 45678

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MAN_FPGA_RST

FPGA_RESET

EN1 EN2

3.3VCC1

3.3VCC3.3VCC1

3.3VCC1 3.3VCC1

3.3VCC1

3.3VCC1

XILINX_VCC_CORE_1p2 XILINX_VCC_AUX_2p5

REG_VDD

REG_VDDREG_VDD

REG_VDD

REG_VDD

XILINX_VCC_AUX_2p5

XILINX_VCC_CORE_1p2

TDIODE_n [8]

TDIODE_p [8]

NVM_VDDQ [8]

SMBCLK_16[26]SMBDATA_16[26]

ALERT_n[26]OVERT_n[26]

EN_NVM_VDDQ[26]

FPGA_RESET [26]PS_Pwr_Good[4,26]

Title


Date: Sheet of

91-0131-000-A 0


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Date: Sheet of

91-0131-000-A 0


C


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Date: Sheet of

91-0131-000-A 0


C


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8619 Base Board RDK

Decoupling Caps for FPGA. Place1000pf close to the pins.Sprinkle 0.01uf around the chip.Sprinkle 1uf around the chip

- Make the common trace on NVM_VDDQ thicker - Make thetraces on pin 2 of both the Resistors Thicker - Populate1 to 3 connection on Both of these shunts

This Net should go to FPGA GSR Capable Pin

Inductor/Bead Should be Rated Above 3Amps Inductor/Bead Should be Rated Above 3Amps

L3

1uH

L3

1uH

C406

1000pF

C406

1000pF

C421

1000pF

C421

1000pF

L2

1uH

L2

1uH

C396

1uF

C396

1uF

C73

0.1uf

C73

0.1uf

R354

5K

R354

5K

C407

1000pF

C407

1000pF

C399

1000pF

C399

1000pF

C422

1000pF

C422

1000pF

U20

MAX6420

U20

MAX6420

RST IN3 VCC 5

SRT4 GND 2

RESET# 1

R346

10

R346

10

C397

1000pF

C397

1000pF

C156

22uF

C156

22uF

C381

1000pF

C381

1000pF

C389

1uF

C389

1uF

TP2Prototyping PadTP2Prototyping Pad

C423

1uF

C423

1uF

U78

MAX6658

U78

MAX6658

VCC1DXP 2

DXN 3

OVERT1#4GND 5

ALTER#6

SMBDATA7 SMBCLK8

C72

0.1uF

C72

0.1uF

C334

1000pF

C334

1000pF

C400

1000pF

C400

1000pF

R347200R347200

TP3Prototyping PadTP3Prototyping Pad

C398

1000pF

C398

1000pF

C79

1000pf

C79

1000pf

C153

0.001uF

C153

0.001uF

C384

0.01uF

C384

0.01uF

R35910K

R35910K

C424

0.01uF

C424

0.01uF

C382

1000pF

C382

1000pF

R340

0 Shunt

R340

0 Shunt

123

U21

NC7S08

U21

NC7S08

VCC5

GND 3

A1

B2

Y 4

R62 0R62 0

C378

1000pF

C378

1000pF

RN56

10K

RN56

10K

1 2 3 45678

C415

1000pF

C415

1000pF

C401

1000pF

C401

1000pF

C385

0.01uF

C385

0.01uF

C157

0.1uF

C157

0.1uF

C81

1uF NL

C81

1uF NL

C383

1000pF

C383

1000pF

C77

47uF

C77

47uF

C82

1000pf

C82

1000pf

R66

51K

R66

51KC154

0.1uF

C154

0.1uF

C416

1000pF

C416

1000pF

C391

1uF

C391

1uF

C386

0.01uF

C386

0.01uF

C402

1000pF

C402

1000pF

C78

0.1uF

C78

0.1uF

C417

1000pF

C417

1000pF

R3501K

R3501K

R64

5.1K

R64

5.1K

C2622200pFC2622200pF

C387

0.01uF

C387

0.01uF

C74

0.1uF

C74

0.1uF

C413

0.01uF

C413

0.01uF

S3

SW PUSHBUTTON

S3

SW PUSHBUTTON

1 342

R35620KR35620K

C408

1000pF

C408

1000pF

R35720KR35720K

C418

1000pF

C418

1000pF

C392

1uF

C392

1uF

R35120K

R35120K

R35520KR35520K

C76

0.1uF

C76

0.1uF

C403

1000pF

C403

1000pF

C388

0.01uF

C388

0.01uF

C163

0.022uF

C163

0.022uF

C261

.1uF

C261

.1uF

C379

1000pF

C379

1000pF

R339

0 Shunt

R339

0 Shunt

123

C160

150pf

C160

150pf

R278200R278200

R35220KR35220K

C83

0.1uF

C83

0.1uF

R67

10K

R67

10K

C393

1uF

C393

1uF

C259

1000pF

C259

1000pF

R34810KR34810K

C409

1000pF

C409

1000pF

R349

10K

R349

10K

C404

1000pF

C404

1000pF

C390

0.01uF

C390

0.01uF

R353

33

R353

33

C414

0.01uF

C414

0.01uF

C394

1000pF

C394

1000pF

U117

DUAL OUTPUT VOLTAGE REGULATOR

U117

DUAL OUTPUT VOLTAGE REGULATOR

VD

D3

PGND1_124

PGND1_225

PGND1_326

IN1_127

IN1_228

BST121 BST2 20

LX1_122

LX1_223

COMP130

FB131

REFIN2

SS132

PWRGD11

EN129 EN2 12

PWRGD2 8

SS2 9

FSYNC 7

FB2 10

COMP2 11

LX2_1 18

LX2_2 19

EP

33

IN2_1 13

IN2_2 14

PGND2_1 15

PGND2_2 16

PGND2_3 17V

DL

6

GN

D4

NC5

C84

10uF

C84

10uFC410

1000pF

C410

1000pF

C380

1000pF

C380

1000pF

C161

1uF

C161

1uF

TP4

EXT_NVM_VDDQ

TP4

EXT_NVM_VDDQ

C419

1000pF

C419

1000pF

R35820K

R35820K

JP5

HDR 2X2

JP5

HDR 2X2

1 1223 344

C412

1uF

C412

1uF

C80

330pf

C80

330pf

C260

1000pF

C260

1000pF

C86

0.1uF

C86

0.1uF

C405

1000pF

C405

1000pF

C395

1uF

C395

1uF

C420

1000pF

C420

1000pF

C162

1uF NL

C162

1uF NL

C75

10uF

C75

10uF

C411

0.01uF

C411

0.01uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of

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Date: Sheet of

91-0131-000-A 0


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Date: Sheet of

91-0131-000-A 0


C


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8619 Base Board RDK

U75B

Receptacle 10 x 20

U75B

Receptacle 10 x 20

GND0A1GND1A4GND2A5GND3A8GND4A9GND5A12GND6A13GND7A16GND8A17GND9A20GND10B1GND11B4GND12B5GND13B8GND14B9GND15B12GND16B13GND17B16GND18B17GND19B20GND20C1GND21C4GND22C5GND23C8GND24C9GND25C12GND26C13GND27C16GND28C17GND29C20GND30D1GND31D4GND32D5GND33D8GND34D9GND35D12GND36D13GND37D16GND38D17GND39D20GND40G1GND41G4GND42G5GND43G8GND44G9GND45G12GND46G13GND47G16GND48G17GND49G20GND50H1GND51H4GND52H5GND53H8GND54H9GND55H12GND56H13GND57H16GND58H17GND59H20GND60I1GND61I4GND62I5GND63I8GND64I9GND65I12GND66I13GND67I16GND68I17GND69I20GND70J1GND71J4GND72J5GND73J8GND74J9GND75J12GND76J13GND77J16GND78J17GND79J20

NC0 E20NC1 E11NC2 E10NC3 E9NC4 E8NC5 E7NC6 E6NC7 E5NC8 E4NC9 E3

NC10 E19NC11 E18NC12 E17NC13 E16NC14 E15NC15 E14NC16 E13NC17 E12NC18 F20NC19 F11NC20 F10NC21 F9NC22 F8NC23 F7NC24 F6NC25 F5NC26 F4NC27 F3NC28 F2NC29 F19NC30 F18NC31 F17NC32 F16NC33 F15NC34 F14NC35 F13NC36 F12

U74B

Receptacle 10 x 20

U74B

Receptacle 10 x 20




U76B

Receptacle 10 x 20

U76B

Receptacle 10 x 20




5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GPIO13 [8,26]

LN_GOOD_00_n [8,26]

GPIO12 [8,26]

UPSTRM_PSEL3[8]

SPARE0[8,26]

GPIO24[8,26]

SPARE1 [8,26]

GPIO25[8,26]

GPIO16[8,26]GPIO17[8,26]GPIO18[8,26]

GPIO05 [8,26]

GPIO20[8,26]GPIO21[8,26]GPIO22[8,26]

GPIO19[8,26]

PROCMON[8,26]

GPIO11 [8,26]

GPIO04 [8,26]

GPIO08[8,26]

GPIO06[8,26]GPIO07[8,26]

GPIO03 [8,26]GPIO02 [8,26]

I2C_ADDR0 [8]I2C_ADDR1 [8]

LN_GOOD_11_n [8,26]

DEBUG_SEL0[8]GPIO01 [8,26]

SPARE5[8,26]

LN_GOOD_10_n [8,26]

GPIO00 [8,26]

LN_GOOD_09_n [8,26]

STRAP_NT_P2PEN#[8,26]

LN_GOOD_08_n [8,26]

I2C_ADDR2[8]

GPIO10 [8,26]

LN_GOOD_15_n [8,26]LN_GOOD_14_n [8,26]LN_GOOD_13_n [8,26]LN_GOOD_12_n [8,26]

LN_GOOD_07_n [8,26]LN_GOOD_06_n [8,26]

GPIO30[8,26]

GPIO09 [8,26]

LN_GOOD_05_n [8,26]LN_GOOD_04_n [8,26]

STRAP_UPCFG_TR_EN#[8,26]

LN_GOOD_03_n [8,26]

GPIO26[8,26]

STRAP_SMBUSEN#[8,26]

GPIO15 [8,26]

LN_GOOD_02_n [8,26]

GPIO27[8,26]

GPIO23[8,26]

GPIO14 [8,26]

LN_GOOD_01_n [8,26]

GPIO29[8,26]

Title


Date: Sheet of

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Date: Sheet of

91-0131-000-A 0


C


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Date: Sheet of

91-0131-000-A 0


C


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8619 Base Board RDK

MICTOR CONNECTOR A

MICTOR CONNECTOR C

Note: The debug Circuit on this pageis for PLX use only

TV58Prototyping Pad TV58Prototyping Pad

TPV20 Prototyping PadTPV20 Prototyping PadTV61Prototyping Pad TV61Prototyping Pad


JP11

MICTOR 38 RECEPT

JP11

MICTOR 38 RECEPT

NC01 NC1 2GND03 NC2 4CLK/Q05 CLK/Q1 6L3:77 R1:7 8L3:69 R1:6 10L3:511 R1:5 12L3:413 R1:4 14L3:315 R1:3 16L3:217 R1:2 18L3:119 R1:1 20L3:021 R1:0 22L2:723 R0:7 24L2:625 R0:6 26L2:527 R0:5 28L2:429 R0:4 30L2:331 R0:3 32

R0:2 34R0:1 36R0:0 38

GND2 40GND4 42

L2:233L2:135L2:037GND139GND341GND543

TV62Prototyping Pad TV62Prototyping PadTPV21 Prototyping PadTPV21 Prototyping Pad


JP9

MICTOR 38 RECEPT

JP9

MICTOR 38 RECEPT

NC01 NC1 2GND03 NC2 4CLK/Q05 CLK/Q1 6L3:77 R1:7 8L3:69 R1:6 10L3:511 R1:5 12L3:413 R1:4 14L3:315 R1:3 16L3:217 R1:2 18L3:119 R1:1 20L3:021 R1:0 22L2:723 R0:7 24L2:625 R0:6 26L2:527 R0:5 28L2:429 R0:4 30L2:331 R0:3 32

R0:2 34R0:1 36R0:0 38

GND2 40GND4 42

L2:233L2:135L2:037GND139GND341GND543









JP10

PRB MODE INPUT HEADER

JP10

PRB MODE INPUT HEADER

GND01 2 233 4 455 6 677 GND2 899 10 101111 12 12GND113 14 141515 16 161717 18 181919 20 20








TV60Prototyping Pad TV60Prototyping PadTPV19 Prototyping PadTPV19 Prototyping Pad


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

UMODE5

UMODE7

UMODE3UMODE2

UMODE6

UMODE1

UMODE4

UMODE0

FPGA_CLK1 FPGA_CLKFPGA_CLK

FPGA_CLK

ROM_DOUT

ROM_OE_RESET_nROM_DOUT

ROM_OE_RESET_n

XILINX_VCC_CORE_1p2XILINX_VCC_AUX_2p5

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

3.3VCC1

XILINX_VCC_AUX_2p5

XILINX_VCC_AUX_2p5

XILINX_VCC_AUX_2p5

XILINX_VCC_AUX_2p5

GPIO11[8,25]GPIO12[8,25]

GPIO00[8,25]GPIO01[8,25]GPIO02[8,25]GPIO03[8,25]GPIO04[8,25]GPIO05[8,25]GPIO06[8,25]GPIO07[8,25]GPIO08[8,25]GPIO09[8,25]GPIO10[8,25]

GPIO13[8,25]GPIO14[8,25]GPIO15[8,25]GPIO16[8,25]GPIO17[8,25]GPIO18[8,25]GPIO19[8,25]GPIO20[8,25]GPIO21[8,25]GPIO22[8,25]GPIO23[8,25]GPIO24[8,25]GPIO25[8,25]

GPIO31[8]

GPIO26[8,25]GPIO27[8,25]GPIO28[8]GPIO29[8,25]GPIO30[8,25]

LN_GOOD_04_n[8,25]LN_GOOD_05_n[8,25]LN_GOOD_06_n[8,25]

LN_GOOD_00_n[8,25]LN_GOOD_01_n[8,25]LN_GOOD_02_n[8,25]LN_GOOD_03_n[8,25]

LN_GOOD_07_n[8,25]LN_GOOD_08_n[8,25]LN_GOOD_09_n[8,25]LN_GOOD_10_n[8,25]LN_GOOD_11_n[8,25]LN_GOOD_12_n[8,25]LN_GOOD_13_n[8,25]LN_GOOD_14_n[8,25]LN_GOOD_15_n[8,25]

RECP1_PRES_n[22]RECP1_CFGID0[22]RECP1_CFGID1[22]RECP0_PRES_n[22]RECP0_CFGID0[22]RECP0_CFGID1[22]

RECP2_PRES_n[22]RECP2_CFGID0[22]RECP2_CFGID1[22]

PRSNT_n_SL1[9]PRSNT_n_SL2[9]PRSNT_n_SL3[10]PRSNT_n_SL4[10]PRSNT_n_SL5[11]PRSNT_n_SL6[11]PRSNT_n_SL7[12]PRSNT_n_SL8[12,21]PRSNT_n_SL9[13]PRSNT_n_SL10[13]PRSNT_n_SL11[14]PRSNT_n_SL12[14]

PRSNT_n_SL13[15]PRSNT_n_SL14[15]PRSNT_n_SL15[16]

DEBUG_NORMAL_n[4]CPWRON[16]

PS_Pwr_Good[4,23]

FPGA_PEX_PERST_n[4]

LEDSET0_CLK [17]LEDSET0_DATA [17]








PERST_n_SL9 [13]PERST_n_SL10 [13]PERST_n_SL11 [14]PERST_n_SL12 [14]PERST_n_SL13 [15]PERST_n_SL14 [15]PERST_n_SL15 [16]

SPARE0 [8,25]SPARE1 [8,25]STRAP_NT_P2PEN# [8,25]STRAP_SMBUSEN# [8,25]STRAP_UPCFG_TR_EN# [8,25]SPARE5 [8,25]

CLKEN_SL8 [21]

I2C_SCL0 [8]I2C_SDA0 [8]

PROCMON [8,25]PEX_INTA_n [8]FATAL_ERR_n [8]

WAKE_n [9,10,11,12,13,14,15,16]PEX_PERST_n [8,17,18,19,21]

PERST_n_SL5 [11]PERST_n_SL6 [11]PERST_n_SL7 [12]

PERST_n_SL5 [11]

PERST_n_SL1 [9]PERST_n_SL2 [9]PERST_n_SL3 [10]PERST_n_SL4 [10]

ALERT_n [23]OVERT_n [23]

SMBDATA_16 [23]SMBCLK_16 [23]EN_NVM_VDDQ [23]

FPGA_RESET[23]

PS_ON_n [4]

SHPC_INT_n [8,21]CPRSNTN [16]

Title


Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com



Date: Sheet of

91-0131-000-A 0


C


www.plxtech.com

8619 Base Board RDK

TP33TP33

R341 33R341 33

R78

5.1K

R78

5.1K

XC3S200-4FTG256C

4 OF 12

U115D

XC3S200-4FTG256C

XC3S200-4FTG256C

4 OF 12

U115D

XC3S200-4FTG256C

IO_6K15IO_L01N_3_VRP_3P16IO_L01P_3_VRN_3R16IO_L16N_3P15IO_L16P_3P14IO_L17N_3N16IO_L17P_3_VREF_3N15IO_L19N_3M14IO_L19P_3N14IO_L20N_3M16IO_L20P_3M15IO_L21N_3L13IO_L21P_3M13 IO_L22N_3 L15IO_L22P_3 L14IO_L23N_3 K12IO_L23P_3_VREF_3 L12IO_L24N_3 K14IO_L24P_3 K13IO_L39N_3 J14IO_L39P_3 J13IO_L40N_3_VREF_3 J16IO_L40P_3 K16VCCO_3_0 J11VCCO_3_1 J12VCCO_3_2 K11

TP19TP19

TP20TP20

TP30TP30

XC3S200-4FTG256C

8 OF 12

U115H

XC3S200-4FTG256C

XC3S200-4FTG256C

8 OF 12

U115H

XC3S200-4FTG256C

IO_13G2IO_L01N_7_VRP_7C1IO_L01P_7_VRN_7B1IO_L16N_7C2IO_L16P_7_VREF_7C3IO_L17N_7D1IO_L17P_7D2IO_L19N_7_VREF_7E3IO_L19P_7D3IO_L20N_7E1IO_L20P_7E2IO_L21N_7F4IO_L21P_7E4 IO_L22N_7 F2IO_L22P_7 F3IO_L23N_7 G5IO_L23P_7 F5IO_L24N_7 G3IO_L24P_7 G4IO_L39N_7 H3IO_L39P_7 H4IO_L40N_7_VREF_7 H1IO_L40P_7 G1VCCO_7_0 G6VCCO_7_1 H5VCCO_7_2 H6

J12

JTAG HEADER 7x2

J12

JTAG HEADER 7x2

GND0 1GND1 3GND2 5GND3 7GND4 9GND5 11GND6 13

VREF2SS_PROG_TMS4SCK_CCLK_TCK6MISO_DONE_TDO8MOSI_DIN_TDI10NC_NC_NC12NC_INIT_NC14

XC3S200-4FTG256C

9 OF 12

U115I

XC3S200-4FTG256C

XC3S200-4FTG256C

9 OF 12

U115I

XC3S200-4FTG256C

GND0A1GND1A16GND2B2GND3B9GND4B15GND5F6GND6F11GND7G7GND8G8GND9G9GND10G10GND11H2GND12H7GND13H8GND14H9GND15H10 GND16 J7GND17 J8GND18 J9GND19 J10GND20 J15GND21 K7GND22 K8GND23 K9GND24 K10GND25 L6GND26 L11GND27 R2GND28 R8GND29 R15GND30 T1GND31 T16

RN114R 4.7K

RN114R 4.7K

1 2 3 45678

TP21TP21

TP12

ROM_OE_RESET_n

TP12

ROM_OE_RESET_n

R77

5.1K

R77

5.1K

RN134R 4.7K

RN134R 4.7K

1 2 3 45678

TP34TP34

XC3S200-4FTG256C

6 OF 12

U115F

XC3S200-4FTG256C

XC3S200-4FTG256C

6 OF 12

U115F

XC3S200-4FTG256C

IO_9N5IO_10P7IO_11T5IO_VREF_5T8IO_L01N_5_RDWR_BT3IO_L01P_5_CS_BR3IO_L10N_5_VRP_5T4IO_L10P_5_VRN_5R4IO_L27N_5_VREF_5R5IO_L27P_5P5IO_L28N_5_D6N6IO_L28P_5_D7M6 IO_L29N_5 R6IO_L29P_5_VREF_5 P6IO_L30N_5 N7IO_L30P_5 M7IO_L31N_5_D4 T7IO_L31P_5_D5 R7IO_L32N_5_GCLK3 P8IO_L32P_5_GCLK2 N8

VCCO_5_0 L7VCCO_5_1 L8VCCO_5_2 M8

TP31TP31

R342 33R342 33

TP10ROM_CEO_nTP10ROM_CEO_n

TP15TP15

XC3S200-4FTG256C

1 OF 12

U115A

XC3S200-4FTG256C

XC3S200-4FTG256C

1 OF 12

U115A

XC3S200-4FTG256C

IO_0A5IO_1A7 IO_VREF_0_0 A3

IO_VREF_0_1 D5

IO_L01N_0_VRP_0 B4IO_L01P_0_VRN_0 A4IO_L25N_0C5IO_L25P_0B5IO_L27N_0E6IO_L27P_0D6IO_L28N_0C6IO_L28P_0B6IO_L29N_0E7IO_L29P_0D7IO_L30N_0C7IO_L30P_0B7 IO_L31N_0 D8IO_L31P_0_VREF_0 C8IO_L32N_0_GCLK7 B8IO_L32P_0_GCLK6 A8

VCCO_0_0 E8VCCO_0_1 F7VCCO_0_2 F8

TP35TP35

TP28TP28

TP32TP32

TP29TP29TP5

FPGA CLKTP5

FPGA CLK

TP8 ROM_DOUTTP8 ROM_DOUT

TP39TP39

XC3S200-4FTG256C

3 OF 12

U115C

XC3S200-4FTG256C

XC3S200-4FTG256C

3 OF 12

U115C

XC3S200-4FTG256C

IO_5G16IO_L01N_2_VRP_2B16IO_L01P_2_VRN_2C16IO_L16N_2C15IO_L16P_2D14IO_L17N_2D15IO_L17P_2_VREF_2D16IO_L19N_2E13IO_L19P_2E14IO_L20N_2E15IO_L20P_2E16IO_L21N_2F12IO_L21P_2F13 IO_L22N_2 F14IO_L22P_2 F15IO_L23N_2_VREF_2 G12IO_L23P_2 G13IO_L24N_2 G14IO_L24P_2 G15IO_L39N_2 H13IO_L39P_2 H14IO_L40N_2 H15IO_L40P_2_VREF_2 H16VCCO_2_0 G11VCCO_2_1 H11VCCO_2_2 H12

TP25TP25

TP18TP18

TP36TP36

XC3S200-4FTG256C

10 OF 12

U115J

XC3S200-4FTG256C

XC3S200-4FTG256C

10 OF 12

U115J

XC3S200-4FTG256C

VCCAUX0A6VCCAUX1A11VCCAUX2F1VCCAUX3F16VCCAUX4L1VCCAUX5L16VCCAUX6T6VCCAUX7T11 VCCINT0 D4VCCINT1 D13VCCINT2 E5VCCINT3 E12VCCINT4 M5VCCINT5 M12VCCINT6 N4VCCINT7 N13

C155

1000pF

C155

1000pF

XCF01SVOG20CU116

XCF01SVOG20C

XCF01SVOG20CU116

XCF01SVOG20C

D0 1

DNC02

CLK3TDI4TMS5TCK6

CF 7

OE_RESET 8

DNC19

CE10

GND 11

DNC212

CEO 13

DNC314DNC415DNC516

TDO 17

VCCINT 18VCCO 19VCCJ 20

TP27TP27

TP26TP26

TP24TP24

TP22TP22

TP40TP40

XC3S200-4FTG256C

5 OF 12

U115E

XC3S200-4FTG256C

XC3S200-4FTG256C

5 OF 12

U115E

XC3S200-4FTG256C

IO_7T12IO_8T14IO_VREF_4_0N12IO_VREF_4_1P13IO_VREF_4_2T10IO_L01N_4_VRP_4R13IO_L01P_4_VRN_4T13IO_L25N_4P12IO_L25P_4R12IO_L27N_4_DIN_D0M11IO_L27P_4_D1N11IO_L28N_4P11IO_L28P_4R11 IO_L29N_4 M10IO_L29P_4 N10IO_L30N_4_D2 P10IO_L30P_4_D3 R10IO_L31N_4_INIT_B N9IO_L31P_4_DOUT_BUSY P9IO_L32N_4_GCLK1 R9IO_L32P_4_GCLK0 T9

VCCO_4_0 L9VCCO_4_1 L10VCCO_4_2 M9

TP14TP14

TP6HOT_SWAP_EN TP6HOT_SWAP_EN

TP23TP23

TP38TP38

TP37TP37

TP17TP17


1234

8765

XC3S200-4FTG256C

11 OF 12

U115K

XC3S200-4FTG256C

XC3S200-4FTG256C

11 OF 12

U115K

XC3S200-4FTG256C

CCLKT15DONER14HSWAP_ENC4

M0 P3M1 T2M2 P4PROG_B B3

Y4

100MHz

Y4

100MHz

VCC4

OUT 3

GND 2

EN1

TP41TP41

R80

5.1K

R80

5.1K

XC3S200-4FTG256C

7 OF 12

U115G

XC3S200-4FTG256C

XC3S200-4FTG256C

7 OF 12

U115G

XC3S200-4FTG256C

IO_12K1IO_L01N_6_VRP_6R1IO_L01P_6_VRN_6P1IO_L16N_6P2IO_L16P_6N3IO_L17N_6N2IO_L17P_6_VREF_6N1IO_L19N_6M4IO_L19P_6M3IO_L20N_6M2IO_L20P_6M1IO_L21N_6L5IO_L21P_6L4 IO_L22N_6 L3IO_L22P_6 L2IO_L23N_6 K5IO_L23P_6 K4IO_L24N_6_VREF_6 K3IO_L24P_6 K2IO_L39N_6 J4IO_L39P_6 J3IO_L40N_6 J2IO_L40P_6_VREF_6 J1VCCO_6_0 J5VCCO_6_1 J6VCCO_6_2 K6XC3S200-4FTG256C

2 OF 12

U115B

XC3S200-4FTG256C

XC3S200-4FTG256C

2 OF 12

U115B

XC3S200-4FTG256C

IO_2A9IO_3A12IO_4C10

IO_VREF_1 D12IO_L01N_1_VRP_1A14IO_L01P_1_VRN_1B14IO_L10N_1_VREF_1A13IO_L10P_1B13IO_L27N_1B12IO_L27P_1C12IO_L28N_1D11IO_L28P_1E11IO_L29N_1B11IO_L29P_1C11 IO_L30N_1 D10IO_L30P_1 E10IO_L31N_1_VREF_1 A10IO_L31P_1 B10IO_L32N_1_GCLK5 C9IO_L32P_1_GCLK4 D9

VCCO_1_0 E9VCCO_1_1 F9VCCO_1_2 F10

TP9TP9


1234

8765

TP42TP42

R81

5.1K

R81

5.1K

TP7TP7

XC3S200-4FTG256C

12 OF 12

U115L

XC3S200-4FTG256C

XC3S200-4FTG256C

12 OF 12

U115L

XC3S200-4FTG256C

TCKC14TDIA2 TDO A15TMS C13

J13Header 3x2

J13Header 3x2

11

22

33

44

55

66

TP13TP13

TP16TP16

TP11NC_INIT_NC TP11NC_INIT_NC

R70

5.1K

R70

5.1K

R71

5.1K

R71

5.1K

R72

5.1K

R72

5.1K

pex 8619ba base board rdk - broadcom inc.this document contains plx confidential and proprietary...

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